1 //==- HexagonRegisterInfo.cpp - Hexagon Register Information -----*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
16 #include "HexagonRegisterInfo.h"
17 #include "HexagonSubtarget.h"
18 #include "HexagonTargetMachine.h"
19 #include "HexagonMachineFunctionInfo.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/MC/MachineLocation.h"
26 #include "llvm/Target/TargetInstrInfo.h"
27 #include "llvm/Type.h"
28 #include "llvm/ADT/BitVector.h"
29 #include "llvm/ADT/STLExtras.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/CodeGen/MachineFunctionPass.h"
37 #include "llvm/Function.h"
41 HexagonRegisterInfo::HexagonRegisterInfo(HexagonSubtarget &st,
42 const HexagonInstrInfo &tii)
43 : HexagonGenRegisterInfo(Hexagon::R31),
48 const unsigned* HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction
51 static const unsigned CalleeSavedRegsV2[] = {
52 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
54 static const unsigned CalleeSavedRegsV3[] = {
55 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
56 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
57 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
60 switch(Subtarget.getHexagonArchVersion()) {
61 case HexagonSubtarget::V2:
62 return CalleeSavedRegsV2;
64 case HexagonSubtarget::V3:
65 case HexagonSubtarget::V4:
66 return CalleeSavedRegsV3;
69 const char *ErrorString =
70 "Callee saved registers requested for unknown archtecture version";
71 llvm_unreachable(ErrorString);
75 BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF)
77 BitVector Reserved(getNumRegs());
78 Reserved.set(HEXAGON_RESERVED_REG_1);
79 Reserved.set(HEXAGON_RESERVED_REG_2);
80 Reserved.set(Hexagon::R29);
81 Reserved.set(Hexagon::R30);
82 Reserved.set(Hexagon::R31);
83 Reserved.set(Hexagon::D14);
84 Reserved.set(Hexagon::D15);
85 Reserved.set(Hexagon::LC0);
86 Reserved.set(Hexagon::LC1);
87 Reserved.set(Hexagon::SA0);
88 Reserved.set(Hexagon::SA1);
93 const TargetRegisterClass* const*
94 HexagonRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
95 static const TargetRegisterClass * const CalleeSavedRegClassesV2[] = {
96 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
97 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
99 static const TargetRegisterClass * const CalleeSavedRegClassesV3[] = {
100 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
101 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
102 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
103 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
104 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
105 &Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
108 switch(Subtarget.getHexagonArchVersion()) {
109 case HexagonSubtarget::V2:
110 return CalleeSavedRegClassesV2;
112 case HexagonSubtarget::V3:
113 case HexagonSubtarget::V4:
114 return CalleeSavedRegClassesV3;
117 const char *ErrorString =
118 "Callee saved register classes requested for unknown archtecture version";
119 llvm_unreachable(ErrorString);
123 void HexagonRegisterInfo::
124 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
125 MachineBasicBlock::iterator I) const {
126 MachineInstr &MI = *I;
128 if (MI.getOpcode() == Hexagon::ADJCALLSTACKDOWN) {
129 // Hexagon_TODO: add code
130 } else if (MI.getOpcode() == Hexagon::ADJCALLSTACKUP) {
131 // Hexagon_TODO: add code
133 assert(0 && "Cannot handle this call frame pseudo instruction");
138 void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
139 int SPAdj, RegScavenger *RS) const {
142 // Hexagon_TODO: Do we need to enforce this for Hexagon?
143 assert(SPAdj == 0 && "Unexpected");
147 MachineInstr &MI = *II;
148 while (!MI.getOperand(i).isFI()) {
150 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
153 int FrameIndex = MI.getOperand(i).getIndex();
155 // Addressable stack objects are accessed using neg. offsets from %fp.
156 MachineFunction &MF = *MI.getParent()->getParent();
157 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
158 MachineFrameInfo &MFI = *MF.getFrameInfo();
160 unsigned FrameReg = getFrameRegister(MF);
161 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
162 if (!TFI->hasFP(MF)) {
163 // We will not reserve space on the stack for the lr and fp registers.
164 Offset -= 2 * Hexagon_WordSize;
167 const unsigned FrameSize = MFI.getStackSize();
169 if (!MFI.hasVarSizedObjects() &&
170 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) &&
171 !TII.isSpillPredRegOp(&MI)) {
172 // Replace frame index with a stack pointer reference.
173 MI.getOperand(i).ChangeToRegister(getStackRegister(), false, false, true);
174 MI.getOperand(i+1).ChangeToImmediate(FrameSize+Offset);
176 // Replace frame index with a frame pointer reference.
177 if (!TII.isValidOffset(MI.getOpcode(), Offset)) {
179 // If the offset overflows, then correct it.
181 // For loads, we do not need a reserved register
182 // r0 = memw(r30 + #10000) to:
184 // r0 = add(r30, #10000)
186 if ( (MI.getOpcode() == Hexagon::LDriw) ||
187 (MI.getOpcode() == Hexagon::LDrid) ||
188 (MI.getOpcode() == Hexagon::LDrih) ||
189 (MI.getOpcode() == Hexagon::LDriuh) ||
190 (MI.getOpcode() == Hexagon::LDrib) ||
191 (MI.getOpcode() == Hexagon::LDriub) ) {
192 unsigned dstReg = (MI.getOpcode() == Hexagon::LDrid) ?
193 *getSubRegisters(MI.getOperand(0).getReg()) :
194 MI.getOperand(0).getReg();
196 // Check if offset can fit in addi.
197 if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) {
198 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
199 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
200 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
201 TII.get(Hexagon::ADD_rr),
202 dstReg).addReg(FrameReg).addReg(dstReg);
204 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
205 TII.get(Hexagon::ADD_ri),
206 dstReg).addReg(FrameReg).addImm(Offset);
209 MI.getOperand(i).ChangeToRegister(dstReg, false, false, true);
210 MI.getOperand(i+1).ChangeToImmediate(0);
211 } else if ((MI.getOpcode() == Hexagon::STriw) ||
212 (MI.getOpcode() == Hexagon::STrid) ||
213 (MI.getOpcode() == Hexagon::STrih) ||
214 (MI.getOpcode() == Hexagon::STrib) ||
215 (MI.getOpcode() == Hexagon::STriwt)) {
216 // For stores, we need a reserved register. Change
217 // memw(r30 + #10000) = r0 to:
219 // rs = add(r30, #10000);
221 unsigned resReg = HEXAGON_RESERVED_REG_1;
223 // Check if offset can fit in addi.
224 if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) {
225 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
226 TII.get(Hexagon::CONST32_Int_Real), resReg).addImm(Offset);
227 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
228 TII.get(Hexagon::ADD_rr),
229 resReg).addReg(FrameReg).addReg(resReg);
231 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
232 TII.get(Hexagon::ADD_ri),
233 resReg).addReg(FrameReg).addImm(Offset);
235 MI.getOperand(i).ChangeToRegister(resReg, false, false, true);
236 MI.getOperand(i+1).ChangeToImmediate(0);
237 } else if (TII.isMemOp(&MI)) {
238 unsigned resReg = HEXAGON_RESERVED_REG_1;
239 if (!MFI.hasVarSizedObjects() &&
240 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset))) {
241 MI.getOperand(i).ChangeToRegister(getStackRegister(), false, false,
243 MI.getOperand(i+1).ChangeToImmediate(FrameSize+Offset);
244 } else if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) {
245 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
246 TII.get(Hexagon::CONST32_Int_Real), resReg).addImm(Offset);
247 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
248 TII.get(Hexagon::ADD_rr),
249 resReg).addReg(FrameReg).addReg(resReg);
250 MI.getOperand(i).ChangeToRegister(resReg, false, false, true);
251 MI.getOperand(i+1).ChangeToImmediate(0);
253 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
254 TII.get(Hexagon::ADD_ri),
255 resReg).addReg(FrameReg).addImm(Offset);
256 MI.getOperand(i).ChangeToRegister(resReg, false, false, true);
257 MI.getOperand(i+1).ChangeToImmediate(0);
260 unsigned dstReg = MI.getOperand(0).getReg();
261 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
262 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
263 BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
264 TII.get(Hexagon::ADD_rr),
265 dstReg).addReg(FrameReg).addReg(dstReg);
266 // Can we delete MI??? r2 = add (r2, #0).
267 MI.getOperand(i).ChangeToRegister(dstReg, false, false, true);
268 MI.getOperand(i+1).ChangeToImmediate(0);
271 // If the offset is small enough to fit in the immediate field, directly
273 MI.getOperand(i).ChangeToRegister(FrameReg, false);
274 MI.getOperand(i+1).ChangeToImmediate(Offset);
280 unsigned HexagonRegisterInfo::getRARegister() const {
284 unsigned HexagonRegisterInfo::getFrameRegister(const MachineFunction
286 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
287 if (TFI->hasFP(MF)) {
294 unsigned HexagonRegisterInfo::getFrameRegister() const {
298 unsigned HexagonRegisterInfo::getStackRegister() const {
302 void HexagonRegisterInfo::getInitialFrameState(std::vector<MachineMove>
305 // VirtualFP = (R30 + #0).
306 unsigned FPReg = getFrameRegister();
307 MachineLocation Dst(MachineLocation::VirtualFP);
308 MachineLocation Src(FPReg, 0);
309 Moves.push_back(MachineMove(0, Dst, Src));
312 unsigned HexagonRegisterInfo::getEHExceptionRegister() const {
313 assert(0 && "What is the exception register");
317 unsigned HexagonRegisterInfo::getEHHandlerRegister() const {
318 assert(0 && "What is the exception handler register");
322 #define GET_REGINFO_TARGET_DESC
323 #include "HexagonGenRegisterInfo.inc"