1 //===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #include "HexagonRegisterInfo.h"
17 #include "HexagonMachineFunctionInfo.h"
18 #include "HexagonSubtarget.h"
19 #include "HexagonTargetMachine.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/MC/MachineLocation.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetOptions.h"
42 HexagonRegisterInfo::HexagonRegisterInfo()
43 : HexagonGenRegisterInfo(Hexagon::R31) {}
46 bool HexagonRegisterInfo::isEHReturnCalleeSaveReg(unsigned R) const {
47 return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 ||
48 R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1;
51 bool HexagonRegisterInfo::isCalleeSaveReg(unsigned Reg) const {
52 return Hexagon::R16 <= Reg && Reg <= Hexagon::R27;
57 HexagonRegisterInfo::getCallerSavedRegs(const MachineFunction *MF) const {
58 static const MCPhysReg CallerSavedRegsV4[] = {
59 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
60 Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,
61 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
65 auto &HST = static_cast<const HexagonSubtarget&>(MF->getSubtarget());
66 switch (HST.getHexagonArchVersion()) {
67 case HexagonSubtarget::V4:
68 case HexagonSubtarget::V5:
69 return CallerSavedRegsV4;
72 "Callee saved registers requested for unknown archtecture version");
77 HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
78 static const MCPhysReg CalleeSavedRegsV3[] = {
79 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
80 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
81 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
84 switch (MF->getSubtarget<HexagonSubtarget>().getHexagonArchVersion()) {
85 case HexagonSubtarget::V4:
86 case HexagonSubtarget::V5:
87 return CalleeSavedRegsV3;
89 llvm_unreachable("Callee saved registers requested for unknown architecture "
93 BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF)
95 BitVector Reserved(getNumRegs());
96 Reserved.set(HEXAGON_RESERVED_REG_1);
97 Reserved.set(HEXAGON_RESERVED_REG_2);
98 Reserved.set(Hexagon::R29);
99 Reserved.set(Hexagon::R30);
100 Reserved.set(Hexagon::R31);
101 Reserved.set(Hexagon::D14);
102 Reserved.set(Hexagon::D15);
103 Reserved.set(Hexagon::LC0);
104 Reserved.set(Hexagon::LC1);
105 Reserved.set(Hexagon::SA0);
106 Reserved.set(Hexagon::SA1);
111 void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
112 int SPAdj, unsigned FIOp,
113 RegScavenger *RS) const {
115 // Hexagon_TODO: Do we need to enforce this for Hexagon?
116 assert(SPAdj == 0 && "Unexpected");
118 MachineInstr &MI = *II;
120 MachineBasicBlock &MB = *MI.getParent();
121 MachineFunction &MF = *MB.getParent();
122 MachineFrameInfo &MFI = *MF.getFrameInfo();
123 auto &HST = static_cast<const HexagonSubtarget&>(MF.getSubtarget());
124 auto &HII = *HST.getInstrInfo();
125 auto &HFI = *HST.getFrameLowering();
127 int FI = MI.getOperand(FIOp).getIndex();
128 int Offset = MFI.getObjectOffset(FI) + MI.getOperand(FIOp+1).getImm();
129 bool HasAlloca = MFI.hasVarSizedObjects();
130 bool HasAlign = needsStackRealignment(MF);
132 // XXX: Fixed objects cannot be accessed through SP if there are aligned
133 // objects in the local frame, or if there are dynamically allocated objects.
134 // In such cases, there has to be FP available.
135 if (!HFI.hasFP(MF)) {
136 assert(!HasAlloca && !HasAlign && "This function must have frame pointer");
137 // We will not reserve space on the stack for the lr and fp registers.
141 unsigned SP = getStackRegister(), FP = getFrameRegister();
143 if (MachineInstr *AI = HFI.getAlignaInstr(MF))
144 AP = AI->getOperand(0).getReg();
145 unsigned FrameSize = MFI.getStackSize();
147 // Special handling of dbg_value instructions and INLINEASM.
148 if (MI.isDebugValue() || MI.isInlineAsm()) {
149 MI.getOperand(FIOp).ChangeToRegister(SP, false /*isDef*/);
150 MI.getOperand(FIOp+1).ChangeToImmediate(Offset+FrameSize);
154 bool UseFP = false, UseAP = false; // Default: use SP.
155 if (MFI.isFixedObjectIndex(FI) || MFI.isObjectPreAllocated(FI)) {
156 UseFP = HasAlloca || HasAlign;
166 unsigned Opc = MI.getOpcode();
167 bool ValidSP = HII.isValidOffset(Opc, FrameSize+Offset);
168 bool ValidFP = HII.isValidOffset(Opc, Offset);
170 // Calculate the actual offset in the instruction.
171 int64_t RealOffset = Offset;
172 if (!UseFP && !UseAP)
173 RealOffset = FrameSize+Offset;
176 case Hexagon::TFR_FIA:
177 MI.setDesc(HII.get(Hexagon::A2_addi));
178 MI.getOperand(FIOp).ChangeToImmediate(RealOffset);
179 MI.RemoveOperand(FIOp+1);
181 case Hexagon::TFR_FI:
182 // Set up the instruction for updating below.
183 MI.setDesc(HII.get(Hexagon::A2_addi));
201 MI.getOperand(FIOp).ChangeToRegister(BP, false);
202 MI.getOperand(FIOp+1).ChangeToImmediate(RealOffset);
207 const Function *F = MF.getFunction();
208 dbgs() << "In function ";
209 if (F) dbgs() << F->getName();
210 else dbgs() << "<?>";
211 dbgs() << ", BB#" << MB.getNumber() << "\n" << MI;
213 llvm_unreachable("Unhandled instruction");
217 unsigned HexagonRegisterInfo::getRARegister() const {
222 unsigned HexagonRegisterInfo::getFrameRegister(const MachineFunction
224 const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
231 unsigned HexagonRegisterInfo::getFrameRegister() const {
236 unsigned HexagonRegisterInfo::getStackRegister() const {
242 HexagonRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
243 return MF.getSubtarget().getFrameLowering()->hasFP(MF);
248 HexagonRegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
249 const MachineFrameInfo *MFI = MF.getFrameInfo();
250 return MFI->getMaxAlignment() > 8;
254 unsigned HexagonRegisterInfo::getFirstCallerSavedNonParamReg() const {
259 #define GET_REGINFO_TARGET_DESC
260 #include "HexagonGenRegisterInfo.inc"