1 //==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef HexagonREGISTERINFO_H
16 #define HexagonREGISTERINFO_H
18 #include "llvm/Target/TargetRegisterInfo.h"
19 #define GET_REGINFO_HEADER
20 #include "HexagonGenRegisterInfo.inc"
21 #include "llvm/MC/MachineLocation.h"
24 // We try not to hard code the reserved registers in our code,
25 // so the following two macros were defined. However, there
26 // are still a few places that R11 and R10 are hard wired.
27 // See below. If, in the future, we decided to change the reserved
28 // register. Don't forget changing the following places.
30 // 1. the "Defs" set of STriw_pred in HexagonInstrInfo.td
31 // 2. the "Defs" set of LDri_pred in HexagonInstrInfo.td
32 // 3. the definition of "IntRegs" in HexagonRegisterInfo.td
33 // 4. the definition of "DoubleRegs" in HexagonRegisterInfo.td
35 #define HEXAGON_RESERVED_REG_1 Hexagon::R10
36 #define HEXAGON_RESERVED_REG_2 Hexagon::R11
40 class HexagonSubtarget;
41 class HexagonInstrInfo;
44 struct HexagonRegisterInfo : public HexagonGenRegisterInfo {
45 HexagonSubtarget &Subtarget;
46 const HexagonInstrInfo &TII;
48 HexagonRegisterInfo(HexagonSubtarget &st, const HexagonInstrInfo &tii);
50 /// Code Generation virtual methods...
51 const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
53 const TargetRegisterClass* const* getCalleeSavedRegClasses(
54 const MachineFunction *MF = 0) const;
56 BitVector getReservedRegs(const MachineFunction &MF) const;
58 void eliminateCallFramePseudoInstr(MachineFunction &MF,
59 MachineBasicBlock &MBB,
60 MachineBasicBlock::iterator I) const;
62 void eliminateFrameIndex(MachineBasicBlock::iterator II,
63 int SPAdj, RegScavenger *RS = NULL) const;
65 /// determineFrameLayout - Determine the size of the frame and maximum call
67 void determineFrameLayout(MachineFunction &MF) const;
69 /// requiresRegisterScavenging - returns true since we may need scavenging for
70 /// a temporary register when generating hardware loop instructions.
71 bool requiresRegisterScavenging(const MachineFunction &MF) const {
75 // Debug information queries.
76 unsigned getRARegister() const;
77 unsigned getFrameRegister(const MachineFunction &MF) const;
78 unsigned getFrameRegister() const;
79 void getInitialFrameState(std::vector<MachineMove> &Moves) const;
80 unsigned getStackRegister() const;
82 // Exception handling queries.
83 unsigned getEHExceptionRegister() const;
84 unsigned getEHHandlerRegister() const;
87 } // end namespace llvm