1 //==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H
16 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H
18 #include "llvm/MC/MachineLocation.h"
19 #include "llvm/Target/TargetRegisterInfo.h"
21 #define GET_REGINFO_HEADER
22 #include "HexagonGenRegisterInfo.inc"
25 // We try not to hard code the reserved registers in our code,
26 // so the following two macros were defined. However, there
27 // are still a few places that R11 and R10 are hard wired.
28 // See below. If, in the future, we decided to change the reserved
29 // register. Don't forget changing the following places.
31 // 1. the "Defs" set of STriw_pred in HexagonInstrInfo.td
32 // 2. the "Defs" set of LDri_pred in HexagonInstrInfo.td
33 // 3. the definition of "IntRegs" in HexagonRegisterInfo.td
34 // 4. the definition of "DoubleRegs" in HexagonRegisterInfo.td
36 #define HEXAGON_RESERVED_REG_1 Hexagon::R10
37 #define HEXAGON_RESERVED_REG_2 Hexagon::R11
40 class HexagonRegisterInfo : public HexagonGenRegisterInfo {
42 HexagonRegisterInfo();
44 /// Code Generation virtual methods...
45 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF)
49 BitVector getReservedRegs(const MachineFunction &MF) const override;
51 void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
52 unsigned FIOperandNum, RegScavenger *RS = nullptr) const override;
54 /// Returns true since we may need scavenging for a temporary register
55 /// when generating hardware loop instructions.
56 bool requiresRegisterScavenging(const MachineFunction &MF) const override {
60 /// Returns true. Spill code for predicate registers might need an extra
62 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
66 bool needsStackRealignment(const MachineFunction &MF) const override;
68 /// Returns true if the frame pointer is valid.
69 bool useFPForScavengingIndex(const MachineFunction &MF) const override;
71 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
75 // Debug information queries.
76 unsigned getRARegister() const;
77 unsigned getFrameRegister(const MachineFunction &MF) const override;
78 unsigned getFrameRegister() const;
79 unsigned getStackRegister() const;
81 const MCPhysReg *getCallerSavedRegs(const MachineFunction *MF) const;
83 unsigned getFirstCallerSavedNonParamReg() const;
85 bool isEHReturnCalleeSaveReg(unsigned Reg) const;
86 bool isCalleeSaveReg(unsigned Reg) const;
89 } // end namespace llvm