1 //===-- HexagonRegisterInfo.td - Hexagon Register defs -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the Hexagon register file.
12 //===----------------------------------------------------------------------===//
14 let Namespace = "Hexagon" in {
16 class HexagonReg<bits<5> num, string n> : Register<n> {
18 let HWEncoding{4-0} = num;
21 class HexagonDoubleReg<bits<5> num, string n, list<Register> subregs> :
22 RegisterWithSubRegs<n, subregs> {
24 let HWEncoding{4-0} = num;
27 // Registers are identified with 5-bit ID numbers.
28 // Ri - 32-bit integer registers.
29 class Ri<bits<5> num, string n> : HexagonReg<num, n> {
33 // Rf - 32-bit floating-point registers.
34 class Rf<bits<5> num, string n> : HexagonReg<num, n> {
39 // Rd - 64-bit registers.
40 class Rd<bits<5> num, string n, list<Register> subregs> :
41 HexagonDoubleReg<num, n, subregs> {
43 let SubRegs = subregs;
46 // Rp - predicate registers
47 class Rp<bits<5> num, string n> : HexagonReg<num, n> {
51 // Rc - control registers
52 class Rc<bits<5> num, string n> : HexagonReg<num, n> {
56 // Rj - aliased integer registers
57 class Rj<string n, Ri R>: HexagonReg<R.Num, n> {
62 def subreg_loreg : SubRegIndex<32>;
63 def subreg_hireg : SubRegIndex<32, 32>;
67 def R#I : Ri<I, "r"#I>, DwarfRegNum<[I]>;
70 def SP : Rj<"sp", R29>, DwarfRegNum<[29]>;
71 def FP : Rj<"fp", R30>, DwarfRegNum<[30]>;
72 def LR : Rj<"lr", R31>, DwarfRegNum<[31]>;
74 // Aliases of the R* registers used to hold 64-bit int values (doubles).
75 let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in {
76 def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>;
77 def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>;
78 def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>;
79 def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>;
80 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>;
81 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>;
82 def D6 : Rd<12, "r13:12", [R12, R13]>, DwarfRegNum<[44]>;
83 def D7 : Rd<14, "r15:14", [R14, R15]>, DwarfRegNum<[46]>;
84 def D8 : Rd<16, "r17:16", [R16, R17]>, DwarfRegNum<[48]>;
85 def D9 : Rd<18, "r19:18", [R18, R19]>, DwarfRegNum<[50]>;
86 def D10 : Rd<20, "r21:20", [R20, R21]>, DwarfRegNum<[52]>;
87 def D11 : Rd<22, "r23:22", [R22, R23]>, DwarfRegNum<[54]>;
88 def D12 : Rd<24, "r25:24", [R24, R25]>, DwarfRegNum<[56]>;
89 def D13 : Rd<26, "r27:26", [R26, R27]>, DwarfRegNum<[58]>;
90 def D14 : Rd<28, "r29:28", [R28, R29]>, DwarfRegNum<[60]>;
91 def D15 : Rd<30, "r31:30", [R30, R31]>, DwarfRegNum<[62]>;
94 // Predicate registers.
95 def P0 : Rp<0, "p0">, DwarfRegNum<[63]>;
96 def P1 : Rp<1, "p1">, DwarfRegNum<[64]>;
97 def P2 : Rp<2, "p2">, DwarfRegNum<[65]>;
98 def P3 : Rp<3, "p3">, DwarfRegNum<[66]>;
100 // Control registers.
101 def SA0 : Rc<0, "sa0">, DwarfRegNum<[67]>;
102 def LC0 : Rc<1, "lc0">, DwarfRegNum<[68]>;
104 def SA1 : Rc<2, "sa1">, DwarfRegNum<[69]>;
105 def LC1 : Rc<3, "lc1">, DwarfRegNum<[70]>;
107 def M0 : Rc<6, "m0">, DwarfRegNum<[71]>;
108 def M1 : Rc<7, "m1">, DwarfRegNum<[72]>;
110 def PC : Rc<9, "pc">, DwarfRegNum<[32]>; // is the Dwarf number correct?
111 def GP : Rc<11, "gp">, DwarfRegNum<[33]>; // is the Dwarf number correct?
116 // FIXME: the register order should be defined in terms of the preferred
117 // allocation order...
119 def IntRegs : RegisterClass<"Hexagon", [i32,f32], 32,
120 (add (sequence "R%u", 0, 9),
121 (sequence "R%u", 12, 28),
122 R10, R11, R29, R30, R31)> {
125 def DoubleRegs : RegisterClass<"Hexagon", [i64,f64], 64,
126 (add (sequence "D%u", 0, 4),
127 (sequence "D%u", 6, 13), D5, D14, D15)>;
130 def PredRegs : RegisterClass<"Hexagon", [i1], 32, (add (sequence "P%u", 0, 3))>
135 def CRRegs : RegisterClass<"Hexagon", [i32], 32,
136 (add (sequence "LC%u", 0, 1),
137 (sequence "SA%u", 0, 1),
138 (sequence "M%u", 0, 1), PC, GP)> {