1 //===- HexagonSchedule.td - Hexagon Scheduling Definitions -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 def LSUNIT : FuncUnit;
17 def ALU32 : InstrItinClass;
18 def ALU64 : InstrItinClass;
19 def CR : InstrItinClass;
20 def J : InstrItinClass;
21 def JR : InstrItinClass;
22 def LD : InstrItinClass;
23 def M : InstrItinClass;
24 def ST : InstrItinClass;
25 def S : InstrItinClass;
26 def SYS : InstrItinClass;
27 def MARKER : InstrItinClass;
28 def PSEUDO : InstrItinClass;
30 def HexagonItineraries :
31 ProcessorItineraries<[LUNIT, LSUNIT, MUNIT, SUNIT], [], [
32 InstrItinData<ALU32 , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>,
33 InstrItinData<ALU64 , [InstrStage<1, [MUNIT, SUNIT]>]>,
34 InstrItinData<CR , [InstrStage<1, [SUNIT]>]>,
35 InstrItinData<J , [InstrStage<1, [SUNIT, MUNIT]>]>,
36 InstrItinData<JR , [InstrStage<1, [MUNIT]>]>,
37 InstrItinData<LD , [InstrStage<1, [LUNIT, LSUNIT]>]>,
38 InstrItinData<M , [InstrStage<1, [MUNIT, SUNIT]>]>,
39 InstrItinData<ST , [InstrStage<1, [LSUNIT]>]>,
40 InstrItinData<S , [InstrStage<1, [SUNIT, MUNIT]>]>,
41 InstrItinData<SYS , [InstrStage<1, [LSUNIT]>]>,
42 InstrItinData<MARKER , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>,
43 InstrItinData<PSEUDO , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>
46 def HexagonModel : SchedMachineModel {
47 // Max issue per cycle == bundle width.
49 let Itineraries = HexagonItineraries;
52 //===----------------------------------------------------------------------===//
54 //===----------------------------------------------------------------------===//
56 include "HexagonScheduleV4.td"
58 //===----------------------------------------------------------------------===//
60 //===----------------------------------------------------------------------===//