1 //=-HexagonScheduleV4.td - HexagonV4 Scheduling Definitions --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // There are four SLOTS (four parallel pipelines) in Hexagon V4 machine.
11 // This file describes that machine information.
14 // |===========|==================================================|
15 // | PIPELINE | Instruction Classes |
16 // |===========|==================================================|
17 // | SLOT0 | LD ST ALU32 MEMOP NV SYSTEM |
18 // |-----------|--------------------------------------------------|
19 // | SLOT1 | LD ST ALU32 |
20 // |-----------|--------------------------------------------------|
21 // | SLOT2 | XTYPE ALU32 J JR |
22 // |-----------|--------------------------------------------------|
23 // | SLOT3 | XTYPE ALU32 J CR |
24 // |===========|==================================================|
26 def CJ_tc_1_SLOT23 : InstrItinClass;
27 def CJ_tc_2early_SLOT23 : InstrItinClass;
28 def COPROC_VMEM_vtc_long_SLOT01 : InstrItinClass;
29 def COPROC_VX_vtc_long_SLOT23 : InstrItinClass;
30 def COPROC_VX_vtc_SLOT23 : InstrItinClass;
31 def J_tc_3stall_SLOT2 : InstrItinClass;
32 def MAPPING_tc_1_SLOT0123 : InstrItinClass;
33 def M_tc_3stall_SLOT23 : InstrItinClass;
34 def SUBINSN_tc_1_SLOT01 : InstrItinClass;
35 def SUBINSN_tc_2early_SLOT0 : InstrItinClass;
36 def SUBINSN_tc_2early_SLOT01 : InstrItinClass;
37 def SUBINSN_tc_3stall_SLOT0 : InstrItinClass;
38 def SUBINSN_tc_ld_SLOT0 : InstrItinClass;
39 def SUBINSN_tc_ld_SLOT01 : InstrItinClass;
40 def SUBINSN_tc_st_SLOT01 : InstrItinClass;
42 def HexagonItinerariesV55 :
43 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [
45 InstrItinData<ALU32_2op_tc_1_SLOT0123 ,
46 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
47 InstrItinData<ALU32_2op_tc_2early_SLOT0123,
48 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
49 InstrItinData<ALU32_3op_tc_1_SLOT0123 ,
50 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
51 InstrItinData<ALU32_3op_tc_2_SLOT0123 ,
52 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
53 InstrItinData<ALU32_3op_tc_2early_SLOT0123,
54 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
55 InstrItinData<ALU32_ADDI_tc_1_SLOT0123 ,
56 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
59 InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
60 InstrItinData<ALU64_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
61 InstrItinData<ALU64_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
62 InstrItinData<ALU64_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
65 InstrItinData<CR_tc_2_SLOT3 , [InstrStage<2, [SLOT3]>]>,
66 InstrItinData<CR_tc_2early_SLOT3 , [InstrStage<2, [SLOT3]>]>,
67 InstrItinData<CR_tc_3x_SLOT3 , [InstrStage<3, [SLOT3]>]>,
69 // Jump (conditional/unconditional/return etc)
70 InstrItinData<CR_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
71 InstrItinData<CR_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
72 InstrItinData<CJ_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
73 InstrItinData<CJ_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
74 InstrItinData<J_tc_2early_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
75 InstrItinData<J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>]>,
78 InstrItinData<J_tc_2early_SLOT2 , [InstrStage<2, [SLOT2]>]>,
79 InstrItinData<J_tc_3stall_SLOT2 , [InstrStage<3, [SLOT2]>]>,
82 InstrItinData<EXTENDER_tc_1_SLOT0123,
83 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
86 InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
87 InstrItinData<LD_tc_3or4stall_SLOT0, [InstrStage<3, [SLOT0]>]>,
88 InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>,
91 InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
92 InstrItinData<M_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
93 InstrItinData<M_tc_3_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
94 InstrItinData<M_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
95 InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
96 InstrItinData<M_tc_3stall_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>,
99 InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
100 InstrItinData<ST_tc_3stall_SLOT0, [InstrStage<3, [SLOT0]>]>,
101 InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>,
102 InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
105 InstrItinData<SUBINSN_tc_2early_SLOT0, [InstrStage<2, [SLOT0]>]>,
106 InstrItinData<SUBINSN_tc_3stall_SLOT0, [InstrStage<3, [SLOT0]>]>,
107 InstrItinData<SUBINSN_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>,
108 InstrItinData<SUBINSN_tc_1_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
109 InstrItinData<SUBINSN_tc_2early_SLOT01,
110 [InstrStage<2, [SLOT0, SLOT1]>]>,
111 InstrItinData<SUBINSN_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
112 InstrItinData<SUBINSN_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
115 InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
116 InstrItinData<S_2op_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
117 InstrItinData<S_2op_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
118 InstrItinData<S_2op_tc_3or4x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
119 InstrItinData<S_3op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
120 InstrItinData<S_3op_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
121 InstrItinData<S_3op_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
122 InstrItinData<S_3op_tc_3_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
123 InstrItinData<S_3op_tc_3stall_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>,
124 InstrItinData<S_3op_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
126 // New Value Compare Jump
127 InstrItinData<NCJ_tc_3or4stall_SLOT0, [InstrStage<3, [SLOT0]>]>,
130 InstrItinData<V2LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
131 InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<2, [SLOT0, SLOT1]>]>,
132 InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
133 InstrItinData<V4LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
134 InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
135 InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
138 InstrItinData<J_tc_2early_SLOT0123, [InstrStage<2, [SLOT_ENDLOOP]>]>,
141 InstrItinData<COPROC_VMEM_vtc_long_SLOT01,
142 [InstrStage<3, [SLOT0, SLOT1]>]>,
143 InstrItinData<COPROC_VX_vtc_long_SLOT23 ,
144 [InstrStage<3, [SLOT2, SLOT3]>]>,
145 InstrItinData<COPROC_VX_vtc_SLOT23 ,
146 [InstrStage<3, [SLOT2, SLOT3]>]>,
147 InstrItinData<MAPPING_tc_1_SLOT0123 ,
148 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
151 InstrItinData<COMPOUND_CJ_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>]>,
152 InstrItinData<COMPOUND , [InstrStage<1, [SLOT2, SLOT3]>]>,
153 InstrItinData<DUPLEX , [InstrStage<1, [SLOT0]>]>,
154 InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
155 InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
156 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
157 InstrStage<1, [SLOT2, SLOT3]>]>
161 def HexagonModelV55 : SchedMachineModel {
162 // Max issue per cycle == bundle width.
164 let Itineraries = HexagonItinerariesV55;
168 //===----------------------------------------------------------------------===//
169 // Hexagon V4 Resource Definitions -
170 //===----------------------------------------------------------------------===//