1 //=== HexagonSplitConst32AndConst64.cpp - split CONST32/Const64 into HI/LO ===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // When the compiler is invoked with no small data, for instance, with the -G0
11 // command line option, then all CONST32_* opcodes should be broken down into
12 // appropriate LO and HI instructions. This splitting is done by this pass.
13 // The only reason this is not done in the DAG lowering itself is that there
14 // is no simple way of getting the register allocator to allot the same hard
15 // register to the result of LO and HI instructions. This pass is always
16 // scheduled after register allocation.
18 //===----------------------------------------------------------------------===//
20 #include "HexagonMachineFunctionInfo.h"
21 #include "HexagonSubtarget.h"
22 #include "HexagonTargetMachine.h"
23 #include "HexagonTargetObjectFile.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/CodeGen/LatencyPriorityQueue.h"
26 #include "llvm/CodeGen/MachineDominators.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineLoopInfo.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/Passes.h"
32 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34 #include "llvm/CodeGen/SchedulerRegistry.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Compiler.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/MathExtras.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetMachine.h"
41 #include "llvm/Target/TargetRegisterInfo.h"
46 #define DEBUG_TYPE "xfer"
50 class HexagonSplitConst32AndConst64 : public MachineFunctionPass {
53 HexagonSplitConst32AndConst64() : MachineFunctionPass(ID) {}
55 const char *getPassName() const override {
56 return "Hexagon Split Const32s and Const64s";
58 bool runOnMachineFunction(MachineFunction &Fn) override;
62 char HexagonSplitConst32AndConst64::ID = 0;
65 bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) {
67 const HexagonTargetObjectFile &TLOF =
68 *static_cast<const HexagonTargetObjectFile *>(
69 Fn.getTarget().getObjFileLowering());
70 if (TLOF.IsSmallDataEnabled())
73 const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo();
75 // Loop over all of the basic blocks
76 for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
77 MBBb != MBBe; ++MBBb) {
78 MachineBasicBlock* MBB = MBBb;
79 // Traverse the basic block
80 MachineBasicBlock::iterator MII = MBB->begin();
81 MachineBasicBlock::iterator MIE = MBB->end ();
83 MachineInstr *MI = MII;
84 int Opc = MI->getOpcode();
85 if (Opc == Hexagon::CONST32_set) {
86 int DestReg = MI->getOperand(0).getReg();
87 MachineOperand &Symbol = MI->getOperand (1);
89 BuildMI (*MBB, MII, MI->getDebugLoc(),
90 TII->get(Hexagon::LO), DestReg).addOperand(Symbol);
91 BuildMI (*MBB, MII, MI->getDebugLoc(),
92 TII->get(Hexagon::HI), DestReg).addOperand(Symbol);
93 // MBB->erase returns the iterator to the next instruction, which is the
94 // one we want to process next
95 MII = MBB->erase (MI);
98 else if (Opc == Hexagon::CONST32_set_jt) {
99 int DestReg = MI->getOperand(0).getReg();
100 MachineOperand &Symbol = MI->getOperand (1);
102 BuildMI (*MBB, MII, MI->getDebugLoc(),
103 TII->get(Hexagon::LO_jt), DestReg).addOperand(Symbol);
104 BuildMI (*MBB, MII, MI->getDebugLoc(),
105 TII->get(Hexagon::HI_jt), DestReg).addOperand(Symbol);
106 // MBB->erase returns the iterator to the next instruction, which is the
107 // one we want to process next
108 MII = MBB->erase (MI);
111 else if (Opc == Hexagon::CONST32_Label) {
112 int DestReg = MI->getOperand(0).getReg();
113 MachineOperand &Symbol = MI->getOperand (1);
115 BuildMI (*MBB, MII, MI->getDebugLoc(),
116 TII->get(Hexagon::LO_PIC), DestReg).addOperand(Symbol);
117 BuildMI (*MBB, MII, MI->getDebugLoc(),
118 TII->get(Hexagon::HI_PIC), DestReg).addOperand(Symbol);
119 // MBB->erase returns the iterator to the next instruction, which is the
120 // one we want to process next
121 MII = MBB->erase (MI);
124 else if (Opc == Hexagon::CONST32_Int_Real) {
125 int DestReg = MI->getOperand(0).getReg();
126 int64_t ImmValue = MI->getOperand(1).getImm ();
128 BuildMI (*MBB, MII, MI->getDebugLoc(),
129 TII->get(Hexagon::LOi), DestReg).addImm(ImmValue);
130 BuildMI (*MBB, MII, MI->getDebugLoc(),
131 TII->get(Hexagon::HIi), DestReg).addImm(ImmValue);
132 MII = MBB->erase (MI);
135 else if (Opc == Hexagon::CONST64_Int_Real) {
136 int DestReg = MI->getOperand(0).getReg();
137 int64_t ImmValue = MI->getOperand(1).getImm ();
138 unsigned DestLo = Fn.getSubtarget().getRegisterInfo()->getSubReg(
139 DestReg, Hexagon::subreg_loreg);
140 unsigned DestHi = Fn.getSubtarget().getRegisterInfo()->getSubReg(
141 DestReg, Hexagon::subreg_hireg);
143 int32_t LowWord = (ImmValue & 0xFFFFFFFF);
144 int32_t HighWord = (ImmValue >> 32) & 0xFFFFFFFF;
146 // Lower Registers Lower Half
147 BuildMI (*MBB, MII, MI->getDebugLoc(),
148 TII->get(Hexagon::LOi), DestLo).addImm(LowWord);
149 // Lower Registers Higher Half
150 BuildMI (*MBB, MII, MI->getDebugLoc(),
151 TII->get(Hexagon::HIi), DestLo).addImm(LowWord);
152 // Higher Registers Lower Half
153 BuildMI (*MBB, MII, MI->getDebugLoc(),
154 TII->get(Hexagon::LOi), DestHi).addImm(HighWord);
155 // Higher Registers Higher Half.
156 BuildMI (*MBB, MII, MI->getDebugLoc(),
157 TII->get(Hexagon::HIi), DestHi).addImm(HighWord);
158 MII = MBB->erase (MI);
170 //===----------------------------------------------------------------------===//
171 // Public Constructor Functions
172 //===----------------------------------------------------------------------===//
175 llvm::createHexagonSplitConst32AndConst64() {
176 return new HexagonSplitConst32AndConst64();