1 //===-- HexagonSplitTFRCondSets.cpp - split TFR condsets into xfers -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
10 // This pass tries to provide opportunities for better optimization of muxes.
11 // The default code generated for something like: flag = (a == b) ? 1 : 3;
14 // {p0 = cmp.eq(r0,r1)}
15 // {r3 = mux(p0,#1,#3)}
17 // This requires two packets. If we use .new predicated immediate transfers,
18 // then we can do this in a single packet, e.g.:
20 // {p0 = cmp.eq(r0,r1)
21 // if (p0.new) r3 = #1
22 // if (!p0.new) r3 = #3}
24 // Note that the conditional assignments are not generated in .new form here.
25 // We assume opptimisically that they will be formed later.
27 //===----------------------------------------------------------------------===//
30 #include "HexagonMachineFunctionInfo.h"
31 #include "HexagonSubtarget.h"
32 #include "HexagonTargetMachine.h"
33 #include "llvm/CodeGen/LatencyPriorityQueue.h"
34 #include "llvm/CodeGen/MachineDominators.h"
35 #include "llvm/CodeGen/MachineFunctionPass.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "llvm/CodeGen/MachineLoopInfo.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/Passes.h"
40 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
41 #include "llvm/CodeGen/SchedulerRegistry.h"
42 #include "llvm/Support/Compiler.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetRegisterInfo.h"
51 #define DEBUG_TYPE "xfer"
54 void initializeHexagonSplitTFRCondSetsPass(PassRegistry&);
60 class HexagonSplitTFRCondSets : public MachineFunctionPass {
63 HexagonSplitTFRCondSets() : MachineFunctionPass(ID) {
64 initializeHexagonSplitTFRCondSetsPass(*PassRegistry::getPassRegistry());
67 const char *getPassName() const override {
68 return "Hexagon Split TFRCondSets";
70 bool runOnMachineFunction(MachineFunction &Fn) override;
74 char HexagonSplitTFRCondSets::ID = 0;
77 bool HexagonSplitTFRCondSets::runOnMachineFunction(MachineFunction &Fn) {
79 const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo();
81 // Loop over all of the basic blocks.
82 for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
83 MBBb != MBBe; ++MBBb) {
84 MachineBasicBlock* MBB = MBBb;
85 // Traverse the basic block.
86 for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end();
88 MachineInstr *MI = MII;
89 switch(MI->getOpcode()) {
90 case Hexagon::TFR_condset_ri: {
91 int DestReg = MI->getOperand(0).getReg();
92 int SrcReg1 = MI->getOperand(2).getReg();
94 // Do not emit the predicated copy if the source and the destination
95 // is the same register.
96 if (DestReg != SrcReg1) {
97 BuildMI(*MBB, MII, MI->getDebugLoc(),
98 TII->get(Hexagon::A2_tfrt), DestReg).
99 addReg(MI->getOperand(1).getReg()).addReg(SrcReg1);
101 BuildMI(*MBB, MII, MI->getDebugLoc(),
102 TII->get(Hexagon::C2_cmoveif), DestReg).
103 addReg(MI->getOperand(1).getReg()).
104 addImm(MI->getOperand(3).getImm());
106 MII = MBB->erase(MI);
110 case Hexagon::TFR_condset_ir: {
111 int DestReg = MI->getOperand(0).getReg();
112 int SrcReg2 = MI->getOperand(3).getReg();
114 BuildMI(*MBB, MII, MI->getDebugLoc(),
115 TII->get(Hexagon::C2_cmoveit), DestReg).
116 addReg(MI->getOperand(1).getReg()).
117 addImm(MI->getOperand(2).getImm());
119 // Do not emit the predicated copy if the source and
120 // the destination is the same register.
121 if (DestReg != SrcReg2) {
122 BuildMI(*MBB, MII, MI->getDebugLoc(),
123 TII->get(Hexagon::A2_tfrf), DestReg).
124 addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
126 MII = MBB->erase(MI);
130 case Hexagon::TFR_condset_ii: {
131 int DestReg = MI->getOperand(0).getReg();
132 int SrcReg1 = MI->getOperand(1).getReg();
134 int Immed1 = MI->getOperand(2).getImm();
135 int Immed2 = MI->getOperand(3).getImm();
136 BuildMI(*MBB, MII, MI->getDebugLoc(),
137 TII->get(Hexagon::C2_cmoveit),
138 DestReg).addReg(SrcReg1).addImm(Immed1);
139 BuildMI(*MBB, MII, MI->getDebugLoc(),
140 TII->get(Hexagon::C2_cmoveif),
141 DestReg).addReg(SrcReg1).addImm(Immed2);
142 MII = MBB->erase(MI);
154 //===----------------------------------------------------------------------===//
155 // Public Constructor Functions
156 //===----------------------------------------------------------------------===//
158 static void initializePassOnce(PassRegistry &Registry) {
159 const char *Name = "Hexagon Split TFRCondSets";
160 PassInfo *PI = new PassInfo(Name, "hexagon-split-tfr",
161 &HexagonSplitTFRCondSets::ID, nullptr, false,
163 Registry.registerPass(*PI, true);
166 void llvm::initializeHexagonSplitTFRCondSetsPass(PassRegistry &Registry) {
167 CALL_ONCE_INITIALIZATION(initializePassOnce)
170 FunctionPass *llvm::createHexagonSplitTFRCondSets() {
171 return new HexagonSplitTFRCondSets();