1 //===-- HexagonSubtarget.cpp - Hexagon Subtarget Information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the Hexagon specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonSubtarget.h"
16 #include "llvm/Support/CommandLine.h"
17 #include "llvm/Support/ErrorHandling.h"
20 #define GET_SUBTARGETINFO_CTOR
21 #define GET_SUBTARGETINFO_TARGET_DESC
22 #include "HexagonGenSubtargetInfo.inc"
25 EnableV3("enable-hexagon-v3", cl::Hidden,
26 cl::desc("Enable Hexagon V3 instructions."));
30 "enable-hexagon-memops",
31 cl::Hidden, cl::ZeroOrMore, cl::ValueDisallowed,
32 cl::desc("Generate V4 MEMOP in code generation for Hexagon target"));
34 HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS):
35 HexagonGenSubtargetInfo(TT, CPU, FS),
36 HexagonArchVersion(V1),
37 CPUString(CPU.str()) {
38 ParseSubtargetFeatures(CPU, FS);
40 switch(HexagonArchVersion) {
41 case HexagonSubtarget::V2:
43 case HexagonSubtarget::V3:
46 case HexagonSubtarget::V4:
49 llvm_unreachable("Unknown Architecture Version.");
52 // Initialize scheduling itinerary for the specified CPU.
53 InstrItins = getInstrItineraryForCPU(CPUString);
55 // Max issue per cycle == bundle width.
56 InstrItins.IssueWidth = 4;