1 //==- HexagonSystemInst.td - System Instructions for Hexagon -*- tablegen -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Cache manipulation instructions.
16 //===----------------------------------------------------------------------===//
18 class ST_MISC_CACHEOP<dag outs, dag ins,
19 string asmstr, list<dag> pattern = [],
20 bits<3> amode, bits<3> type, bits<1> un>
21 : ST0Inst<outs, ins, asmstr, pattern, "", ST_tc_ld_SLOT0> {
26 let Inst{31-28} = 0b1010;
27 let Inst{27-25} = amode;
28 let Inst{24-22} = type;
36 class ST_MISC_CACHEOP_SYS<dag outs, dag ins,
37 string asmstr, list<dag> pattern = [],
38 bits<3> amode, bits<3> type, bits<1> un>
39 : SYSInst<outs, ins, asmstr, pattern, ""> {
44 let Inst{31-28} = 0b1010;
45 let Inst{27-25} = amode;
46 let Inst{24-22} = type;
54 let isSolo = 1, Rs = 0, Rt = 0, Rd = 0 in {
55 def Y2_syncht: ST_MISC_CACHEOP <(outs), (ins),
56 "syncht" , [], 0b100, 0b001, 0b0>;
59 let Rt = 0, Rd = 0 in {
60 let isSoloAin1 = 1 in {
61 def Y2_dccleana: ST_MISC_CACHEOP <(outs), (ins IntRegs:$Rs),
62 "dccleana($Rs)", [], 0b000, 0b000, 0b0>;
63 def Y2_dcinva: ST_MISC_CACHEOP <(outs), (ins IntRegs:$Rs),
64 "dcinva($Rs)", [], 0b000, 0b000, 0b1>;
65 def Y2_dccleaninva: ST_MISC_CACHEOP <(outs), (ins IntRegs:$Rs),
66 "dccleaninva($Rs)", [], 0b000, 0b001, 0b0>;
70 let isSoloAX = 1, hasSideEffects = 1, Rd = 0 in {
71 def Y4_l2fetch: ST_MISC_CACHEOP_SYS<(outs), (ins IntRegs:$Rs, IntRegs:$Rt),
72 "l2fetch($Rs, $Rt)", [], 0b011, 0b000, 0b0>;
73 def Y5_l2fetch: ST_MISC_CACHEOP_SYS<(outs), (ins IntRegs:$Rs, DoubleRegs:$Rt),
74 "l2fetch($Rs, $Rt)", [], 0b011, 0b010, 0b0>;
77 let hasSideEffects = 0, isSolo = 1 in
78 class Y2_INVALIDATE_CACHE<string mnemonic, bit MajOp>
80 (outs), (ins IntRegs:$Rs),
85 let Inst{27-21} = 0b0110110;
87 let Inst{13-12} = 0b00;
90 // Instruction cache invalidate
91 def Y2_icinva : Y2_INVALIDATE_CACHE<"icinva", 0b0>;
93 // Zero an aligned 32-byte cacheline.
95 def Y2_dczeroa: ST0Inst <(outs), (ins IntRegs:$Rs),
99 let Inst{27-21} = 0b0000110;
101 let Inst{20-16} = Rs;
104 // Memory synchronization.
105 let hasSideEffects = 0, isSolo = 1 in
106 def Y2_isync: JRInst <(outs), (ins),
109 let Inst{27-16} = 0b011111000000;
111 let Inst{9-0} = 0b0000000010;