1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implements the info about Hexagon target spec.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonTargetMachine.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/IR/Module.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
25 #include "llvm/Transforms/Scalar.h"
29 static cl:: opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
30 cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
32 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
33 cl::Hidden, cl::ZeroOrMore, cl::init(false),
34 cl::desc("Disable Hexagon CFG Optimization"));
36 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
37 cl::init(true), cl::Hidden, cl::ZeroOrMore,
38 cl::desc("Early expansion of MUX"));
40 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
41 cl::Hidden, cl::desc("Generate \"insert\" instructions"));
43 /// HexagonTargetMachineModule - Note that this is used on hosts that
44 /// cannot link in a library unless there are references into the
45 /// library. In particular, it seems that it is not possible to get
46 /// things to work on Win32 without this. Though it is unused, do not
48 extern "C" int HexagonTargetMachineModule;
49 int HexagonTargetMachineModule = 0;
51 extern "C" void LLVMInitializeHexagonTarget() {
52 // Register the target.
53 RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
56 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
57 return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
60 static MachineSchedRegistry
61 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
62 createVLIWMachineSched);
65 FunctionPass *createHexagonExpandCondsets();
66 FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
67 CodeGenOpt::Level OptLevel);
68 FunctionPass *createHexagonDelaySlotFillerPass(const TargetMachine &TM);
69 FunctionPass *createHexagonRemoveExtendArgs(const HexagonTargetMachine &TM);
70 FunctionPass *createHexagonCFGOptimizer();
72 FunctionPass *createHexagonSplitConst32AndConst64();
73 FunctionPass *createHexagonExpandPredSpillCode();
74 FunctionPass *createHexagonGenInsert();
75 FunctionPass *createHexagonHardwareLoops();
76 FunctionPass *createHexagonPeephole();
77 FunctionPass *createHexagonFixupHwLoops();
78 FunctionPass *createHexagonNewValueJump();
79 FunctionPass *createHexagonCopyToCombine();
80 FunctionPass *createHexagonPacketizer();
81 FunctionPass *createHexagonNewValueJump();
82 } // end namespace llvm;
84 /// HexagonTargetMachine ctor - Create an ILP32 architecture model.
87 /// Hexagon_TODO: Do I need an aggregate alignment?
89 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
90 StringRef CPU, StringRef FS,
91 const TargetOptions &Options,
92 Reloc::Model RM, CodeModel::Model CM,
94 : LLVMTargetMachine(T, "e-m:e-p:32:32-i1:32-i64:64-a:0-n32", TT, CPU, FS,
96 TLOF(make_unique<HexagonTargetObjectFile>()),
97 Subtarget(TT, CPU, FS, *this) {
101 HexagonTargetMachine::~HexagonTargetMachine() {}
104 /// Hexagon Code Generator Pass Configuration Options.
105 class HexagonPassConfig : public TargetPassConfig {
107 HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
108 : TargetPassConfig(TM, PM) {
109 bool NoOpt = (TM->getOptLevel() == CodeGenOpt::None);
111 if (EnableExpandCondsets) {
112 Pass *Exp = createHexagonExpandCondsets();
113 insertPass(&RegisterCoalescerID, IdentifyingPassPtr(Exp));
118 HexagonTargetMachine &getHexagonTargetMachine() const {
119 return getTM<HexagonTargetMachine>();
123 createMachineScheduler(MachineSchedContext *C) const override {
124 return createVLIWMachineSched(C);
127 bool addInstSelector() override;
128 void addPreRegAlloc() override;
129 void addPostRegAlloc() override;
130 void addPreSched2() override;
131 void addPreEmitPass() override;
135 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
136 return new HexagonPassConfig(this, PM);
139 bool HexagonPassConfig::addInstSelector() {
140 HexagonTargetMachine &TM = getHexagonTargetMachine();
141 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
144 addPass(createHexagonRemoveExtendArgs(TM));
146 addPass(createHexagonISelDag(TM, getOptLevel()));
149 addPass(createHexagonPeephole());
150 printAndVerify("After hexagon peephole pass");
152 addPass(createHexagonGenInsert(), false);
158 void HexagonPassConfig::addPreRegAlloc() {
159 if (getOptLevel() != CodeGenOpt::None)
160 if (!DisableHardwareLoops)
161 addPass(createHexagonHardwareLoops(), false);
164 void HexagonPassConfig::addPostRegAlloc() {
165 if (getOptLevel() != CodeGenOpt::None)
166 if (!DisableHexagonCFGOpt)
167 addPass(createHexagonCFGOptimizer(), false);
170 void HexagonPassConfig::addPreSched2() {
171 addPass(createHexagonCopyToCombine(), false);
172 if (getOptLevel() != CodeGenOpt::None)
173 addPass(&IfConverterID, false);
174 addPass(createHexagonSplitConst32AndConst64());
177 void HexagonPassConfig::addPreEmitPass() {
178 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
181 addPass(createHexagonNewValueJump(), false);
183 // Expand Spill code for predicate registers.
184 addPass(createHexagonExpandPredSpillCode(), false);
188 if (!DisableHardwareLoops)
189 addPass(createHexagonFixupHwLoops(), false);
190 addPass(createHexagonPacketizer(), false);