1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implements the info about Hexagon target spec.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonTargetMachine.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/IR/LegacyPassManager.h"
22 #include "llvm/IR/Module.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Transforms/Scalar.h"
30 static cl::opt<bool> EnableRDFOpt("rdf-opt", cl::Hidden, cl::ZeroOrMore,
31 cl::init(true), cl::desc("Enable RDF-based optimizations"));
33 static cl::opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
34 cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
36 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
37 cl::Hidden, cl::ZeroOrMore, cl::init(false),
38 cl::desc("Disable Hexagon CFG Optimization"));
40 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
41 cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
43 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
44 cl::init(true), cl::Hidden, cl::ZeroOrMore,
45 cl::desc("Early expansion of MUX"));
47 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
48 cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
50 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
51 cl::Hidden, cl::desc("Generate \"insert\" instructions"));
53 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
54 cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
56 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
57 cl::Hidden, cl::desc("Generate \"extract\" instructions"));
59 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
60 cl::desc("Enable converting conditional transfers into MUX instructions"));
62 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
63 cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
64 "predicate instructions"));
66 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
67 cl::desc("Disable splitting double registers"));
69 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
70 cl::Hidden, cl::desc("Bit simplification"));
72 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
73 cl::Hidden, cl::desc("Loop rescheduling"));
75 /// HexagonTargetMachineModule - Note that this is used on hosts that
76 /// cannot link in a library unless there are references into the
77 /// library. In particular, it seems that it is not possible to get
78 /// things to work on Win32 without this. Though it is unused, do not
80 extern "C" int HexagonTargetMachineModule;
81 int HexagonTargetMachineModule = 0;
83 extern "C" void LLVMInitializeHexagonTarget() {
84 // Register the target.
85 RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
88 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
89 return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
92 static MachineSchedRegistry
93 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
94 createVLIWMachineSched);
97 FunctionPass *createHexagonBitSimplify();
98 FunctionPass *createHexagonCallFrameInformation();
99 FunctionPass *createHexagonCFGOptimizer();
100 FunctionPass *createHexagonCommonGEP();
101 FunctionPass *createHexagonCopyToCombine();
102 FunctionPass *createHexagonEarlyIfConversion();
103 FunctionPass *createHexagonExpandCondsets();
104 FunctionPass *createHexagonExpandPredSpillCode();
105 FunctionPass *createHexagonFixupHwLoops();
106 FunctionPass *createHexagonGenExtract();
107 FunctionPass *createHexagonGenInsert();
108 FunctionPass *createHexagonGenMux();
109 FunctionPass *createHexagonGenPredicate();
110 FunctionPass *createHexagonHardwareLoops();
111 FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
112 CodeGenOpt::Level OptLevel);
113 FunctionPass *createHexagonLoopRescheduling();
114 FunctionPass *createHexagonNewValueJump();
115 FunctionPass *createHexagonOptimizeSZextends();
116 FunctionPass *createHexagonPacketizer();
117 FunctionPass *createHexagonPeephole();
118 FunctionPass *createHexagonRDFOpt();
119 FunctionPass *createHexagonSplitConst32AndConst64();
120 FunctionPass *createHexagonSplitDoubleRegs();
121 FunctionPass *createHexagonStoreWidening();
122 } // end namespace llvm;
124 /// HexagonTargetMachine ctor - Create an ILP32 architecture model.
127 /// Hexagon_TODO: Do I need an aggregate alignment?
129 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
130 StringRef CPU, StringRef FS,
131 const TargetOptions &Options,
132 Reloc::Model RM, CodeModel::Model CM,
133 CodeGenOpt::Level OL)
134 : LLVMTargetMachine(T, "e-m:e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-"
135 "i1:8:8-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-"
136 "n16:32", TT, CPU, FS, Options, RM, CM, OL),
137 TLOF(make_unique<HexagonTargetObjectFile>()) {
141 const HexagonSubtarget *
142 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
143 AttributeSet FnAttrs = F.getAttributes();
145 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
147 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
149 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
150 ? CPUAttr.getValueAsString().str()
152 std::string FS = !FSAttr.hasAttribute(Attribute::None)
153 ? FSAttr.getValueAsString().str()
156 auto &I = SubtargetMap[CPU + FS];
158 // This needs to be done before we create a new subtarget since any
159 // creation will depend on the TM and the code generation flags on the
160 // function that reside in TargetOptions.
161 resetTargetOptions(F);
162 I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
167 TargetIRAnalysis HexagonTargetMachine::getTargetIRAnalysis() {
168 return TargetIRAnalysis([this](const Function &F) {
169 return TargetTransformInfo(HexagonTTIImpl(this, F));
174 HexagonTargetMachine::~HexagonTargetMachine() {}
177 /// Hexagon Code Generator Pass Configuration Options.
178 class HexagonPassConfig : public TargetPassConfig {
180 HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
181 : TargetPassConfig(TM, PM) {
182 bool NoOpt = (TM->getOptLevel() == CodeGenOpt::None);
184 if (EnableExpandCondsets) {
185 Pass *Exp = createHexagonExpandCondsets();
186 insertPass(&RegisterCoalescerID, IdentifyingPassPtr(Exp));
191 HexagonTargetMachine &getHexagonTargetMachine() const {
192 return getTM<HexagonTargetMachine>();
196 createMachineScheduler(MachineSchedContext *C) const override {
197 return createVLIWMachineSched(C);
200 void addIRPasses() override;
201 bool addInstSelector() override;
202 void addPreRegAlloc() override;
203 void addPostRegAlloc() override;
204 void addPreSched2() override;
205 void addPreEmitPass() override;
209 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
210 return new HexagonPassConfig(this, PM);
213 void HexagonPassConfig::addIRPasses() {
214 TargetPassConfig::addIRPasses();
215 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
217 addPass(createAtomicExpandPass(TM));
220 addPass(createHexagonCommonGEP());
221 // Replace certain combinations of shifts and ands with extracts.
222 if (EnableGenExtract)
223 addPass(createHexagonGenExtract());
227 bool HexagonPassConfig::addInstSelector() {
228 HexagonTargetMachine &TM = getHexagonTargetMachine();
229 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
232 addPass(createHexagonOptimizeSZextends());
234 addPass(createHexagonISelDag(TM, getOptLevel()));
237 // Create logical operations on predicate registers.
239 addPass(createHexagonGenPredicate(), false);
240 // Rotate loops to expose bit-simplification opportunities.
241 if (EnableLoopResched)
242 addPass(createHexagonLoopRescheduling(), false);
243 // Split double registers.
245 addPass(createHexagonSplitDoubleRegs());
246 // Bit simplification.
247 if (EnableBitSimplify)
248 addPass(createHexagonBitSimplify(), false);
249 addPass(createHexagonPeephole());
250 printAndVerify("After hexagon peephole pass");
252 addPass(createHexagonGenInsert(), false);
254 addPass(createHexagonEarlyIfConversion(), false);
260 void HexagonPassConfig::addPreRegAlloc() {
261 if (getOptLevel() != CodeGenOpt::None) {
262 if (!DisableStoreWidening)
263 addPass(createHexagonStoreWidening(), false);
264 if (!DisableHardwareLoops)
265 addPass(createHexagonHardwareLoops(), false);
269 void HexagonPassConfig::addPostRegAlloc() {
270 if (getOptLevel() != CodeGenOpt::None) {
272 addPass(createHexagonRDFOpt());
273 if (!DisableHexagonCFGOpt)
274 addPass(createHexagonCFGOptimizer(), false);
278 void HexagonPassConfig::addPreSched2() {
279 addPass(createHexagonCopyToCombine(), false);
280 if (getOptLevel() != CodeGenOpt::None)
281 addPass(&IfConverterID, false);
282 addPass(createHexagonSplitConst32AndConst64());
285 void HexagonPassConfig::addPreEmitPass() {
286 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
289 addPass(createHexagonNewValueJump(), false);
291 // Expand Spill code for predicate registers.
292 addPass(createHexagonExpandPredSpillCode(), false);
296 if (!DisableHardwareLoops)
297 addPass(createHexagonFixupHwLoops(), false);
298 // Generate MUX from pairs of conditional transfers.
300 addPass(createHexagonGenMux(), false);
302 addPass(createHexagonPacketizer(), false);
305 // Add CFI instructions if necessary.
306 addPass(createHexagonCallFrameInformation(), false);