1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implements the info about Hexagon target spec.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonTargetMachine.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "HexagonTargetTransformInfo.h"
20 #include "llvm/CodeGen/Passes.h"
21 #include "llvm/IR/LegacyPassManager.h"
22 #include "llvm/IR/Module.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Transforms/Scalar.h"
29 static cl:: opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
30 cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
32 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
33 cl::Hidden, cl::ZeroOrMore, cl::init(false),
34 cl::desc("Disable Hexagon CFG Optimization"));
36 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
37 cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
39 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
40 cl::init(true), cl::Hidden, cl::ZeroOrMore,
41 cl::desc("Early expansion of MUX"));
43 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
44 cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
46 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
47 cl::Hidden, cl::desc("Generate \"insert\" instructions"));
49 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
50 cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
52 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
53 cl::Hidden, cl::desc("Generate \"extract\" instructions"));
55 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
56 cl::desc("Enable converting conditional transfers into MUX instructions"));
58 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
59 cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
60 "predicate instructions"));
62 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
63 cl::desc("Disable splitting double registers"));
65 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
66 cl::Hidden, cl::desc("Bit simplification"));
68 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
69 cl::Hidden, cl::desc("Loop rescheduling"));
71 /// HexagonTargetMachineModule - Note that this is used on hosts that
72 /// cannot link in a library unless there are references into the
73 /// library. In particular, it seems that it is not possible to get
74 /// things to work on Win32 without this. Though it is unused, do not
76 extern "C" int HexagonTargetMachineModule;
77 int HexagonTargetMachineModule = 0;
79 extern "C" void LLVMInitializeHexagonTarget() {
80 // Register the target.
81 RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
84 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
85 return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
88 static MachineSchedRegistry
89 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
90 createVLIWMachineSched);
93 FunctionPass *createHexagonBitSimplify();
94 FunctionPass *createHexagonCallFrameInformation();
95 FunctionPass *createHexagonCFGOptimizer();
96 FunctionPass *createHexagonCommonGEP();
97 FunctionPass *createHexagonCopyToCombine();
98 FunctionPass *createHexagonEarlyIfConversion();
99 FunctionPass *createHexagonExpandCondsets();
100 FunctionPass *createHexagonExpandPredSpillCode();
101 FunctionPass *createHexagonFixupHwLoops();
102 FunctionPass *createHexagonGenExtract();
103 FunctionPass *createHexagonGenInsert();
104 FunctionPass *createHexagonGenMux();
105 FunctionPass *createHexagonGenPredicate();
106 FunctionPass *createHexagonHardwareLoops();
107 FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
108 CodeGenOpt::Level OptLevel);
109 FunctionPass *createHexagonLoopRescheduling();
110 FunctionPass *createHexagonNewValueJump();
111 FunctionPass *createHexagonOptimizeSZextends();
112 FunctionPass *createHexagonPacketizer();
113 FunctionPass *createHexagonPeephole();
114 FunctionPass *createHexagonSplitConst32AndConst64();
115 FunctionPass *createHexagonSplitDoubleRegs();
116 FunctionPass *createHexagonStoreWidening();
117 } // end namespace llvm;
119 /// HexagonTargetMachine ctor - Create an ILP32 architecture model.
122 /// Hexagon_TODO: Do I need an aggregate alignment?
124 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
125 StringRef CPU, StringRef FS,
126 const TargetOptions &Options,
127 Reloc::Model RM, CodeModel::Model CM,
128 CodeGenOpt::Level OL)
129 : LLVMTargetMachine(T, "e-m:e-p:32:32-i1:32-i64:64-a:0-n32", TT, CPU, FS,
130 Options, RM, CM, OL),
131 TLOF(make_unique<HexagonTargetObjectFile>()) {
135 const HexagonSubtarget *
136 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
137 AttributeSet FnAttrs = F.getAttributes();
139 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
141 FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
143 std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
144 ? CPUAttr.getValueAsString().str()
146 std::string FS = !FSAttr.hasAttribute(Attribute::None)
147 ? FSAttr.getValueAsString().str()
150 auto &I = SubtargetMap[CPU + FS];
152 // This needs to be done before we create a new subtarget since any
153 // creation will depend on the TM and the code generation flags on the
154 // function that reside in TargetOptions.
155 resetTargetOptions(F);
156 I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
161 TargetIRAnalysis HexagonTargetMachine::getTargetIRAnalysis() {
162 return TargetIRAnalysis([this](const Function &F) {
163 return TargetTransformInfo(HexagonTTIImpl(this, F));
168 HexagonTargetMachine::~HexagonTargetMachine() {}
171 /// Hexagon Code Generator Pass Configuration Options.
172 class HexagonPassConfig : public TargetPassConfig {
174 HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
175 : TargetPassConfig(TM, PM) {
176 bool NoOpt = (TM->getOptLevel() == CodeGenOpt::None);
178 if (EnableExpandCondsets) {
179 Pass *Exp = createHexagonExpandCondsets();
180 insertPass(&RegisterCoalescerID, IdentifyingPassPtr(Exp));
185 HexagonTargetMachine &getHexagonTargetMachine() const {
186 return getTM<HexagonTargetMachine>();
190 createMachineScheduler(MachineSchedContext *C) const override {
191 return createVLIWMachineSched(C);
194 void addIRPasses() override;
195 bool addInstSelector() override;
196 void addPreRegAlloc() override;
197 void addPostRegAlloc() override;
198 void addPreSched2() override;
199 void addPreEmitPass() override;
203 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
204 return new HexagonPassConfig(this, PM);
207 void HexagonPassConfig::addIRPasses() {
208 TargetPassConfig::addIRPasses();
209 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
211 addPass(createAtomicExpandPass(TM));
214 addPass(createHexagonCommonGEP());
215 // Replace certain combinations of shifts and ands with extracts.
216 if (EnableGenExtract)
217 addPass(createHexagonGenExtract());
221 bool HexagonPassConfig::addInstSelector() {
222 HexagonTargetMachine &TM = getHexagonTargetMachine();
223 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
226 addPass(createHexagonOptimizeSZextends());
228 addPass(createHexagonISelDag(TM, getOptLevel()));
231 // Create logical operations on predicate registers.
233 addPass(createHexagonGenPredicate(), false);
234 // Rotate loops to expose bit-simplification opportunities.
235 if (EnableLoopResched)
236 addPass(createHexagonLoopRescheduling(), false);
237 // Split double registers.
239 addPass(createHexagonSplitDoubleRegs());
240 // Bit simplification.
241 if (EnableBitSimplify)
242 addPass(createHexagonBitSimplify(), false);
243 addPass(createHexagonPeephole());
244 printAndVerify("After hexagon peephole pass");
246 addPass(createHexagonGenInsert(), false);
248 addPass(createHexagonEarlyIfConversion(), false);
254 void HexagonPassConfig::addPreRegAlloc() {
255 if (getOptLevel() != CodeGenOpt::None) {
256 if (!DisableStoreWidening)
257 addPass(createHexagonStoreWidening(), false);
258 if (!DisableHardwareLoops)
259 addPass(createHexagonHardwareLoops(), false);
263 void HexagonPassConfig::addPostRegAlloc() {
264 if (getOptLevel() != CodeGenOpt::None)
265 if (!DisableHexagonCFGOpt)
266 addPass(createHexagonCFGOptimizer(), false);
269 void HexagonPassConfig::addPreSched2() {
270 addPass(createHexagonCopyToCombine(), false);
271 if (getOptLevel() != CodeGenOpt::None)
272 addPass(&IfConverterID, false);
273 addPass(createHexagonSplitConst32AndConst64());
276 void HexagonPassConfig::addPreEmitPass() {
277 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
280 addPass(createHexagonNewValueJump(), false);
282 // Expand Spill code for predicate registers.
283 addPass(createHexagonExpandPredSpillCode(), false);
287 if (!DisableHardwareLoops)
288 addPass(createHexagonFixupHwLoops(), false);
289 // Generate MUX from pairs of conditional transfers.
291 addPass(createHexagonGenMux(), false);
293 addPass(createHexagonPacketizer(), false);
296 // Add CFI instructions if necessary.
297 addPass(createHexagonCallFrameInformation(), false);