lib/Target/Hexagon/HexagonTargetMachine.cpp

   1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "HexagonTargetMachine.h"
  14 #include "Hexagon.h"
  15 #include "HexagonISelLowering.h"
  16 #include "llvm/Module.h"
  17 #include "llvm/CodeGen/Passes.h"
  18 #include "llvm/PassManager.h"
  19 #include "llvm/Support/CommandLine.h"
  20 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
  21 #include "llvm/Transforms/Scalar.h"
  22 #include "llvm/Support/TargetRegistry.h"
  23 #include <iostream>
  24
  25 using namespace llvm;
  26
  27 static cl::
  28 opt<bool> DisableHardwareLoops(
  29                         "disable-hexagon-hwloops", cl::Hidden,
  30                         cl::desc("Disable Hardware Loops for Hexagon target"));
  31
  32 /// HexagonTargetMachineModule - Note that this is used on hosts that
  33 /// cannot link in a library unless there are references into the
  34 /// library.  In particular, it seems that it is not possible to get
  35 /// things to work on Win32 without this.  Though it is unused, do not
  36 /// remove it.
  37 extern "C" int HexagonTargetMachineModule;
  38 int HexagonTargetMachineModule = 0;
  39
  40 extern "C" void LLVMInitializeHexagonTarget() {
  41   // Register the target.
  42   RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
  43 }
  44
  45
  46 /// HexagonTargetMachine ctor - Create an ILP32 architecture model.
  47 ///
  48
  49 /// Hexagon_TODO: Do I need an aggregate alignment?
  50 ///
  51 HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
  52                                            StringRef CPU, StringRef FS,
  53                                            TargetOptions Options,
  54                                            Reloc::Model RM,
  55                                            CodeModel::Model CM,
  56                                            CodeGenOpt::Level OL)
  57   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
  58     DataLayout("e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-a0:0") ,
  59     Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
  60     TSInfo(*this),
  61     FrameLowering(Subtarget),
  62     InstrItins(&Subtarget.getInstrItineraryData()) {
  63   setMCUseCFI(false);
  64 }
  65
  66 // addPassesForOptimizations - Allow the backend (target) to add Target
  67 // Independent Optimization passes to the Pass Manager.
  68 bool HexagonTargetMachine::addPassesForOptimizations(PassManagerBase &PM) {
  69
  70   PM.add(createConstantPropagationPass());
  71   PM.add(createLoopSimplifyPass());
  72   PM.add(createDeadCodeEliminationPass());
  73   PM.add(createConstantPropagationPass());
  74   PM.add(createLoopUnrollPass());
  75   PM.add(createLoopStrengthReducePass(getTargetLowering()));
  76   return true;
  77 }
  78
  79 bool HexagonTargetMachine::addInstSelector(PassManagerBase &PM) {
  80   PM.add(createHexagonRemoveExtendOps(*this));
  81   PM.add(createHexagonISelDag(*this));
  82   return false;
  83 }
  84
  85
  86 bool HexagonTargetMachine::addPreRegAlloc(PassManagerBase &PM) {
  87   if (!DisableHardwareLoops) {
  88     PM.add(createHexagonHardwareLoops());
  89   }
  90
  91   return false;
  92 }
  93
  94 bool HexagonTargetMachine::addPostRegAlloc(PassManagerBase &PM) {
  95   PM.add(createHexagonCFGOptimizer(*this));
  96   return true;
  97 }
  98
  99
 100 bool HexagonTargetMachine::addPreSched2(PassManagerBase &PM) {
 101   PM.add(createIfConverterPass());
 102   return true;
 103 }
 104
 105 bool HexagonTargetMachine::addPreEmitPass(PassManagerBase &PM) {
 106
 107   if (!DisableHardwareLoops) {
 108     PM.add(createHexagonFixupHwLoops());
 109   }
 110
 111   // Expand Spill code for predicate registers.
 112   PM.add(createHexagonExpandPredSpillCode(*this));
 113
 114   // Split up TFRcondsets into conditional transfers.
 115   PM.add(createHexagonSplitTFRCondSets(*this));
 116
 117   return false;
 118 }