1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implements the info about Hexagon target spec.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonTargetMachine.h"
16 #include "HexagonISelLowering.h"
17 #include "HexagonMachineScheduler.h"
18 #include "HexagonTargetObjectFile.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/IR/Module.h"
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
25 #include "llvm/Transforms/Scalar.h"
29 static cl:: opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
30 cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
32 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
33 cl::Hidden, cl::ZeroOrMore, cl::init(false),
34 cl::desc("Disable Hexagon CFG Optimization"));
37 /// HexagonTargetMachineModule - Note that this is used on hosts that
38 /// cannot link in a library unless there are references into the
39 /// library. In particular, it seems that it is not possible to get
40 /// things to work on Win32 without this. Though it is unused, do not
42 extern "C" int HexagonTargetMachineModule;
43 int HexagonTargetMachineModule = 0;
45 extern "C" void LLVMInitializeHexagonTarget() {
46 // Register the target.
47 RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
50 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
51 return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
54 static MachineSchedRegistry
55 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
56 createVLIWMachineSched);
58 /// HexagonTargetMachine ctor - Create an ILP32 architecture model.
61 /// Hexagon_TODO: Do I need an aggregate alignment?
63 HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
64 StringRef CPU, StringRef FS,
65 const TargetOptions &Options,
66 Reloc::Model RM, CodeModel::Model CM,
68 : LLVMTargetMachine(T, "e-m:e-p:32:32-i1:32-i64:64-a:0-n32", TT, CPU, FS,
70 TLOF(make_unique<HexagonTargetObjectFile>()),
71 Subtarget(TT, CPU, FS, *this) {
75 HexagonTargetMachine::~HexagonTargetMachine() {}
78 /// Hexagon Code Generator Pass Configuration Options.
79 class HexagonPassConfig : public TargetPassConfig {
81 HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
82 : TargetPassConfig(TM, PM) {}
84 HexagonTargetMachine &getHexagonTargetMachine() const {
85 return getTM<HexagonTargetMachine>();
89 createMachineScheduler(MachineSchedContext *C) const override {
90 return createVLIWMachineSched(C);
93 bool addInstSelector() override;
94 void addPreRegAlloc() override;
95 void addPostRegAlloc() override;
96 void addPreSched2() override;
97 void addPreEmitPass() override;
101 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
102 return new HexagonPassConfig(this, PM);
105 bool HexagonPassConfig::addInstSelector() {
106 HexagonTargetMachine &TM = getHexagonTargetMachine();
107 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
110 addPass(createHexagonRemoveExtendArgs(TM));
112 addPass(createHexagonISelDag(TM, getOptLevel()));
115 addPass(createHexagonPeephole());
116 printAndVerify("After hexagon peephole pass");
122 void HexagonPassConfig::addPreRegAlloc() {
123 if (getOptLevel() != CodeGenOpt::None)
124 if (!DisableHardwareLoops)
125 addPass(createHexagonHardwareLoops(), false);
128 void HexagonPassConfig::addPostRegAlloc() {
129 if (getOptLevel() != CodeGenOpt::None)
130 if (!DisableHexagonCFGOpt)
131 addPass(createHexagonCFGOptimizer(), false);
134 void HexagonPassConfig::addPreSched2() {
135 addPass(createHexagonCopyToCombine(), false);
136 if (getOptLevel() != CodeGenOpt::None)
137 addPass(&IfConverterID, false);
138 addPass(createHexagonSplitConst32AndConst64());
141 void HexagonPassConfig::addPreEmitPass() {
142 bool NoOpt = (getOptLevel() == CodeGenOpt::None);
145 addPass(createHexagonNewValueJump(), false);
147 // Expand Spill code for predicate registers.
148 addPass(createHexagonExpandPredSpillCode(), false);
152 if (!DisableHardwareLoops)
153 addPass(createHexagonFixupHwLoops(), false);
154 addPass(createHexagonPacketizer(), false);