1 //===- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #include "HexagonTargetMachine.h"
15 #include "HexagonISelLowering.h"
16 #include "llvm/Module.h"
17 #include "llvm/CodeGen/Passes.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
20 #include "llvm/Transforms/Scalar.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/TargetRegistry.h"
27 opt<bool> DisableHardwareLoops(
28 "disable-hexagon-hwloops", cl::Hidden,
29 cl::desc("Disable Hardware Loops for Hexagon target"));
31 /// HexagonTargetMachineModule - Note that this is used on hosts that
32 /// cannot link in a library unless there are references into the
33 /// library. In particular, it seems that it is not possible to get
34 /// things to work on Win32 without this. Though it is unused, do not
36 extern "C" int HexagonTargetMachineModule;
37 int HexagonTargetMachineModule = 0;
39 extern "C" void LLVMInitializeHexagonTarget() {
40 // Register the target.
41 RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
45 /// HexagonTargetMachine ctor - Create an ILP32 architecture model.
48 /// Hexagon_TODO: Do I need an aggregate alignment?
50 HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
51 StringRef CPU, StringRef FS,
52 TargetOptions Options,
56 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
57 DataLayout("e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-a0:0") ,
58 Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
60 FrameLowering(Subtarget),
61 InstrItins(&Subtarget.getInstrItineraryData()) {
65 // addPassesForOptimizations - Allow the backend (target) to add Target
66 // Independent Optimization passes to the Pass Manager.
67 bool HexagonTargetMachine::addPassesForOptimizations(PassManagerBase &PM) {
69 PM.add(createConstantPropagationPass());
70 PM.add(createLoopSimplifyPass());
71 PM.add(createDeadCodeEliminationPass());
72 PM.add(createConstantPropagationPass());
73 PM.add(createLoopUnrollPass());
74 PM.add(createLoopStrengthReducePass(getTargetLowering()));
79 /// Hexagon Code Generator Pass Configuration Options.
80 class HexagonPassConfig : public TargetPassConfig {
82 HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
83 : TargetPassConfig(TM, PM) {}
85 HexagonTargetMachine &getHexagonTargetMachine() const {
86 return getTM<HexagonTargetMachine>();
89 virtual bool addInstSelector();
90 virtual bool addPreRegAlloc();
91 virtual bool addPostRegAlloc();
92 virtual bool addPreSched2();
93 virtual bool addPreEmitPass();
97 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
98 return new HexagonPassConfig(this, PM);
101 bool HexagonPassConfig::addInstSelector() {
102 PM.add(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
103 PM.add(createHexagonISelDag(getHexagonTargetMachine()));
108 bool HexagonPassConfig::addPreRegAlloc() {
109 if (!DisableHardwareLoops) {
110 PM.add(createHexagonHardwareLoops());
116 bool HexagonPassConfig::addPostRegAlloc() {
117 PM.add(createHexagonCFGOptimizer(getHexagonTargetMachine()));
122 bool HexagonPassConfig::addPreSched2() {
123 addPass(IfConverterID);
127 bool HexagonPassConfig::addPreEmitPass() {
129 if (!DisableHardwareLoops) {
130 PM.add(createHexagonFixupHwLoops());
133 // Expand Spill code for predicate registers.
134 PM.add(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
136 // Split up TFRcondsets into conditional transfers.
137 PM.add(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));