1 //===----- HexagonPacketizer.cpp - vliw packetizer ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a simple VLIW packetizer using DFA. The packetizer works on
11 // machine basic blocks. For each instruction I in BB, the packetizer consults
12 // the DFA to see if machine resources are available to execute I. If so, the
13 // packetizer checks if I depends on any instruction J in the current packet.
14 // If no dependency is found, I is added to current packet and machine resource
15 // is marked as taken. If any dependency is found, a target API call is made to
16 // prune the dependence.
18 //===----------------------------------------------------------------------===//
19 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "HexagonMachineFunctionInfo.h"
22 #include "HexagonRegisterInfo.h"
23 #include "HexagonSubtarget.h"
24 #include "HexagonTargetMachine.h"
25 #include "llvm/ADT/DenseMap.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/CodeGen/LatencyPriorityQueue.h"
28 #include "llvm/CodeGen/MachineDominators.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineLoopInfo.h"
34 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/Passes.h"
36 #include "llvm/CodeGen/ScheduleDAG.h"
37 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
38 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
39 #include "llvm/CodeGen/SchedulerRegistry.h"
40 #include "llvm/MC/MCInstrItineraries.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/Compiler.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Target/TargetInstrInfo.h"
46 #include "llvm/Target/TargetMachine.h"
47 #include "llvm/Target/TargetRegisterInfo.h"
53 #define DEBUG_TYPE "packets"
55 static cl::opt<bool> PacketizeVolatiles("hexagon-packetize-volatiles",
56 cl::ZeroOrMore, cl::Hidden, cl::init(true),
57 cl::desc("Allow non-solo packetization of volatile memory references"));
60 void initializeHexagonPacketizerPass(PassRegistry&);
65 class HexagonPacketizer : public MachineFunctionPass {
69 HexagonPacketizer() : MachineFunctionPass(ID) {
70 initializeHexagonPacketizerPass(*PassRegistry::getPassRegistry());
73 void getAnalysisUsage(AnalysisUsage &AU) const override {
75 AU.addRequired<MachineDominatorTree>();
76 AU.addRequired<MachineBranchProbabilityInfo>();
77 AU.addPreserved<MachineDominatorTree>();
78 AU.addRequired<MachineLoopInfo>();
79 AU.addPreserved<MachineLoopInfo>();
80 MachineFunctionPass::getAnalysisUsage(AU);
83 const char *getPassName() const override {
84 return "Hexagon Packetizer";
87 bool runOnMachineFunction(MachineFunction &Fn) override;
89 char HexagonPacketizer::ID = 0;
91 class HexagonPacketizerList : public VLIWPacketizerList {
95 // Has the instruction been promoted to a dot-new instruction.
96 bool PromotedToDotNew;
98 // Has the instruction been glued to allocframe.
99 bool GlueAllocframeStore;
101 // Has the feeder instruction been glued to new value jump.
102 bool GlueToNewValueJump;
104 // Check if there is a dependence between some instruction already in this
105 // packet and this instruction.
108 // Only check for dependence if there are resources available to
109 // schedule this instruction.
110 bool FoundSequentialDependence;
112 /// \brief A handle to the branch probability pass.
113 const MachineBranchProbabilityInfo *MBPI;
115 // Track MIs with ignored dependece.
116 std::vector<MachineInstr*> IgnoreDepMIs;
120 HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
121 MachineDominatorTree &MDT,
122 const MachineBranchProbabilityInfo *MBPI);
124 // initPacketizerState - initialize some internal flags.
125 void initPacketizerState() override;
127 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
128 bool ignorePseudoInstruction(MachineInstr *MI,
129 MachineBasicBlock *MBB) override;
131 // isSoloInstruction - return true if instruction MI can not be packetized
132 // with any other instruction, which means that MI itself is a packet.
133 bool isSoloInstruction(MachineInstr *MI) override;
135 // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
137 bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override;
139 // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
141 bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override;
143 MachineBasicBlock::iterator addToPacket(MachineInstr *MI) override;
145 bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg);
146 bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
147 MachineBasicBlock::iterator &MII,
148 const TargetRegisterClass* RC);
149 bool CanPromoteToDotNew(MachineInstr* MI, SUnit* PacketSU,
151 std::map <MachineInstr*, SUnit*> MIToSUnit,
152 MachineBasicBlock::iterator &MII,
153 const TargetRegisterClass* RC);
154 bool CanPromoteToNewValue(MachineInstr* MI, SUnit* PacketSU,
156 std::map <MachineInstr*, SUnit*> MIToSUnit,
157 MachineBasicBlock::iterator &MII);
158 bool CanPromoteToNewValueStore(MachineInstr* MI, MachineInstr* PacketMI,
160 std::map <MachineInstr*, SUnit*> MIToSUnit);
161 bool DemoteToDotOld(MachineInstr* MI);
162 bool ArePredicatesComplements(MachineInstr* MI1, MachineInstr* MI2,
163 std::map <MachineInstr*, SUnit*> MIToSUnit);
164 bool RestrictingDepExistInPacket(MachineInstr*,
165 unsigned, std::map <MachineInstr*, SUnit*>);
166 bool isNewifiable(MachineInstr* MI);
167 bool isCondInst(MachineInstr* MI);
168 bool tryAllocateResourcesForConstExt(MachineInstr* MI);
169 bool canReserveResourcesForConstExt(MachineInstr *MI);
170 void reserveResourcesForConstExt(MachineInstr* MI);
171 bool isNewValueInst(MachineInstr* MI);
175 INITIALIZE_PASS_BEGIN(HexagonPacketizer, "packets", "Hexagon Packetizer",
177 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
178 INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
179 INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
180 INITIALIZE_AG_DEPENDENCY(AliasAnalysis)
181 INITIALIZE_PASS_END(HexagonPacketizer, "packets", "Hexagon Packetizer",
185 // HexagonPacketizerList Ctor.
186 HexagonPacketizerList::HexagonPacketizerList(
187 MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT,
188 const MachineBranchProbabilityInfo *MBPI)
189 : VLIWPacketizerList(MF, MLI, MDT, true){
193 bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) {
194 const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo();
195 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
196 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
197 const MachineBranchProbabilityInfo *MBPI =
198 &getAnalysis<MachineBranchProbabilityInfo>();
199 // Instantiate the packetizer.
200 HexagonPacketizerList Packetizer(Fn, MLI, MDT, MBPI);
202 // DFA state table should not be empty.
203 assert(Packetizer.getResourceTracker() && "Empty DFA table!");
206 // Loop over all basic blocks and remove KILL pseudo-instructions
207 // These instructions confuse the dependence analysis. Consider:
209 // R0 = KILL R0, D0 (Insn 1)
211 // Here, Insn 1 will result in the dependence graph not emitting an output
212 // dependence between Insn 0 and Insn 2. This can lead to incorrect
215 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
216 MBB != MBBe; ++MBB) {
217 MachineBasicBlock::iterator End = MBB->end();
218 MachineBasicBlock::iterator MI = MBB->begin();
221 MachineBasicBlock::iterator DeleteMI = MI;
223 MBB->erase(DeleteMI);
231 // Loop over all of the basic blocks.
232 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
233 MBB != MBBe; ++MBB) {
234 // Find scheduling regions and schedule / packetize each region.
235 unsigned RemainingCount = MBB->size();
236 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
237 RegionEnd != MBB->begin();) {
238 // The next region starts above the previous region. Look backward in the
239 // instruction stream until we find the nearest boundary.
240 MachineBasicBlock::iterator I = RegionEnd;
241 for(;I != MBB->begin(); --I, --RemainingCount) {
242 if (TII->isSchedulingBoundary(std::prev(I), MBB, Fn))
247 // Skip empty scheduling regions.
248 if (I == RegionEnd) {
249 RegionEnd = std::prev(RegionEnd);
253 // Skip regions with one instruction.
254 if (I == std::prev(RegionEnd)) {
255 RegionEnd = std::prev(RegionEnd);
259 Packetizer.PacketizeMIs(MBB, I, RegionEnd);
268 static bool IsIndirectCall(MachineInstr* MI) {
269 return ((MI->getOpcode() == Hexagon::CALLR) ||
270 (MI->getOpcode() == Hexagon::CALLRv3));
273 // Reserve resources for constant extender. Trigure an assertion if
275 void HexagonPacketizerList::reserveResourcesForConstExt(MachineInstr* MI) {
276 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
277 MachineFunction *MF = MI->getParent()->getParent();
278 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
281 if (ResourceTracker->canReserveResources(PseudoMI)) {
282 ResourceTracker->reserveResources(PseudoMI);
283 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
285 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
286 llvm_unreachable("can not reserve resources for constant extender.");
291 bool HexagonPacketizerList::canReserveResourcesForConstExt(MachineInstr *MI) {
292 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
293 assert((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
294 "Should only be called for constant extended instructions");
295 MachineFunction *MF = MI->getParent()->getParent();
296 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
298 bool CanReserve = ResourceTracker->canReserveResources(PseudoMI);
299 MF->DeleteMachineInstr(PseudoMI);
303 // Allocate resources (i.e. 4 bytes) for constant extender. If succeed, return
304 // true, otherwise, return false.
305 bool HexagonPacketizerList::tryAllocateResourcesForConstExt(MachineInstr* MI) {
306 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
307 MachineFunction *MF = MI->getParent()->getParent();
308 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT_i),
311 if (ResourceTracker->canReserveResources(PseudoMI)) {
312 ResourceTracker->reserveResources(PseudoMI);
313 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
316 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
322 bool HexagonPacketizerList::IsCallDependent(MachineInstr* MI,
326 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
327 const HexagonRegisterInfo *QRI =
328 (const HexagonRegisterInfo *)TM.getSubtargetImpl()->getRegisterInfo();
330 // Check for lr dependence
331 if (DepReg == QRI->getRARegister()) {
335 if (QII->isDeallocRet(MI)) {
336 if (DepReg == QRI->getFrameRegister() ||
337 DepReg == QRI->getStackRegister())
341 // Check if this is a predicate dependence
342 const TargetRegisterClass* RC = QRI->getMinimalPhysRegClass(DepReg);
343 if (RC == &Hexagon::PredRegsRegClass) {
348 // Lastly check for an operand used in an indirect call
349 // If we had an attribute for checking if an instruction is an indirect call,
350 // then we could have avoided this relatively brittle implementation of
353 // Assumes that the first operand of the CALLr is the function address
355 if (IsIndirectCall(MI) && (DepType == SDep::Data)) {
356 MachineOperand MO = MI->getOperand(0);
357 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) {
365 static bool IsRegDependence(const SDep::Kind DepType) {
366 return (DepType == SDep::Data || DepType == SDep::Anti ||
367 DepType == SDep::Output);
370 static bool IsDirectJump(MachineInstr* MI) {
371 return (MI->getOpcode() == Hexagon::JMP);
374 static bool IsSchedBarrier(MachineInstr* MI) {
375 switch (MI->getOpcode()) {
376 case Hexagon::BARRIER:
382 static bool IsControlFlow(MachineInstr* MI) {
383 return (MI->getDesc().isTerminator() || MI->getDesc().isCall());
386 static bool IsLoopN(MachineInstr *MI) {
387 return (MI->getOpcode() == Hexagon::LOOP0_i ||
388 MI->getOpcode() == Hexagon::LOOP0_r);
391 /// DoesModifyCalleeSavedReg - Returns true if the instruction modifies a
392 /// callee-saved register.
393 static bool DoesModifyCalleeSavedReg(MachineInstr *MI,
394 const TargetRegisterInfo *TRI) {
395 for (const MCPhysReg *CSR = TRI->getCalleeSavedRegs(); *CSR; ++CSR) {
396 unsigned CalleeSavedReg = *CSR;
397 if (MI->modifiesRegister(CalleeSavedReg, TRI))
403 // Returns true if an instruction can be promoted to .new predicate
404 // or new-value store.
405 bool HexagonPacketizerList::isNewifiable(MachineInstr* MI) {
406 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
407 if ( isCondInst(MI) || QII->mayBeNewStore(MI))
413 bool HexagonPacketizerList::isCondInst (MachineInstr* MI) {
414 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
415 const MCInstrDesc& TID = MI->getDesc();
416 // bug 5670: until that is fixed,
417 // this portion is disabled.
418 if ( TID.isConditionalBranch() // && !IsRegisterJump(MI)) ||
419 || QII->isConditionalTransfer(MI)
420 || QII->isConditionalALU32(MI)
421 || QII->isConditionalLoad(MI)
422 || QII->isConditionalStore(MI)) {
429 // Promote an instructiont to its .new form.
430 // At this time, we have already made a call to CanPromoteToDotNew
431 // and made sure that it can *indeed* be promoted.
432 bool HexagonPacketizerList::PromoteToDotNew(MachineInstr* MI,
433 SDep::Kind DepType, MachineBasicBlock::iterator &MII,
434 const TargetRegisterClass* RC) {
436 assert (DepType == SDep::Data);
437 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
440 if (RC == &Hexagon::PredRegsRegClass)
441 NewOpcode = QII->GetDotNewPredOp(MI, MBPI);
443 NewOpcode = QII->GetDotNewOp(MI);
444 MI->setDesc(QII->get(NewOpcode));
449 bool HexagonPacketizerList::DemoteToDotOld(MachineInstr* MI) {
450 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
451 int NewOpcode = QII->GetDotOldOp(MI->getOpcode());
452 MI->setDesc(QII->get(NewOpcode));
462 /// Returns true if an instruction is predicated on p0 and false if it's
463 /// predicated on !p0.
464 static PredicateKind getPredicateSense(MachineInstr* MI,
465 const HexagonInstrInfo *QII) {
466 if (!QII->isPredicated(MI))
469 if (QII->isPredicatedTrue(MI))
475 static MachineOperand& GetPostIncrementOperand(MachineInstr *MI,
476 const HexagonInstrInfo *QII) {
477 assert(QII->isPostIncrement(MI) && "Not a post increment operation.");
479 // Post Increment means duplicates. Use dense map to find duplicates in the
480 // list. Caution: Densemap initializes with the minimum of 64 buckets,
481 // whereas there are at most 5 operands in the post increment.
482 DenseMap<unsigned, unsigned> DefRegsSet;
483 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
484 if (MI->getOperand(opNum).isReg() &&
485 MI->getOperand(opNum).isDef()) {
486 DefRegsSet[MI->getOperand(opNum).getReg()] = 1;
489 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
490 if (MI->getOperand(opNum).isReg() &&
491 MI->getOperand(opNum).isUse()) {
492 if (DefRegsSet[MI->getOperand(opNum).getReg()]) {
493 return MI->getOperand(opNum);
497 if (MI->getDesc().mayLoad()) {
498 // The 2nd operand is always the post increment operand in load.
499 assert(MI->getOperand(1).isReg() &&
500 "Post increment operand has be to a register.");
501 return (MI->getOperand(1));
503 if (MI->getDesc().mayStore()) {
504 // The 1st operand is always the post increment operand in store.
505 assert(MI->getOperand(0).isReg() &&
506 "Post increment operand has be to a register.");
507 return (MI->getOperand(0));
510 // we should never come here.
511 llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
514 // get the value being stored
515 static MachineOperand& GetStoreValueOperand(MachineInstr *MI) {
516 // value being stored is always the last operand.
517 return (MI->getOperand(MI->getNumOperands()-1));
520 // can be new value store?
521 // Following restrictions are to be respected in convert a store into
522 // a new value store.
523 // 1. If an instruction uses auto-increment, its address register cannot
524 // be a new-value register. Arch Spec 5.4.2.1
525 // 2. If an instruction uses absolute-set addressing mode,
526 // its address register cannot be a new-value register.
527 // Arch Spec 5.4.2.1.TODO: This is not enabled as
528 // as absolute-set address mode patters are not implemented.
529 // 3. If an instruction produces a 64-bit result, its registers cannot be used
530 // as new-value registers. Arch Spec 5.4.2.2.
531 // 4. If the instruction that sets a new-value register is conditional, then
532 // the instruction that uses the new-value register must also be conditional,
533 // and both must always have their predicates evaluate identically.
534 // Arch Spec 5.4.2.3.
535 // 5. There is an implied restriction of a packet can not have another store,
536 // if there is a new value store in the packet. Corollary, if there is
537 // already a store in a packet, there can not be a new value store.
538 // Arch Spec: 3.4.4.2
539 bool HexagonPacketizerList::CanPromoteToNewValueStore( MachineInstr *MI,
540 MachineInstr *PacketMI, unsigned DepReg,
541 std::map <MachineInstr*, SUnit*> MIToSUnit) {
542 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
543 // Make sure we are looking at the store, that can be promoted.
544 if (!QII->mayBeNewStore(MI))
547 // Make sure there is dependency and can be new value'ed
548 if (GetStoreValueOperand(MI).isReg() &&
549 GetStoreValueOperand(MI).getReg() != DepReg)
552 const HexagonRegisterInfo *QRI =
553 (const HexagonRegisterInfo *)TM.getSubtargetImpl()->getRegisterInfo();
554 const MCInstrDesc& MCID = PacketMI->getDesc();
555 // first operand is always the result
557 const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI, MF);
559 // if there is already an store in the packet, no can do new value store
560 // Arch Spec 3.4.4.2.
561 for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
562 VE = CurrentPacketMIs.end();
564 SUnit* PacketSU = MIToSUnit[*VI];
565 if (PacketSU->getInstr()->getDesc().mayStore() ||
566 // if we have mayStore = 1 set on ALLOCFRAME and DEALLOCFRAME,
567 // then we don't need this
568 PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
569 PacketSU->getInstr()->getOpcode() == Hexagon::DEALLOCFRAME)
573 if (PacketRC == &Hexagon::DoubleRegsRegClass) {
574 // new value store constraint: double regs can not feed into new value store
575 // arch spec section: 5.4.2.2
579 // Make sure it's NOT the post increment register that we are going to
581 if (QII->isPostIncrement(MI) &&
582 MI->getDesc().mayStore() &&
583 GetPostIncrementOperand(MI, QII).getReg() == DepReg) {
587 if (QII->isPostIncrement(PacketMI) &&
588 PacketMI->getDesc().mayLoad() &&
589 GetPostIncrementOperand(PacketMI, QII).getReg() == DepReg) {
590 // if source is post_inc, or absolute-set addressing,
591 // it can not feed into new value store
593 // memw(r30 + #-1404) = r2.new -> can not be new value store
594 // arch spec section: 5.4.2.1
598 // If the source that feeds the store is predicated, new value store must
599 // also be predicated.
600 if (QII->isPredicated(PacketMI)) {
601 if (!QII->isPredicated(MI))
604 // Check to make sure that they both will have their predicates
605 // evaluate identically
606 unsigned predRegNumSrc = 0;
607 unsigned predRegNumDst = 0;
608 const TargetRegisterClass* predRegClass = nullptr;
610 // Get predicate register used in the source instruction
611 for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
612 if ( PacketMI->getOperand(opNum).isReg())
613 predRegNumSrc = PacketMI->getOperand(opNum).getReg();
614 predRegClass = QRI->getMinimalPhysRegClass(predRegNumSrc);
615 if (predRegClass == &Hexagon::PredRegsRegClass) {
619 assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
620 ("predicate register not found in a predicated PacketMI instruction"));
622 // Get predicate register used in new-value store instruction
623 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
624 if ( MI->getOperand(opNum).isReg())
625 predRegNumDst = MI->getOperand(opNum).getReg();
626 predRegClass = QRI->getMinimalPhysRegClass(predRegNumDst);
627 if (predRegClass == &Hexagon::PredRegsRegClass) {
631 assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
632 ("predicate register not found in a predicated MI instruction"));
634 // New-value register producer and user (store) need to satisfy these
636 // 1) Both instructions should be predicated on the same register.
637 // 2) If producer of the new-value register is .new predicated then store
638 // should also be .new predicated and if producer is not .new predicated
639 // then store should not be .new predicated.
640 // 3) Both new-value register producer and user should have same predicate
641 // sense, i.e, either both should be negated or both should be none negated.
643 if (( predRegNumDst != predRegNumSrc) ||
644 QII->isDotNewInst(PacketMI) != QII->isDotNewInst(MI) ||
645 getPredicateSense(MI, QII) != getPredicateSense(PacketMI, QII)) {
650 // Make sure that other than the new-value register no other store instruction
651 // register has been modified in the same packet. Predicate registers can be
652 // modified by they should not be modified between the producer and the store
653 // instruction as it will make them both conditional on different values.
654 // We already know this to be true for all the instructions before and
655 // including PacketMI. Howerver, we need to perform the check for the
656 // remaining instructions in the packet.
658 std::vector<MachineInstr*>::iterator VI;
659 std::vector<MachineInstr*>::iterator VE;
660 unsigned StartCheck = 0;
662 for (VI=CurrentPacketMIs.begin(), VE = CurrentPacketMIs.end();
664 SUnit* TempSU = MIToSUnit[*VI];
665 MachineInstr* TempMI = TempSU->getInstr();
667 // Following condition is true for all the instructions until PacketMI is
668 // reached (StartCheck is set to 0 before the for loop).
669 // StartCheck flag is 1 for all the instructions after PacketMI.
670 if (TempMI != PacketMI && !StartCheck) // start processing only after
671 continue; // encountering PacketMI
674 if (TempMI == PacketMI) // We don't want to check PacketMI for dependence
677 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
678 if (MI->getOperand(opNum).isReg() &&
679 TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(),
685 // Make sure that for non-POST_INC stores:
686 // 1. The only use of reg is DepReg and no other registers.
687 // This handles V4 base+index registers.
688 // The following store can not be dot new.
689 // Eg. r0 = add(r0, #3)a
690 // memw(r1+r0<<#2) = r0
691 if (!QII->isPostIncrement(MI) &&
692 GetStoreValueOperand(MI).isReg() &&
693 GetStoreValueOperand(MI).getReg() == DepReg) {
694 for(unsigned opNum = 0; opNum < MI->getNumOperands()-1; opNum++) {
695 if (MI->getOperand(opNum).isReg() &&
696 MI->getOperand(opNum).getReg() == DepReg) {
700 // 2. If data definition is because of implicit definition of the register,
701 // do not newify the store. Eg.
702 // %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def>
703 // STrih_indexed %R8, 2, %R12<kill>; mem:ST2[%scevgep343]
704 for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
705 if (PacketMI->getOperand(opNum).isReg() &&
706 PacketMI->getOperand(opNum).getReg() == DepReg &&
707 PacketMI->getOperand(opNum).isDef() &&
708 PacketMI->getOperand(opNum).isImplicit()) {
714 // Can be dot new store.
718 // can this MI to promoted to either
719 // new value store or new value jump
720 bool HexagonPacketizerList::CanPromoteToNewValue( MachineInstr *MI,
721 SUnit *PacketSU, unsigned DepReg,
722 std::map <MachineInstr*, SUnit*> MIToSUnit,
723 MachineBasicBlock::iterator &MII)
726 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
727 const HexagonRegisterInfo *QRI =
728 (const HexagonRegisterInfo *)TM.getSubtargetImpl()->getRegisterInfo();
729 if (!QRI->Subtarget.hasV4TOps() ||
730 !QII->mayBeNewStore(MI))
733 MachineInstr *PacketMI = PacketSU->getInstr();
735 // Check to see the store can be new value'ed.
736 if (CanPromoteToNewValueStore(MI, PacketMI, DepReg, MIToSUnit))
739 // Check to see the compare/jump can be new value'ed.
740 // This is done as a pass on its own. Don't need to check it here.
744 // Check to see if an instruction can be dot new
745 // There are three kinds.
746 // 1. dot new on predicate - V2/V3/V4
747 // 2. dot new on stores NV/ST - V4
748 // 3. dot new on jump NV/J - V4 -- This is generated in a pass.
749 bool HexagonPacketizerList::CanPromoteToDotNew( MachineInstr *MI,
750 SUnit *PacketSU, unsigned DepReg,
751 std::map <MachineInstr*, SUnit*> MIToSUnit,
752 MachineBasicBlock::iterator &MII,
753 const TargetRegisterClass* RC )
755 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
756 // Already a dot new instruction.
757 if (QII->isDotNewInst(MI) && !QII->mayBeNewStore(MI))
760 if (!isNewifiable(MI))
764 if (RC == &Hexagon::PredRegsRegClass && isCondInst(MI))
766 else if (RC != &Hexagon::PredRegsRegClass &&
767 !QII->mayBeNewStore(MI)) // MI is not a new-value store
770 // Create a dot new machine instruction to see if resources can be
771 // allocated. If not, bail out now.
772 int NewOpcode = QII->GetDotNewOp(MI);
773 const MCInstrDesc &desc = QII->get(NewOpcode);
775 MachineInstr *NewMI =
776 MI->getParent()->getParent()->CreateMachineInstr(desc, dl);
777 bool ResourcesAvailable = ResourceTracker->canReserveResources(NewMI);
778 MI->getParent()->getParent()->DeleteMachineInstr(NewMI);
780 if (!ResourcesAvailable)
783 // new value store only
784 // new new value jump generated as a passes
785 if (!CanPromoteToNewValue(MI, PacketSU, DepReg, MIToSUnit, MII)) {
792 // Go through the packet instructions and search for anti dependency
793 // between them and DepReg from MI
794 // Consider this case:
796 // a) %R1<def> = TFRI_cdNotPt %P3, 2
799 // b) %P0<def> = OR_pp %P3<kill>, %P0<kill>
800 // c) %P3<def> = TFR_PdRs %R23
801 // d) %R1<def> = TFRI_cdnPt %P3, 4
803 // The P3 from a) and d) will be complements after
804 // a)'s P3 is converted to .new form
805 // Anti Dep between c) and b) is irrelevant for this case
806 bool HexagonPacketizerList::RestrictingDepExistInPacket (MachineInstr* MI,
808 std::map <MachineInstr*, SUnit*> MIToSUnit) {
810 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
811 SUnit* PacketSUDep = MIToSUnit[MI];
813 for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
814 VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
816 // We only care for dependencies to predicated instructions
817 if(!QII->isPredicated(*VIN)) continue;
819 // Scheduling Unit for current insn in the packet
820 SUnit* PacketSU = MIToSUnit[*VIN];
822 // Look at dependencies between current members of the packet
823 // and predicate defining instruction MI.
824 // Make sure that dependency is on the exact register
826 if (PacketSU->isSucc(PacketSUDep)) {
827 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
828 if ((PacketSU->Succs[i].getSUnit() == PacketSUDep) &&
829 (PacketSU->Succs[i].getKind() == SDep::Anti) &&
830 (PacketSU->Succs[i].getReg() == DepReg)) {
841 /// Gets the predicate register of a predicated instruction.
842 static unsigned getPredicatedRegister(MachineInstr *MI,
843 const HexagonInstrInfo *QII) {
844 /// We use the following rule: The first predicate register that is a use is
845 /// the predicate register of a predicated instruction.
847 assert(QII->isPredicated(MI) && "Must be predicated instruction");
849 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
850 OE = MI->operands_end(); OI != OE; ++OI) {
851 MachineOperand &Op = *OI;
852 if (Op.isReg() && Op.getReg() && Op.isUse() &&
853 Hexagon::PredRegsRegClass.contains(Op.getReg()))
857 llvm_unreachable("Unknown instruction operand layout");
862 // Given two predicated instructions, this function detects whether
863 // the predicates are complements
864 bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1,
865 MachineInstr* MI2, std::map <MachineInstr*, SUnit*> MIToSUnit) {
867 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
869 // If we don't know the predicate sense of the instructions bail out early, we
871 if (getPredicateSense(MI1, QII) == PK_Unknown ||
872 getPredicateSense(MI2, QII) == PK_Unknown)
875 // Scheduling unit for candidate
876 SUnit* SU = MIToSUnit[MI1];
878 // One corner case deals with the following scenario:
880 // a) %R24<def> = TFR_cPt %P0, %R25
884 // b) %R25<def> = TFR_cNotPt %P0, %R24
885 // c) %P0<def> = CMPEQri %R26, 1
888 // On general check a) and b) are complements, but
889 // presence of c) will convert a) to .new form, and
890 // then it is not a complement
891 // We attempt to detect it by analyzing existing
892 // dependencies in the packet
894 // Analyze relationships between all existing members of the packet.
895 // Look for Anti dependecy on the same predicate reg
896 // as used in the candidate
897 for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
898 VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
900 // Scheduling Unit for current insn in the packet
901 SUnit* PacketSU = MIToSUnit[*VIN];
903 // If this instruction in the packet is succeeded by the candidate...
904 if (PacketSU->isSucc(SU)) {
905 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
906 // The corner case exist when there is true data
907 // dependency between candidate and one of current
908 // packet members, this dep is on predicate reg, and
909 // there already exist anti dep on the same pred in
911 if (PacketSU->Succs[i].getSUnit() == SU &&
912 PacketSU->Succs[i].getKind() == SDep::Data &&
913 Hexagon::PredRegsRegClass.contains(
914 PacketSU->Succs[i].getReg()) &&
915 // Here I know that *VIN is predicate setting instruction
916 // with true data dep to candidate on the register
917 // we care about - c) in the above example.
918 // Now I need to see if there is an anti dependency
919 // from c) to any other instruction in the
920 // same packet on the pred reg of interest
921 RestrictingDepExistInPacket(*VIN,PacketSU->Succs[i].getReg(),
929 // If the above case does not apply, check regular
930 // complement condition.
931 // Check that the predicate register is the same and
932 // that the predicate sense is different
933 // We also need to differentiate .old vs. .new:
934 // !p0 is not complimentary to p0.new
935 unsigned PReg1 = getPredicatedRegister(MI1, QII);
936 unsigned PReg2 = getPredicatedRegister(MI2, QII);
937 return ((PReg1 == PReg2) &&
938 Hexagon::PredRegsRegClass.contains(PReg1) &&
939 Hexagon::PredRegsRegClass.contains(PReg2) &&
940 (getPredicateSense(MI1, QII) != getPredicateSense(MI2, QII)) &&
941 (QII->isDotNewInst(MI1) == QII->isDotNewInst(MI2)));
944 // initPacketizerState - Initialize packetizer flags
945 void HexagonPacketizerList::initPacketizerState() {
948 PromotedToDotNew = false;
949 GlueToNewValueJump = false;
950 GlueAllocframeStore = false;
951 FoundSequentialDependence = false;
956 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
957 bool HexagonPacketizerList::ignorePseudoInstruction(MachineInstr *MI,
958 MachineBasicBlock *MBB) {
959 if (MI->isDebugValue())
962 // We must print out inline assembly
963 if (MI->isInlineAsm())
966 // We check if MI has any functional units mapped to it.
967 // If it doesn't, we ignore the instruction.
968 const MCInstrDesc& TID = MI->getDesc();
969 unsigned SchedClass = TID.getSchedClass();
970 const InstrStage* IS =
971 ResourceTracker->getInstrItins()->beginStage(SchedClass);
972 unsigned FuncUnits = IS->getUnits();
976 // isSoloInstruction: - Returns true for instructions that must be
977 // scheduled in their own packet.
978 bool HexagonPacketizerList::isSoloInstruction(MachineInstr *MI) {
980 if (MI->isInlineAsm())
986 // From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
987 // trap, pause, barrier, icinva, isync, and syncht are solo instructions.
988 // They must not be grouped with other instructions in a packet.
989 if (IsSchedBarrier(MI))
995 // isLegalToPacketizeTogether:
996 // SUI is the current instruction that is out side of the current packet.
997 // SUJ is the current instruction inside the current packet against which that
998 // SUI will be packetized.
999 bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
1000 MachineInstr *I = SUI->getInstr();
1001 MachineInstr *J = SUJ->getInstr();
1002 assert(I && J && "Unable to packetize null instruction!");
1004 const MCInstrDesc &MCIDI = I->getDesc();
1005 const MCInstrDesc &MCIDJ = J->getDesc();
1007 MachineBasicBlock::iterator II = I;
1009 const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
1010 const HexagonRegisterInfo *QRI =
1011 (const HexagonRegisterInfo *)TM.getSubtargetImpl()->getRegisterInfo();
1012 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1014 // Inline asm cannot go in the packet.
1015 if (I->getOpcode() == Hexagon::INLINEASM)
1016 llvm_unreachable("Should not meet inline asm here!");
1018 if (isSoloInstruction(I))
1019 llvm_unreachable("Should not meet solo instr here!");
1021 // A save callee-save register function call can only be in a packet
1022 // with instructions that don't write to the callee-save registers.
1023 if ((QII->isSaveCalleeSavedRegsCall(I) &&
1024 DoesModifyCalleeSavedReg(J, QRI)) ||
1025 (QII->isSaveCalleeSavedRegsCall(J) &&
1026 DoesModifyCalleeSavedReg(I, QRI))) {
1031 // Two control flow instructions cannot go in the same packet.
1032 if (IsControlFlow(I) && IsControlFlow(J)) {
1037 // A LoopN instruction cannot appear in the same packet as a jump or call.
1039 (IsDirectJump(J) || MCIDJ.isCall() || QII->isDeallocRet(J))) {
1044 (IsDirectJump(I) || MCIDI.isCall() || QII->isDeallocRet(I))) {
1049 // dealloc_return cannot appear in the same packet as a conditional or
1050 // unconditional jump.
1051 if (QII->isDeallocRet(I) &&
1052 (MCIDJ.isBranch() || MCIDJ.isCall() || MCIDJ.isBarrier())) {
1058 // V4 allows dual store. But does not allow second store, if the
1059 // first store is not in SLOT0. New value store, new value jump,
1060 // dealloc_return and memop always take SLOT0.
1061 // Arch spec 3.4.4.2
1062 if (QRI->Subtarget.hasV4TOps()) {
1063 if (MCIDI.mayStore() && MCIDJ.mayStore() &&
1064 (QII->isNewValueInst(J) || QII->isMemOp(J) || QII->isMemOp(I))) {
1069 if ((QII->isMemOp(J) && MCIDI.mayStore())
1070 || (MCIDJ.mayStore() && QII->isMemOp(I))
1071 || (QII->isMemOp(J) && QII->isMemOp(I))) {
1077 if (MCIDJ.mayStore() && QII->isDeallocRet(I)) {
1082 // If an instruction feeds new value jump, glue it.
1083 MachineBasicBlock::iterator NextMII = I;
1085 if (NextMII != I->getParent()->end() && QII->isNewValueJump(NextMII)) {
1086 MachineInstr *NextMI = NextMII;
1088 bool secondRegMatch = false;
1089 bool maintainNewValueJump = false;
1091 if (NextMI->getOperand(1).isReg() &&
1092 I->getOperand(0).getReg() == NextMI->getOperand(1).getReg()) {
1093 secondRegMatch = true;
1094 maintainNewValueJump = true;
1097 if (!secondRegMatch &&
1098 I->getOperand(0).getReg() == NextMI->getOperand(0).getReg()) {
1099 maintainNewValueJump = true;
1102 for (std::vector<MachineInstr*>::iterator
1103 VI = CurrentPacketMIs.begin(),
1104 VE = CurrentPacketMIs.end();
1105 (VI != VE && maintainNewValueJump); ++VI) {
1106 SUnit* PacketSU = MIToSUnit[*VI];
1108 // NVJ can not be part of the dual jump - Arch Spec: section 7.8
1109 if (PacketSU->getInstr()->getDesc().isCall()) {
1114 // 1. Packet does not have a store in it.
1115 // 2. If the first operand of the nvj is newified, and the second
1116 // operand is also a reg, it (second reg) is not defined in
1118 // 3. If the second operand of the nvj is newified, (which means
1119 // first operand is also a reg), first reg is not defined in
1121 if (PacketSU->getInstr()->getDesc().mayStore() ||
1122 PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
1124 (!secondRegMatch && NextMI->getOperand(1).isReg() &&
1125 PacketSU->getInstr()->modifiesRegister(
1126 NextMI->getOperand(1).getReg(), QRI)) ||
1129 PacketSU->getInstr()->modifiesRegister(
1130 NextMI->getOperand(0).getReg(), QRI))) {
1136 GlueToNewValueJump = true;
1142 if (SUJ->isSucc(SUI)) {
1143 for (unsigned i = 0;
1144 (i < SUJ->Succs.size()) && !FoundSequentialDependence;
1147 if (SUJ->Succs[i].getSUnit() != SUI) {
1151 SDep::Kind DepType = SUJ->Succs[i].getKind();
1153 // For direct calls:
1154 // Ignore register dependences for call instructions for
1155 // packetization purposes except for those due to r31 and
1156 // predicate registers.
1158 // For indirect calls:
1159 // Same as direct calls + check for true dependences to the register
1160 // used in the indirect call.
1162 // We completely ignore Order dependences for call instructions
1165 // Ignore register dependences for return instructions like jumpr,
1166 // dealloc return unless we have dependencies on the explicit uses
1167 // of the registers used by jumpr (like r31) or dealloc return
1168 // (like r29 or r30).
1170 // TODO: Currently, jumpr is handling only return of r31. So, the
1171 // following logic (specificaly IsCallDependent) is working fine.
1172 // We need to enable jumpr for register other than r31 and then,
1173 // we need to rework the last part, where it handles indirect call
1174 // of that (IsCallDependent) function. Bug 6216 is opened for this.
1176 unsigned DepReg = 0;
1177 const TargetRegisterClass* RC = nullptr;
1178 if (DepType == SDep::Data) {
1179 DepReg = SUJ->Succs[i].getReg();
1180 RC = QRI->getMinimalPhysRegClass(DepReg);
1182 if ((MCIDI.isCall() || MCIDI.isReturn()) &&
1183 (!IsRegDependence(DepType) ||
1184 !IsCallDependent(I, DepType, SUJ->Succs[i].getReg()))) {
1188 // For instructions that can be promoted to dot-new, try to promote.
1189 else if ((DepType == SDep::Data) &&
1190 CanPromoteToDotNew(I, SUJ, DepReg, MIToSUnit, II, RC) &&
1191 PromoteToDotNew(I, DepType, II, RC)) {
1192 PromotedToDotNew = true;
1196 else if ((DepType == SDep::Data) &&
1197 (QII->isNewValueJump(I))) {
1201 // For predicated instructions, if the predicates are complements
1202 // then there can be no dependence.
1203 else if (QII->isPredicated(I) &&
1204 QII->isPredicated(J) &&
1205 ArePredicatesComplements(I, J, MIToSUnit)) {
1209 else if (IsDirectJump(I) &&
1210 !MCIDJ.isBranch() &&
1212 (DepType == SDep::Order)) {
1213 // Ignore Order dependences between unconditional direct branches
1214 // and non-control-flow instructions
1217 else if (MCIDI.isConditionalBranch() && (DepType != SDep::Data) &&
1218 (DepType != SDep::Output)) {
1219 // Ignore all dependences for jumps except for true and output
1224 // Ignore output dependences due to superregs. We can
1225 // write to two different subregisters of R1:0 for instance
1226 // in the same cycle
1231 // If neither I nor J defines DepReg, then this is a
1232 // superfluous output dependence. The dependence must be of the
1236 // and there is an output dependence between the two instructions
1239 // We want to ignore these dependences.
1240 // Ideally, the dependence constructor should annotate such
1241 // dependences. We can then avoid this relatively expensive check.
1243 else if (DepType == SDep::Output) {
1244 // DepReg is the register that's responsible for the dependence.
1245 unsigned DepReg = SUJ->Succs[i].getReg();
1247 // Check if I and J really defines DepReg.
1248 if (I->definesRegister(DepReg) ||
1249 J->definesRegister(DepReg)) {
1250 FoundSequentialDependence = true;
1255 // We ignore Order dependences for
1256 // 1. Two loads unless they are volatile.
1257 // 2. Two stores in V4 unless they are volatile.
1258 else if ((DepType == SDep::Order) &&
1259 !I->hasOrderedMemoryRef() &&
1260 !J->hasOrderedMemoryRef()) {
1261 if (QRI->Subtarget.hasV4TOps() &&
1262 // hexagonv4 allows dual store.
1263 MCIDI.mayStore() && MCIDJ.mayStore()) {
1266 // store followed by store-- not OK on V2
1267 // store followed by load -- not OK on all (OK if addresses
1269 // load followed by store -- OK on all
1270 // load followed by load -- OK on all
1271 else if ( !MCIDJ.mayStore()) {
1275 FoundSequentialDependence = true;
1280 // For V4, special case ALLOCFRAME. Even though there is dependency
1281 // between ALLOCAFRAME and subsequent store, allow it to be
1282 // packetized in a same packet. This implies that the store is using
1283 // caller's SP. Hense, offset needs to be updated accordingly.
1284 else if (DepType == SDep::Data
1285 && QRI->Subtarget.hasV4TOps()
1286 && J->getOpcode() == Hexagon::ALLOCFRAME
1287 && (I->getOpcode() == Hexagon::STrid
1288 || I->getOpcode() == Hexagon::STriw
1289 || I->getOpcode() == Hexagon::STrib)
1290 && I->getOperand(0).getReg() == QRI->getStackRegister()
1291 && QII->isValidOffset(I->getOpcode(),
1292 I->getOperand(1).getImm() -
1293 (FrameSize + HEXAGON_LRFP_SIZE)))
1295 GlueAllocframeStore = true;
1296 // Since this store is to be glued with allocframe in the same
1297 // packet, it will use SP of the previous stack frame, i.e
1298 // caller's SP. Therefore, we need to recalculate offset according
1300 I->getOperand(1).setImm(I->getOperand(1).getImm() -
1301 (FrameSize + HEXAGON_LRFP_SIZE));
1305 // Skip over anti-dependences. Two instructions that are
1306 // anti-dependent can share a packet
1308 else if (DepType != SDep::Anti) {
1309 FoundSequentialDependence = true;
1314 if (FoundSequentialDependence) {
1323 // isLegalToPruneDependencies
1324 bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
1325 MachineInstr *I = SUI->getInstr();
1326 assert(I && SUJ->getInstr() && "Unable to packetize null instruction!");
1328 const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
1332 // Check if the instruction was promoted to a dot-new. If so, demote it
1333 // back into a dot-old.
1334 if (PromotedToDotNew) {
1338 // Check if the instruction (must be a store) was glued with an Allocframe
1339 // instruction. If so, restore its offset to its original value, i.e. use
1340 // curent SP instead of caller's SP.
1341 if (GlueAllocframeStore) {
1342 I->getOperand(1).setImm(I->getOperand(1).getImm() +
1343 FrameSize + HEXAGON_LRFP_SIZE);
1351 MachineBasicBlock::iterator
1352 HexagonPacketizerList::addToPacket(MachineInstr *MI) {
1354 MachineBasicBlock::iterator MII = MI;
1355 MachineBasicBlock *MBB = MI->getParent();
1357 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1359 if (GlueToNewValueJump) {
1362 MachineInstr *nvjMI = MII;
1363 assert(ResourceTracker->canReserveResources(MI));
1364 ResourceTracker->reserveResources(MI);
1365 if ((QII->isExtended(MI) || QII->isConstExtended(MI)) &&
1366 !tryAllocateResourcesForConstExt(MI)) {
1368 ResourceTracker->reserveResources(MI);
1369 assert(canReserveResourcesForConstExt(MI) &&
1370 "Ensure that there is a slot");
1371 reserveResourcesForConstExt(MI);
1372 // Reserve resources for new value jump constant extender.
1373 assert(canReserveResourcesForConstExt(MI) &&
1374 "Ensure that there is a slot");
1375 reserveResourcesForConstExt(nvjMI);
1376 assert(ResourceTracker->canReserveResources(nvjMI) &&
1377 "Ensure that there is a slot");
1379 } else if ( // Extended instruction takes two slots in the packet.
1380 // Try reserve and allocate 4-byte in the current packet first.
1381 (QII->isExtended(nvjMI)
1382 && (!tryAllocateResourcesForConstExt(nvjMI)
1383 || !ResourceTracker->canReserveResources(nvjMI)))
1384 || // For non-extended instruction, no need to allocate extra 4 bytes.
1385 (!QII->isExtended(nvjMI) &&
1386 !ResourceTracker->canReserveResources(nvjMI)))
1389 // A new and empty packet starts.
1390 // We are sure that the resources requirements can be satisfied.
1391 // Therefore, do not need to call "canReserveResources" anymore.
1392 ResourceTracker->reserveResources(MI);
1393 if (QII->isExtended(nvjMI))
1394 reserveResourcesForConstExt(nvjMI);
1396 // Here, we are sure that "reserveResources" would succeed.
1397 ResourceTracker->reserveResources(nvjMI);
1398 CurrentPacketMIs.push_back(MI);
1399 CurrentPacketMIs.push_back(nvjMI);
1401 if ( (QII->isExtended(MI) || QII->isConstExtended(MI))
1402 && ( !tryAllocateResourcesForConstExt(MI)
1403 || !ResourceTracker->canReserveResources(MI)))
1406 // Check if the instruction was promoted to a dot-new. If so, demote it
1407 // back into a dot-old
1408 if (PromotedToDotNew) {
1411 reserveResourcesForConstExt(MI);
1413 // In case that "MI" is not an extended insn,
1414 // the resource availability has already been checked.
1415 ResourceTracker->reserveResources(MI);
1416 CurrentPacketMIs.push_back(MI);
1421 //===----------------------------------------------------------------------===//
1422 // Public Constructor Functions
1423 //===----------------------------------------------------------------------===//
1425 FunctionPass *llvm::createHexagonPacketizer() {
1426 return new HexagonPacketizer();