1 //===----- HexagonPacketizer.cpp - vliw packetizer ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements a simple VLIW packetizer using DFA. The packetizer works on
11 // machine basic blocks. For each instruction I in BB, the packetizer consults
12 // the DFA to see if machine resources are available to execute I. If so, the
13 // packetizer checks if I depends on any instruction J in the current packet.
14 // If no dependency is found, I is added to current packet and machine resource
15 // is marked as taken. If any dependency is found, a target API call is made to
16 // prune the dependence.
18 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "packets"
20 #include "llvm/CodeGen/DFAPacketizer.h"
21 #include "llvm/CodeGen/Passes.h"
22 #include "llvm/CodeGen/MachineDominators.h"
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/MachineLoopInfo.h"
25 #include "llvm/CodeGen/ScheduleDAG.h"
26 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
27 #include "llvm/CodeGen/LatencyPriorityQueue.h"
28 #include "llvm/CodeGen/SchedulerRegistry.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
32 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
33 #include "llvm/CodeGen/ScheduleHazardRecognizer.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetRegisterInfo.h"
37 #include "llvm/ADT/DenseMap.h"
38 #include "llvm/ADT/Statistic.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/MC/MCInstrItineraries.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/Debug.h"
45 #include "HexagonTargetMachine.h"
46 #include "HexagonRegisterInfo.h"
47 #include "HexagonSubtarget.h"
48 #include "HexagonMachineFunctionInfo.h"
55 class HexagonPacketizer : public MachineFunctionPass {
59 HexagonPacketizer() : MachineFunctionPass(ID) {}
61 void getAnalysisUsage(AnalysisUsage &AU) const {
63 AU.addRequired<MachineDominatorTree>();
64 AU.addPreserved<MachineDominatorTree>();
65 AU.addRequired<MachineLoopInfo>();
66 AU.addPreserved<MachineLoopInfo>();
67 MachineFunctionPass::getAnalysisUsage(AU);
70 const char *getPassName() const {
71 return "Hexagon Packetizer";
74 bool runOnMachineFunction(MachineFunction &Fn);
76 char HexagonPacketizer::ID = 0;
78 class HexagonPacketizerList : public VLIWPacketizerList {
82 // Has the instruction been promoted to a dot-new instruction.
83 bool PromotedToDotNew;
85 // Has the instruction been glued to allocframe.
86 bool GlueAllocframeStore;
88 // Has the feeder instruction been glued to new value jump.
89 bool GlueToNewValueJump;
91 // Check if there is a dependence between some instruction already in this
92 // packet and this instruction.
95 // Only check for dependence if there are resources available to
96 // schedule this instruction.
97 bool FoundSequentialDependence;
101 HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
102 MachineDominatorTree &MDT);
104 // initPacketizerState - initialize some internal flags.
105 void initPacketizerState();
107 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
108 bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB);
110 // isSoloInstruction - return true if instruction MI can not be packetized
111 // with any other instruction, which means that MI itself is a packet.
112 bool isSoloInstruction(MachineInstr *MI);
114 // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
116 bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ);
118 // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
120 bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ);
122 MachineBasicBlock::iterator addToPacket(MachineInstr *MI);
124 bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg);
125 bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
126 MachineBasicBlock::iterator &MII,
127 const TargetRegisterClass* RC);
128 bool CanPromoteToDotNew(MachineInstr* MI, SUnit* PacketSU,
130 std::map <MachineInstr*, SUnit*> MIToSUnit,
131 MachineBasicBlock::iterator &MII,
132 const TargetRegisterClass* RC);
133 bool CanPromoteToNewValue(MachineInstr* MI, SUnit* PacketSU,
135 std::map <MachineInstr*, SUnit*> MIToSUnit,
136 MachineBasicBlock::iterator &MII);
137 bool CanPromoteToNewValueStore(MachineInstr* MI, MachineInstr* PacketMI,
139 std::map <MachineInstr*, SUnit*> MIToSUnit);
140 bool DemoteToDotOld(MachineInstr* MI);
141 bool ArePredicatesComplements(MachineInstr* MI1, MachineInstr* MI2,
142 std::map <MachineInstr*, SUnit*> MIToSUnit);
143 bool RestrictingDepExistInPacket(MachineInstr*,
144 unsigned, std::map <MachineInstr*, SUnit*>);
145 bool isNewifiable(MachineInstr* MI);
146 bool isCondInst(MachineInstr* MI);
147 bool IsNewifyStore (MachineInstr* MI);
148 bool tryAllocateResourcesForConstExt(MachineInstr* MI);
149 bool canReserveResourcesForConstExt(MachineInstr *MI);
150 void reserveResourcesForConstExt(MachineInstr* MI);
151 bool isNewValueInst(MachineInstr* MI);
152 bool isDotNewInst(MachineInstr* MI);
156 // HexagonPacketizerList Ctor.
157 HexagonPacketizerList::HexagonPacketizerList(
158 MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT)
159 : VLIWPacketizerList(MF, MLI, MDT, true){
162 bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) {
163 const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
164 MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
165 MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
167 // Instantiate the packetizer.
168 HexagonPacketizerList Packetizer(Fn, MLI, MDT);
170 // DFA state table should not be empty.
171 assert(Packetizer.getResourceTracker() && "Empty DFA table!");
174 // Loop over all basic blocks and remove KILL pseudo-instructions
175 // These instructions confuse the dependence analysis. Consider:
177 // R0 = KILL R0, D0 (Insn 1)
179 // Here, Insn 1 will result in the dependence graph not emitting an output
180 // dependence between Insn 0 and Insn 2. This can lead to incorrect
183 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
184 MBB != MBBe; ++MBB) {
185 MachineBasicBlock::iterator End = MBB->end();
186 MachineBasicBlock::iterator MI = MBB->begin();
189 MachineBasicBlock::iterator DeleteMI = MI;
191 MBB->erase(DeleteMI);
199 // Loop over all of the basic blocks.
200 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
201 MBB != MBBe; ++MBB) {
202 // Find scheduling regions and schedule / packetize each region.
203 unsigned RemainingCount = MBB->size();
204 for(MachineBasicBlock::iterator RegionEnd = MBB->end();
205 RegionEnd != MBB->begin();) {
206 // The next region starts above the previous region. Look backward in the
207 // instruction stream until we find the nearest boundary.
208 MachineBasicBlock::iterator I = RegionEnd;
209 for(;I != MBB->begin(); --I, --RemainingCount) {
210 if (TII->isSchedulingBoundary(llvm::prior(I), MBB, Fn))
215 // Skip empty scheduling regions.
216 if (I == RegionEnd) {
217 RegionEnd = llvm::prior(RegionEnd);
221 // Skip regions with one instruction.
222 if (I == llvm::prior(RegionEnd)) {
223 RegionEnd = llvm::prior(RegionEnd);
227 Packetizer.PacketizeMIs(MBB, I, RegionEnd);
236 static bool IsIndirectCall(MachineInstr* MI) {
237 return ((MI->getOpcode() == Hexagon::CALLR) ||
238 (MI->getOpcode() == Hexagon::CALLRv3));
241 // Reserve resources for constant extender. Trigure an assertion if
243 void HexagonPacketizerList::reserveResourcesForConstExt(MachineInstr* MI) {
244 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
245 MachineInstr *PseudoMI = MI->getParent()->getParent()->CreateMachineInstr(
246 QII->get(Hexagon::IMMEXT), MI->getDebugLoc());
248 if (ResourceTracker->canReserveResources(PseudoMI)) {
249 ResourceTracker->reserveResources(PseudoMI);
250 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
252 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
253 llvm_unreachable("can not reserve resources for constant extender.");
258 bool HexagonPacketizerList::canReserveResourcesForConstExt(MachineInstr *MI) {
259 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
260 assert(QII->isExtended(MI) &&
261 "Should only be called for constant extended instructions");
262 MachineFunction *MF = MI->getParent()->getParent();
263 MachineInstr *PseudoMI = MF->CreateMachineInstr(QII->get(Hexagon::IMMEXT),
265 bool CanReserve = ResourceTracker->canReserveResources(PseudoMI);
266 MF->DeleteMachineInstr(PseudoMI);
270 // Allocate resources (i.e. 4 bytes) for constant extender. If succeed, return
271 // true, otherwise, return false.
272 bool HexagonPacketizerList::tryAllocateResourcesForConstExt(MachineInstr* MI) {
273 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
274 MachineInstr *PseudoMI = MI->getParent()->getParent()->CreateMachineInstr(
275 QII->get(Hexagon::IMMEXT), MI->getDebugLoc());
277 if (ResourceTracker->canReserveResources(PseudoMI)) {
278 ResourceTracker->reserveResources(PseudoMI);
279 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
282 MI->getParent()->getParent()->DeleteMachineInstr(PseudoMI);
288 bool HexagonPacketizerList::IsCallDependent(MachineInstr* MI,
292 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
293 const HexagonRegisterInfo* QRI =
294 (const HexagonRegisterInfo *) TM.getRegisterInfo();
296 // Check for lr dependence
297 if (DepReg == QRI->getRARegister()) {
301 if (QII->isDeallocRet(MI)) {
302 if (DepReg == QRI->getFrameRegister() ||
303 DepReg == QRI->getStackRegister())
307 // Check if this is a predicate dependence
308 const TargetRegisterClass* RC = QRI->getMinimalPhysRegClass(DepReg);
309 if (RC == &Hexagon::PredRegsRegClass) {
314 // Lastly check for an operand used in an indirect call
315 // If we had an attribute for checking if an instruction is an indirect call,
316 // then we could have avoided this relatively brittle implementation of
319 // Assumes that the first operand of the CALLr is the function address
321 if (IsIndirectCall(MI) && (DepType == SDep::Data)) {
322 MachineOperand MO = MI->getOperand(0);
323 if (MO.isReg() && MO.isUse() && (MO.getReg() == DepReg)) {
331 static bool IsRegDependence(const SDep::Kind DepType) {
332 return (DepType == SDep::Data || DepType == SDep::Anti ||
333 DepType == SDep::Output);
336 static bool IsDirectJump(MachineInstr* MI) {
337 return (MI->getOpcode() == Hexagon::JMP);
340 static bool IsSchedBarrier(MachineInstr* MI) {
341 switch (MI->getOpcode()) {
342 case Hexagon::BARRIER:
348 static bool IsControlFlow(MachineInstr* MI) {
349 return (MI->getDesc().isTerminator() || MI->getDesc().isCall());
352 bool HexagonPacketizerList::isNewValueInst(MachineInstr* MI) {
353 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
354 if (QII->isNewValueJump(MI))
357 if (QII->isNewValueStore(MI))
363 // Function returns true if an instruction can be promoted to the new-value
364 // store. It will always return false for v2 and v3.
365 // It lists all the conditional and unconditional stores that can be promoted
366 // to the new-value stores.
368 bool HexagonPacketizerList::IsNewifyStore (MachineInstr* MI) {
369 const HexagonRegisterInfo* QRI =
370 (const HexagonRegisterInfo *) TM.getRegisterInfo();
371 switch (MI->getOpcode())
375 case Hexagon::STrib_indexed:
376 case Hexagon::STrib_indexed_shl_V4:
377 case Hexagon::STrib_shl_V4:
378 case Hexagon::STrib_GP_V4:
379 case Hexagon::STb_GP_V4:
380 case Hexagon::POST_STbri:
381 case Hexagon::STrib_cPt:
382 case Hexagon::STrib_cdnPt_V4:
383 case Hexagon::STrib_cNotPt:
384 case Hexagon::STrib_cdnNotPt_V4:
385 case Hexagon::STrib_indexed_cPt:
386 case Hexagon::STrib_indexed_cdnPt_V4:
387 case Hexagon::STrib_indexed_cNotPt:
388 case Hexagon::STrib_indexed_cdnNotPt_V4:
389 case Hexagon::STrib_indexed_shl_cPt_V4:
390 case Hexagon::STrib_indexed_shl_cdnPt_V4:
391 case Hexagon::STrib_indexed_shl_cNotPt_V4:
392 case Hexagon::STrib_indexed_shl_cdnNotPt_V4:
393 case Hexagon::POST_STbri_cPt:
394 case Hexagon::POST_STbri_cdnPt_V4:
395 case Hexagon::POST_STbri_cNotPt:
396 case Hexagon::POST_STbri_cdnNotPt_V4:
397 case Hexagon::STb_GP_cPt_V4:
398 case Hexagon::STb_GP_cNotPt_V4:
399 case Hexagon::STb_GP_cdnPt_V4:
400 case Hexagon::STb_GP_cdnNotPt_V4:
401 case Hexagon::STrib_GP_cPt_V4:
402 case Hexagon::STrib_GP_cNotPt_V4:
403 case Hexagon::STrib_GP_cdnPt_V4:
404 case Hexagon::STrib_GP_cdnNotPt_V4:
408 case Hexagon::STrih_indexed:
409 case Hexagon::STrih_indexed_shl_V4:
410 case Hexagon::STrih_shl_V4:
411 case Hexagon::STrih_GP_V4:
412 case Hexagon::STh_GP_V4:
413 case Hexagon::POST_SThri:
414 case Hexagon::STrih_cPt:
415 case Hexagon::STrih_cdnPt_V4:
416 case Hexagon::STrih_cNotPt:
417 case Hexagon::STrih_cdnNotPt_V4:
418 case Hexagon::STrih_indexed_cPt:
419 case Hexagon::STrih_indexed_cdnPt_V4:
420 case Hexagon::STrih_indexed_cNotPt:
421 case Hexagon::STrih_indexed_cdnNotPt_V4:
422 case Hexagon::STrih_indexed_shl_cPt_V4:
423 case Hexagon::STrih_indexed_shl_cdnPt_V4:
424 case Hexagon::STrih_indexed_shl_cNotPt_V4:
425 case Hexagon::STrih_indexed_shl_cdnNotPt_V4:
426 case Hexagon::POST_SThri_cPt:
427 case Hexagon::POST_SThri_cdnPt_V4:
428 case Hexagon::POST_SThri_cNotPt:
429 case Hexagon::POST_SThri_cdnNotPt_V4:
430 case Hexagon::STh_GP_cPt_V4:
431 case Hexagon::STh_GP_cNotPt_V4:
432 case Hexagon::STh_GP_cdnPt_V4:
433 case Hexagon::STh_GP_cdnNotPt_V4:
434 case Hexagon::STrih_GP_cPt_V4:
435 case Hexagon::STrih_GP_cNotPt_V4:
436 case Hexagon::STrih_GP_cdnPt_V4:
437 case Hexagon::STrih_GP_cdnNotPt_V4:
441 case Hexagon::STriw_indexed:
442 case Hexagon::STriw_indexed_shl_V4:
443 case Hexagon::STriw_shl_V4:
444 case Hexagon::STriw_GP_V4:
445 case Hexagon::STw_GP_V4:
446 case Hexagon::POST_STwri:
447 case Hexagon::STriw_cPt:
448 case Hexagon::STriw_cdnPt_V4:
449 case Hexagon::STriw_cNotPt:
450 case Hexagon::STriw_cdnNotPt_V4:
451 case Hexagon::STriw_indexed_cPt:
452 case Hexagon::STriw_indexed_cdnPt_V4:
453 case Hexagon::STriw_indexed_cNotPt:
454 case Hexagon::STriw_indexed_cdnNotPt_V4:
455 case Hexagon::STriw_indexed_shl_cPt_V4:
456 case Hexagon::STriw_indexed_shl_cdnPt_V4:
457 case Hexagon::STriw_indexed_shl_cNotPt_V4:
458 case Hexagon::STriw_indexed_shl_cdnNotPt_V4:
459 case Hexagon::POST_STwri_cPt:
460 case Hexagon::POST_STwri_cdnPt_V4:
461 case Hexagon::POST_STwri_cNotPt:
462 case Hexagon::POST_STwri_cdnNotPt_V4:
463 case Hexagon::STw_GP_cPt_V4:
464 case Hexagon::STw_GP_cNotPt_V4:
465 case Hexagon::STw_GP_cdnPt_V4:
466 case Hexagon::STw_GP_cdnNotPt_V4:
467 case Hexagon::STriw_GP_cPt_V4:
468 case Hexagon::STriw_GP_cNotPt_V4:
469 case Hexagon::STriw_GP_cdnPt_V4:
470 case Hexagon::STriw_GP_cdnNotPt_V4:
471 return QRI->Subtarget.hasV4TOps();
476 static bool IsLoopN(MachineInstr *MI) {
477 return (MI->getOpcode() == Hexagon::LOOP0_i ||
478 MI->getOpcode() == Hexagon::LOOP0_r);
481 /// DoesModifyCalleeSavedReg - Returns true if the instruction modifies a
482 /// callee-saved register.
483 static bool DoesModifyCalleeSavedReg(MachineInstr *MI,
484 const TargetRegisterInfo *TRI) {
485 for (const uint16_t *CSR = TRI->getCalleeSavedRegs(); *CSR; ++CSR) {
486 unsigned CalleeSavedReg = *CSR;
487 if (MI->modifiesRegister(CalleeSavedReg, TRI))
493 // Return the new value instruction for a given store.
494 static int GetDotNewOp(const int opc) {
496 default: llvm_unreachable("Unknown .new type");
497 // store new value byte
499 return Hexagon::STrib_nv_V4;
501 case Hexagon::STrib_indexed:
502 return Hexagon::STrib_indexed_nv_V4;
504 case Hexagon::STrib_indexed_shl_V4:
505 return Hexagon::STrib_indexed_shl_nv_V4;
507 case Hexagon::STrib_shl_V4:
508 return Hexagon::STrib_shl_nv_V4;
510 case Hexagon::STrib_GP_V4:
511 return Hexagon::STrib_GP_nv_V4;
513 case Hexagon::STb_GP_V4:
514 return Hexagon::STb_GP_nv_V4;
516 case Hexagon::POST_STbri:
517 return Hexagon::POST_STbri_nv_V4;
519 case Hexagon::STrib_cPt:
520 return Hexagon::STrib_cPt_nv_V4;
522 case Hexagon::STrib_cdnPt_V4:
523 return Hexagon::STrib_cdnPt_nv_V4;
525 case Hexagon::STrib_cNotPt:
526 return Hexagon::STrib_cNotPt_nv_V4;
528 case Hexagon::STrib_cdnNotPt_V4:
529 return Hexagon::STrib_cdnNotPt_nv_V4;
531 case Hexagon::STrib_indexed_cPt:
532 return Hexagon::STrib_indexed_cPt_nv_V4;
534 case Hexagon::STrib_indexed_cdnPt_V4:
535 return Hexagon::STrib_indexed_cdnPt_nv_V4;
537 case Hexagon::STrib_indexed_cNotPt:
538 return Hexagon::STrib_indexed_cNotPt_nv_V4;
540 case Hexagon::STrib_indexed_cdnNotPt_V4:
541 return Hexagon::STrib_indexed_cdnNotPt_nv_V4;
543 case Hexagon::STrib_indexed_shl_cPt_V4:
544 return Hexagon::STrib_indexed_shl_cPt_nv_V4;
546 case Hexagon::STrib_indexed_shl_cdnPt_V4:
547 return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;
549 case Hexagon::STrib_indexed_shl_cNotPt_V4:
550 return Hexagon::STrib_indexed_shl_cNotPt_nv_V4;
552 case Hexagon::STrib_indexed_shl_cdnNotPt_V4:
553 return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;
555 case Hexagon::POST_STbri_cPt:
556 return Hexagon::POST_STbri_cPt_nv_V4;
558 case Hexagon::POST_STbri_cdnPt_V4:
559 return Hexagon::POST_STbri_cdnPt_nv_V4;
561 case Hexagon::POST_STbri_cNotPt:
562 return Hexagon::POST_STbri_cNotPt_nv_V4;
564 case Hexagon::POST_STbri_cdnNotPt_V4:
565 return Hexagon::POST_STbri_cdnNotPt_nv_V4;
567 case Hexagon::STb_GP_cPt_V4:
568 return Hexagon::STb_GP_cPt_nv_V4;
570 case Hexagon::STb_GP_cNotPt_V4:
571 return Hexagon::STb_GP_cNotPt_nv_V4;
573 case Hexagon::STb_GP_cdnPt_V4:
574 return Hexagon::STb_GP_cdnPt_nv_V4;
576 case Hexagon::STb_GP_cdnNotPt_V4:
577 return Hexagon::STb_GP_cdnNotPt_nv_V4;
579 case Hexagon::STrib_GP_cPt_V4:
580 return Hexagon::STrib_GP_cPt_nv_V4;
582 case Hexagon::STrib_GP_cNotPt_V4:
583 return Hexagon::STrib_GP_cNotPt_nv_V4;
585 case Hexagon::STrib_GP_cdnPt_V4:
586 return Hexagon::STrib_GP_cdnPt_nv_V4;
588 case Hexagon::STrib_GP_cdnNotPt_V4:
589 return Hexagon::STrib_GP_cdnNotPt_nv_V4;
591 // store new value halfword
593 return Hexagon::STrih_nv_V4;
595 case Hexagon::STrih_indexed:
596 return Hexagon::STrih_indexed_nv_V4;
598 case Hexagon::STrih_indexed_shl_V4:
599 return Hexagon::STrih_indexed_shl_nv_V4;
601 case Hexagon::STrih_shl_V4:
602 return Hexagon::STrih_shl_nv_V4;
604 case Hexagon::STrih_GP_V4:
605 return Hexagon::STrih_GP_nv_V4;
607 case Hexagon::STh_GP_V4:
608 return Hexagon::STh_GP_nv_V4;
610 case Hexagon::POST_SThri:
611 return Hexagon::POST_SThri_nv_V4;
613 case Hexagon::STrih_cPt:
614 return Hexagon::STrih_cPt_nv_V4;
616 case Hexagon::STrih_cdnPt_V4:
617 return Hexagon::STrih_cdnPt_nv_V4;
619 case Hexagon::STrih_cNotPt:
620 return Hexagon::STrih_cNotPt_nv_V4;
622 case Hexagon::STrih_cdnNotPt_V4:
623 return Hexagon::STrih_cdnNotPt_nv_V4;
625 case Hexagon::STrih_indexed_cPt:
626 return Hexagon::STrih_indexed_cPt_nv_V4;
628 case Hexagon::STrih_indexed_cdnPt_V4:
629 return Hexagon::STrih_indexed_cdnPt_nv_V4;
631 case Hexagon::STrih_indexed_cNotPt:
632 return Hexagon::STrih_indexed_cNotPt_nv_V4;
634 case Hexagon::STrih_indexed_cdnNotPt_V4:
635 return Hexagon::STrih_indexed_cdnNotPt_nv_V4;
637 case Hexagon::STrih_indexed_shl_cPt_V4:
638 return Hexagon::STrih_indexed_shl_cPt_nv_V4;
640 case Hexagon::STrih_indexed_shl_cdnPt_V4:
641 return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;
643 case Hexagon::STrih_indexed_shl_cNotPt_V4:
644 return Hexagon::STrih_indexed_shl_cNotPt_nv_V4;
646 case Hexagon::STrih_indexed_shl_cdnNotPt_V4:
647 return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;
649 case Hexagon::POST_SThri_cPt:
650 return Hexagon::POST_SThri_cPt_nv_V4;
652 case Hexagon::POST_SThri_cdnPt_V4:
653 return Hexagon::POST_SThri_cdnPt_nv_V4;
655 case Hexagon::POST_SThri_cNotPt:
656 return Hexagon::POST_SThri_cNotPt_nv_V4;
658 case Hexagon::POST_SThri_cdnNotPt_V4:
659 return Hexagon::POST_SThri_cdnNotPt_nv_V4;
661 case Hexagon::STh_GP_cPt_V4:
662 return Hexagon::STh_GP_cPt_nv_V4;
664 case Hexagon::STh_GP_cNotPt_V4:
665 return Hexagon::STh_GP_cNotPt_nv_V4;
667 case Hexagon::STh_GP_cdnPt_V4:
668 return Hexagon::STh_GP_cdnPt_nv_V4;
670 case Hexagon::STh_GP_cdnNotPt_V4:
671 return Hexagon::STh_GP_cdnNotPt_nv_V4;
673 case Hexagon::STrih_GP_cPt_V4:
674 return Hexagon::STrih_GP_cPt_nv_V4;
676 case Hexagon::STrih_GP_cNotPt_V4:
677 return Hexagon::STrih_GP_cNotPt_nv_V4;
679 case Hexagon::STrih_GP_cdnPt_V4:
680 return Hexagon::STrih_GP_cdnPt_nv_V4;
682 case Hexagon::STrih_GP_cdnNotPt_V4:
683 return Hexagon::STrih_GP_cdnNotPt_nv_V4;
685 // store new value word
687 return Hexagon::STriw_nv_V4;
689 case Hexagon::STriw_indexed:
690 return Hexagon::STriw_indexed_nv_V4;
692 case Hexagon::STriw_indexed_shl_V4:
693 return Hexagon::STriw_indexed_shl_nv_V4;
695 case Hexagon::STriw_shl_V4:
696 return Hexagon::STriw_shl_nv_V4;
698 case Hexagon::STriw_GP_V4:
699 return Hexagon::STriw_GP_nv_V4;
701 case Hexagon::STw_GP_V4:
702 return Hexagon::STw_GP_nv_V4;
704 case Hexagon::POST_STwri:
705 return Hexagon::POST_STwri_nv_V4;
707 case Hexagon::STriw_cPt:
708 return Hexagon::STriw_cPt_nv_V4;
710 case Hexagon::STriw_cdnPt_V4:
711 return Hexagon::STriw_cdnPt_nv_V4;
713 case Hexagon::STriw_cNotPt:
714 return Hexagon::STriw_cNotPt_nv_V4;
716 case Hexagon::STriw_cdnNotPt_V4:
717 return Hexagon::STriw_cdnNotPt_nv_V4;
719 case Hexagon::STriw_indexed_cPt:
720 return Hexagon::STriw_indexed_cPt_nv_V4;
722 case Hexagon::STriw_indexed_cdnPt_V4:
723 return Hexagon::STriw_indexed_cdnPt_nv_V4;
725 case Hexagon::STriw_indexed_cNotPt:
726 return Hexagon::STriw_indexed_cNotPt_nv_V4;
728 case Hexagon::STriw_indexed_cdnNotPt_V4:
729 return Hexagon::STriw_indexed_cdnNotPt_nv_V4;
731 case Hexagon::STriw_indexed_shl_cPt_V4:
732 return Hexagon::STriw_indexed_shl_cPt_nv_V4;
734 case Hexagon::STriw_indexed_shl_cdnPt_V4:
735 return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;
737 case Hexagon::STriw_indexed_shl_cNotPt_V4:
738 return Hexagon::STriw_indexed_shl_cNotPt_nv_V4;
740 case Hexagon::STriw_indexed_shl_cdnNotPt_V4:
741 return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;
743 case Hexagon::POST_STwri_cPt:
744 return Hexagon::POST_STwri_cPt_nv_V4;
746 case Hexagon::POST_STwri_cdnPt_V4:
747 return Hexagon::POST_STwri_cdnPt_nv_V4;
749 case Hexagon::POST_STwri_cNotPt:
750 return Hexagon::POST_STwri_cNotPt_nv_V4;
752 case Hexagon::POST_STwri_cdnNotPt_V4:
753 return Hexagon::POST_STwri_cdnNotPt_nv_V4;
755 case Hexagon::STw_GP_cPt_V4:
756 return Hexagon::STw_GP_cPt_nv_V4;
758 case Hexagon::STw_GP_cNotPt_V4:
759 return Hexagon::STw_GP_cNotPt_nv_V4;
761 case Hexagon::STw_GP_cdnPt_V4:
762 return Hexagon::STw_GP_cdnPt_nv_V4;
764 case Hexagon::STw_GP_cdnNotPt_V4:
765 return Hexagon::STw_GP_cdnNotPt_nv_V4;
767 case Hexagon::STriw_GP_cPt_V4:
768 return Hexagon::STriw_GP_cPt_nv_V4;
770 case Hexagon::STriw_GP_cNotPt_V4:
771 return Hexagon::STriw_GP_cNotPt_nv_V4;
773 case Hexagon::STriw_GP_cdnPt_V4:
774 return Hexagon::STriw_GP_cdnPt_nv_V4;
776 case Hexagon::STriw_GP_cdnNotPt_V4:
777 return Hexagon::STriw_GP_cdnNotPt_nv_V4;
781 // Return .new predicate version for an instruction
782 static int GetDotNewPredOp(const int opc) {
784 default: llvm_unreachable("Unknown .new type");
785 // Conditional stores
786 // Store byte conditionally
787 case Hexagon::STrib_cPt :
788 return Hexagon::STrib_cdnPt_V4;
790 case Hexagon::STrib_cNotPt :
791 return Hexagon::STrib_cdnNotPt_V4;
793 case Hexagon::STrib_indexed_cPt :
794 return Hexagon::STrib_indexed_cdnPt_V4;
796 case Hexagon::STrib_indexed_cNotPt :
797 return Hexagon::STrib_indexed_cdnNotPt_V4;
799 case Hexagon::STrib_imm_cPt_V4 :
800 return Hexagon::STrib_imm_cdnPt_V4;
802 case Hexagon::STrib_imm_cNotPt_V4 :
803 return Hexagon::STrib_imm_cdnNotPt_V4;
805 case Hexagon::POST_STbri_cPt :
806 return Hexagon::POST_STbri_cdnPt_V4;
808 case Hexagon::POST_STbri_cNotPt :
809 return Hexagon::POST_STbri_cdnNotPt_V4;
811 case Hexagon::STrib_indexed_shl_cPt_V4 :
812 return Hexagon::STrib_indexed_shl_cdnPt_V4;
814 case Hexagon::STrib_indexed_shl_cNotPt_V4 :
815 return Hexagon::STrib_indexed_shl_cdnNotPt_V4;
817 case Hexagon::STb_GP_cPt_V4 :
818 return Hexagon::STb_GP_cdnPt_V4;
820 case Hexagon::STb_GP_cNotPt_V4 :
821 return Hexagon::STb_GP_cdnNotPt_V4;
823 case Hexagon::STrib_GP_cPt_V4 :
824 return Hexagon::STrib_GP_cdnPt_V4;
826 case Hexagon::STrib_GP_cNotPt_V4 :
827 return Hexagon::STrib_GP_cdnNotPt_V4;
829 // Store doubleword conditionally
830 case Hexagon::STrid_cPt :
831 return Hexagon::STrid_cdnPt_V4;
833 case Hexagon::STrid_cNotPt :
834 return Hexagon::STrid_cdnNotPt_V4;
836 case Hexagon::STrid_indexed_cPt :
837 return Hexagon::STrid_indexed_cdnPt_V4;
839 case Hexagon::STrid_indexed_cNotPt :
840 return Hexagon::STrid_indexed_cdnNotPt_V4;
842 case Hexagon::STrid_indexed_shl_cPt_V4 :
843 return Hexagon::STrid_indexed_shl_cdnPt_V4;
845 case Hexagon::STrid_indexed_shl_cNotPt_V4 :
846 return Hexagon::STrid_indexed_shl_cdnNotPt_V4;
848 case Hexagon::POST_STdri_cPt :
849 return Hexagon::POST_STdri_cdnPt_V4;
851 case Hexagon::POST_STdri_cNotPt :
852 return Hexagon::POST_STdri_cdnNotPt_V4;
854 case Hexagon::STd_GP_cPt_V4 :
855 return Hexagon::STd_GP_cdnPt_V4;
857 case Hexagon::STd_GP_cNotPt_V4 :
858 return Hexagon::STd_GP_cdnNotPt_V4;
860 case Hexagon::STrid_GP_cPt_V4 :
861 return Hexagon::STrid_GP_cdnPt_V4;
863 case Hexagon::STrid_GP_cNotPt_V4 :
864 return Hexagon::STrid_GP_cdnNotPt_V4;
866 // Store halfword conditionally
867 case Hexagon::STrih_cPt :
868 return Hexagon::STrih_cdnPt_V4;
870 case Hexagon::STrih_cNotPt :
871 return Hexagon::STrih_cdnNotPt_V4;
873 case Hexagon::STrih_indexed_cPt :
874 return Hexagon::STrih_indexed_cdnPt_V4;
876 case Hexagon::STrih_indexed_cNotPt :
877 return Hexagon::STrih_indexed_cdnNotPt_V4;
879 case Hexagon::STrih_imm_cPt_V4 :
880 return Hexagon::STrih_imm_cdnPt_V4;
882 case Hexagon::STrih_imm_cNotPt_V4 :
883 return Hexagon::STrih_imm_cdnNotPt_V4;
885 case Hexagon::STrih_indexed_shl_cPt_V4 :
886 return Hexagon::STrih_indexed_shl_cdnPt_V4;
888 case Hexagon::STrih_indexed_shl_cNotPt_V4 :
889 return Hexagon::STrih_indexed_shl_cdnNotPt_V4;
891 case Hexagon::POST_SThri_cPt :
892 return Hexagon::POST_SThri_cdnPt_V4;
894 case Hexagon::POST_SThri_cNotPt :
895 return Hexagon::POST_SThri_cdnNotPt_V4;
897 case Hexagon::STh_GP_cPt_V4 :
898 return Hexagon::STh_GP_cdnPt_V4;
900 case Hexagon::STh_GP_cNotPt_V4 :
901 return Hexagon::STh_GP_cdnNotPt_V4;
903 case Hexagon::STrih_GP_cPt_V4 :
904 return Hexagon::STrih_GP_cdnPt_V4;
906 case Hexagon::STrih_GP_cNotPt_V4 :
907 return Hexagon::STrih_GP_cdnNotPt_V4;
909 // Store word conditionally
910 case Hexagon::STriw_cPt :
911 return Hexagon::STriw_cdnPt_V4;
913 case Hexagon::STriw_cNotPt :
914 return Hexagon::STriw_cdnNotPt_V4;
916 case Hexagon::STriw_indexed_cPt :
917 return Hexagon::STriw_indexed_cdnPt_V4;
919 case Hexagon::STriw_indexed_cNotPt :
920 return Hexagon::STriw_indexed_cdnNotPt_V4;
922 case Hexagon::STriw_imm_cPt_V4 :
923 return Hexagon::STriw_imm_cdnPt_V4;
925 case Hexagon::STriw_imm_cNotPt_V4 :
926 return Hexagon::STriw_imm_cdnNotPt_V4;
928 case Hexagon::STriw_indexed_shl_cPt_V4 :
929 return Hexagon::STriw_indexed_shl_cdnPt_V4;
931 case Hexagon::STriw_indexed_shl_cNotPt_V4 :
932 return Hexagon::STriw_indexed_shl_cdnNotPt_V4;
934 case Hexagon::POST_STwri_cPt :
935 return Hexagon::POST_STwri_cdnPt_V4;
937 case Hexagon::POST_STwri_cNotPt :
938 return Hexagon::POST_STwri_cdnNotPt_V4;
940 case Hexagon::STw_GP_cPt_V4 :
941 return Hexagon::STw_GP_cdnPt_V4;
943 case Hexagon::STw_GP_cNotPt_V4 :
944 return Hexagon::STw_GP_cdnNotPt_V4;
946 case Hexagon::STriw_GP_cPt_V4 :
947 return Hexagon::STriw_GP_cdnPt_V4;
949 case Hexagon::STriw_GP_cNotPt_V4 :
950 return Hexagon::STriw_GP_cdnNotPt_V4;
954 return Hexagon::JMP_cdnPt;
956 case Hexagon::JMP_cNot:
957 return Hexagon::JMP_cdnNotPt;
959 case Hexagon::JMPR_cPt:
960 return Hexagon::JMPR_cdnPt_V3;
962 case Hexagon::JMPR_cNotPt:
963 return Hexagon::JMPR_cdnNotPt_V3;
965 // Conditional Transfers
966 case Hexagon::TFR_cPt:
967 return Hexagon::TFR_cdnPt;
969 case Hexagon::TFR_cNotPt:
970 return Hexagon::TFR_cdnNotPt;
972 case Hexagon::TFRI_cPt:
973 return Hexagon::TFRI_cdnPt;
975 case Hexagon::TFRI_cNotPt:
976 return Hexagon::TFRI_cdnNotPt;
979 case Hexagon::LDrid_cPt :
980 return Hexagon::LDrid_cdnPt;
982 case Hexagon::LDrid_cNotPt :
983 return Hexagon::LDrid_cdnNotPt;
985 case Hexagon::LDrid_indexed_cPt :
986 return Hexagon::LDrid_indexed_cdnPt;
988 case Hexagon::LDrid_indexed_cNotPt :
989 return Hexagon::LDrid_indexed_cdnNotPt;
991 case Hexagon::POST_LDrid_cPt :
992 return Hexagon::POST_LDrid_cdnPt_V4;
994 case Hexagon::POST_LDrid_cNotPt :
995 return Hexagon::POST_LDrid_cdnNotPt_V4;
998 case Hexagon::LDriw_cPt :
999 return Hexagon::LDriw_cdnPt;
1001 case Hexagon::LDriw_cNotPt :
1002 return Hexagon::LDriw_cdnNotPt;
1004 case Hexagon::LDriw_indexed_cPt :
1005 return Hexagon::LDriw_indexed_cdnPt;
1007 case Hexagon::LDriw_indexed_cNotPt :
1008 return Hexagon::LDriw_indexed_cdnNotPt;
1010 case Hexagon::POST_LDriw_cPt :
1011 return Hexagon::POST_LDriw_cdnPt_V4;
1013 case Hexagon::POST_LDriw_cNotPt :
1014 return Hexagon::POST_LDriw_cdnNotPt_V4;
1017 case Hexagon::LDrih_cPt :
1018 return Hexagon::LDrih_cdnPt;
1020 case Hexagon::LDrih_cNotPt :
1021 return Hexagon::LDrih_cdnNotPt;
1023 case Hexagon::LDrih_indexed_cPt :
1024 return Hexagon::LDrih_indexed_cdnPt;
1026 case Hexagon::LDrih_indexed_cNotPt :
1027 return Hexagon::LDrih_indexed_cdnNotPt;
1029 case Hexagon::POST_LDrih_cPt :
1030 return Hexagon::POST_LDrih_cdnPt_V4;
1032 case Hexagon::POST_LDrih_cNotPt :
1033 return Hexagon::POST_LDrih_cdnNotPt_V4;
1036 case Hexagon::LDrib_cPt :
1037 return Hexagon::LDrib_cdnPt;
1039 case Hexagon::LDrib_cNotPt :
1040 return Hexagon::LDrib_cdnNotPt;
1042 case Hexagon::LDrib_indexed_cPt :
1043 return Hexagon::LDrib_indexed_cdnPt;
1045 case Hexagon::LDrib_indexed_cNotPt :
1046 return Hexagon::LDrib_indexed_cdnNotPt;
1048 case Hexagon::POST_LDrib_cPt :
1049 return Hexagon::POST_LDrib_cdnPt_V4;
1051 case Hexagon::POST_LDrib_cNotPt :
1052 return Hexagon::POST_LDrib_cdnNotPt_V4;
1054 // Load unsigned halfword
1055 case Hexagon::LDriuh_cPt :
1056 return Hexagon::LDriuh_cdnPt;
1058 case Hexagon::LDriuh_cNotPt :
1059 return Hexagon::LDriuh_cdnNotPt;
1061 case Hexagon::LDriuh_indexed_cPt :
1062 return Hexagon::LDriuh_indexed_cdnPt;
1064 case Hexagon::LDriuh_indexed_cNotPt :
1065 return Hexagon::LDriuh_indexed_cdnNotPt;
1067 case Hexagon::POST_LDriuh_cPt :
1068 return Hexagon::POST_LDriuh_cdnPt_V4;
1070 case Hexagon::POST_LDriuh_cNotPt :
1071 return Hexagon::POST_LDriuh_cdnNotPt_V4;
1073 // Load unsigned byte
1074 case Hexagon::LDriub_cPt :
1075 return Hexagon::LDriub_cdnPt;
1077 case Hexagon::LDriub_cNotPt :
1078 return Hexagon::LDriub_cdnNotPt;
1080 case Hexagon::LDriub_indexed_cPt :
1081 return Hexagon::LDriub_indexed_cdnPt;
1083 case Hexagon::LDriub_indexed_cNotPt :
1084 return Hexagon::LDriub_indexed_cdnNotPt;
1086 case Hexagon::POST_LDriub_cPt :
1087 return Hexagon::POST_LDriub_cdnPt_V4;
1089 case Hexagon::POST_LDriub_cNotPt :
1090 return Hexagon::POST_LDriub_cdnNotPt_V4;
1092 // V4 indexed+scaled load
1094 case Hexagon::LDrid_indexed_cPt_V4 :
1095 return Hexagon::LDrid_indexed_cdnPt_V4;
1097 case Hexagon::LDrid_indexed_cNotPt_V4 :
1098 return Hexagon::LDrid_indexed_cdnNotPt_V4;
1100 case Hexagon::LDrid_indexed_shl_cPt_V4 :
1101 return Hexagon::LDrid_indexed_shl_cdnPt_V4;
1103 case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
1104 return Hexagon::LDrid_indexed_shl_cdnNotPt_V4;
1106 case Hexagon::LDrib_indexed_cPt_V4 :
1107 return Hexagon::LDrib_indexed_cdnPt_V4;
1109 case Hexagon::LDrib_indexed_cNotPt_V4 :
1110 return Hexagon::LDrib_indexed_cdnNotPt_V4;
1112 case Hexagon::LDrib_indexed_shl_cPt_V4 :
1113 return Hexagon::LDrib_indexed_shl_cdnPt_V4;
1115 case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
1116 return Hexagon::LDrib_indexed_shl_cdnNotPt_V4;
1118 case Hexagon::LDriub_indexed_cPt_V4 :
1119 return Hexagon::LDriub_indexed_cdnPt_V4;
1121 case Hexagon::LDriub_indexed_cNotPt_V4 :
1122 return Hexagon::LDriub_indexed_cdnNotPt_V4;
1124 case Hexagon::LDriub_indexed_shl_cPt_V4 :
1125 return Hexagon::LDriub_indexed_shl_cdnPt_V4;
1127 case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
1128 return Hexagon::LDriub_indexed_shl_cdnNotPt_V4;
1130 case Hexagon::LDrih_indexed_cPt_V4 :
1131 return Hexagon::LDrih_indexed_cdnPt_V4;
1133 case Hexagon::LDrih_indexed_cNotPt_V4 :
1134 return Hexagon::LDrih_indexed_cdnNotPt_V4;
1136 case Hexagon::LDrih_indexed_shl_cPt_V4 :
1137 return Hexagon::LDrih_indexed_shl_cdnPt_V4;
1139 case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
1140 return Hexagon::LDrih_indexed_shl_cdnNotPt_V4;
1142 case Hexagon::LDriuh_indexed_cPt_V4 :
1143 return Hexagon::LDriuh_indexed_cdnPt_V4;
1145 case Hexagon::LDriuh_indexed_cNotPt_V4 :
1146 return Hexagon::LDriuh_indexed_cdnNotPt_V4;
1148 case Hexagon::LDriuh_indexed_shl_cPt_V4 :
1149 return Hexagon::LDriuh_indexed_shl_cdnPt_V4;
1151 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
1152 return Hexagon::LDriuh_indexed_shl_cdnNotPt_V4;
1154 case Hexagon::LDriw_indexed_cPt_V4 :
1155 return Hexagon::LDriw_indexed_cdnPt_V4;
1157 case Hexagon::LDriw_indexed_cNotPt_V4 :
1158 return Hexagon::LDriw_indexed_cdnNotPt_V4;
1160 case Hexagon::LDriw_indexed_shl_cPt_V4 :
1161 return Hexagon::LDriw_indexed_shl_cdnPt_V4;
1163 case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
1164 return Hexagon::LDriw_indexed_shl_cdnNotPt_V4;
1166 // V4 global address load
1168 case Hexagon::LDd_GP_cPt_V4:
1169 return Hexagon::LDd_GP_cdnPt_V4;
1171 case Hexagon::LDd_GP_cNotPt_V4:
1172 return Hexagon::LDd_GP_cdnNotPt_V4;
1174 case Hexagon::LDb_GP_cPt_V4:
1175 return Hexagon::LDb_GP_cdnPt_V4;
1177 case Hexagon::LDb_GP_cNotPt_V4:
1178 return Hexagon::LDb_GP_cdnNotPt_V4;
1180 case Hexagon::LDub_GP_cPt_V4:
1181 return Hexagon::LDub_GP_cdnPt_V4;
1183 case Hexagon::LDub_GP_cNotPt_V4:
1184 return Hexagon::LDub_GP_cdnNotPt_V4;
1186 case Hexagon::LDh_GP_cPt_V4:
1187 return Hexagon::LDh_GP_cdnPt_V4;
1189 case Hexagon::LDh_GP_cNotPt_V4:
1190 return Hexagon::LDh_GP_cdnNotPt_V4;
1192 case Hexagon::LDuh_GP_cPt_V4:
1193 return Hexagon::LDuh_GP_cdnPt_V4;
1195 case Hexagon::LDuh_GP_cNotPt_V4:
1196 return Hexagon::LDuh_GP_cdnNotPt_V4;
1198 case Hexagon::LDw_GP_cPt_V4:
1199 return Hexagon::LDw_GP_cdnPt_V4;
1201 case Hexagon::LDw_GP_cNotPt_V4:
1202 return Hexagon::LDw_GP_cdnNotPt_V4;
1204 case Hexagon::LDrid_GP_cPt_V4:
1205 return Hexagon::LDrid_GP_cdnPt_V4;
1207 case Hexagon::LDrid_GP_cNotPt_V4:
1208 return Hexagon::LDrid_GP_cdnNotPt_V4;
1210 case Hexagon::LDrib_GP_cPt_V4:
1211 return Hexagon::LDrib_GP_cdnPt_V4;
1213 case Hexagon::LDrib_GP_cNotPt_V4:
1214 return Hexagon::LDrib_GP_cdnNotPt_V4;
1216 case Hexagon::LDriub_GP_cPt_V4:
1217 return Hexagon::LDriub_GP_cdnPt_V4;
1219 case Hexagon::LDriub_GP_cNotPt_V4:
1220 return Hexagon::LDriub_GP_cdnNotPt_V4;
1222 case Hexagon::LDrih_GP_cPt_V4:
1223 return Hexagon::LDrih_GP_cdnPt_V4;
1225 case Hexagon::LDrih_GP_cNotPt_V4:
1226 return Hexagon::LDrih_GP_cdnNotPt_V4;
1228 case Hexagon::LDriuh_GP_cPt_V4:
1229 return Hexagon::LDriuh_GP_cdnPt_V4;
1231 case Hexagon::LDriuh_GP_cNotPt_V4:
1232 return Hexagon::LDriuh_GP_cdnNotPt_V4;
1234 case Hexagon::LDriw_GP_cPt_V4:
1235 return Hexagon::LDriw_GP_cdnPt_V4;
1237 case Hexagon::LDriw_GP_cNotPt_V4:
1238 return Hexagon::LDriw_GP_cdnNotPt_V4;
1240 // Conditional store new-value byte
1241 case Hexagon::STrib_cPt_nv_V4 :
1242 return Hexagon::STrib_cdnPt_nv_V4;
1243 case Hexagon::STrib_cNotPt_nv_V4 :
1244 return Hexagon::STrib_cdnNotPt_nv_V4;
1246 case Hexagon::STrib_indexed_cPt_nv_V4 :
1247 return Hexagon::STrib_indexed_cdnPt_nv_V4;
1248 case Hexagon::STrib_indexed_cNotPt_nv_V4 :
1249 return Hexagon::STrib_indexed_cdnNotPt_nv_V4;
1251 case Hexagon::STrib_indexed_shl_cPt_nv_V4 :
1252 return Hexagon::STrib_indexed_shl_cdnPt_nv_V4;
1253 case Hexagon::STrib_indexed_shl_cNotPt_nv_V4 :
1254 return Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4;
1256 case Hexagon::POST_STbri_cPt_nv_V4 :
1257 return Hexagon::POST_STbri_cdnPt_nv_V4;
1258 case Hexagon::POST_STbri_cNotPt_nv_V4 :
1259 return Hexagon::POST_STbri_cdnNotPt_nv_V4;
1261 case Hexagon::STb_GP_cPt_nv_V4 :
1262 return Hexagon::STb_GP_cdnPt_nv_V4;
1264 case Hexagon::STb_GP_cNotPt_nv_V4 :
1265 return Hexagon::STb_GP_cdnNotPt_nv_V4;
1267 case Hexagon::STrib_GP_cPt_nv_V4 :
1268 return Hexagon::STrib_GP_cdnPt_nv_V4;
1270 case Hexagon::STrib_GP_cNotPt_nv_V4 :
1271 return Hexagon::STrib_GP_cdnNotPt_nv_V4;
1273 // Conditional store new-value halfword
1274 case Hexagon::STrih_cPt_nv_V4 :
1275 return Hexagon::STrih_cdnPt_nv_V4;
1276 case Hexagon::STrih_cNotPt_nv_V4 :
1277 return Hexagon::STrih_cdnNotPt_nv_V4;
1279 case Hexagon::STrih_indexed_cPt_nv_V4 :
1280 return Hexagon::STrih_indexed_cdnPt_nv_V4;
1281 case Hexagon::STrih_indexed_cNotPt_nv_V4 :
1282 return Hexagon::STrih_indexed_cdnNotPt_nv_V4;
1284 case Hexagon::STrih_indexed_shl_cPt_nv_V4 :
1285 return Hexagon::STrih_indexed_shl_cdnPt_nv_V4;
1286 case Hexagon::STrih_indexed_shl_cNotPt_nv_V4 :
1287 return Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4;
1289 case Hexagon::POST_SThri_cPt_nv_V4 :
1290 return Hexagon::POST_SThri_cdnPt_nv_V4;
1291 case Hexagon::POST_SThri_cNotPt_nv_V4 :
1292 return Hexagon::POST_SThri_cdnNotPt_nv_V4;
1294 case Hexagon::STh_GP_cPt_nv_V4 :
1295 return Hexagon::STh_GP_cdnPt_nv_V4;
1297 case Hexagon::STh_GP_cNotPt_nv_V4 :
1298 return Hexagon::STh_GP_cdnNotPt_nv_V4;
1300 case Hexagon::STrih_GP_cPt_nv_V4 :
1301 return Hexagon::STrih_GP_cdnPt_nv_V4;
1303 case Hexagon::STrih_GP_cNotPt_nv_V4 :
1304 return Hexagon::STrih_GP_cdnNotPt_nv_V4;
1306 // Conditional store new-value word
1307 case Hexagon::STriw_cPt_nv_V4 :
1308 return Hexagon::STriw_cdnPt_nv_V4;
1309 case Hexagon::STriw_cNotPt_nv_V4 :
1310 return Hexagon::STriw_cdnNotPt_nv_V4;
1312 case Hexagon::STriw_indexed_cPt_nv_V4 :
1313 return Hexagon::STriw_indexed_cdnPt_nv_V4;
1314 case Hexagon::STriw_indexed_cNotPt_nv_V4 :
1315 return Hexagon::STriw_indexed_cdnNotPt_nv_V4;
1317 case Hexagon::STriw_indexed_shl_cPt_nv_V4 :
1318 return Hexagon::STriw_indexed_shl_cdnPt_nv_V4;
1319 case Hexagon::STriw_indexed_shl_cNotPt_nv_V4 :
1320 return Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4;
1322 case Hexagon::POST_STwri_cPt_nv_V4 :
1323 return Hexagon::POST_STwri_cdnPt_nv_V4;
1324 case Hexagon::POST_STwri_cNotPt_nv_V4:
1325 return Hexagon::POST_STwri_cdnNotPt_nv_V4;
1327 case Hexagon::STw_GP_cPt_nv_V4 :
1328 return Hexagon::STw_GP_cdnPt_nv_V4;
1330 case Hexagon::STw_GP_cNotPt_nv_V4 :
1331 return Hexagon::STw_GP_cdnNotPt_nv_V4;
1333 case Hexagon::STriw_GP_cPt_nv_V4 :
1334 return Hexagon::STriw_GP_cdnPt_nv_V4;
1336 case Hexagon::STriw_GP_cNotPt_nv_V4 :
1337 return Hexagon::STriw_GP_cdnNotPt_nv_V4;
1340 case Hexagon::ADD_ri_cPt :
1341 return Hexagon::ADD_ri_cdnPt;
1342 case Hexagon::ADD_ri_cNotPt :
1343 return Hexagon::ADD_ri_cdnNotPt;
1345 case Hexagon::ADD_rr_cPt :
1346 return Hexagon::ADD_rr_cdnPt;
1347 case Hexagon::ADD_rr_cNotPt :
1348 return Hexagon::ADD_rr_cdnNotPt;
1350 // Conditional logical Operations
1351 case Hexagon::XOR_rr_cPt :
1352 return Hexagon::XOR_rr_cdnPt;
1353 case Hexagon::XOR_rr_cNotPt :
1354 return Hexagon::XOR_rr_cdnNotPt;
1356 case Hexagon::AND_rr_cPt :
1357 return Hexagon::AND_rr_cdnPt;
1358 case Hexagon::AND_rr_cNotPt :
1359 return Hexagon::AND_rr_cdnNotPt;
1361 case Hexagon::OR_rr_cPt :
1362 return Hexagon::OR_rr_cdnPt;
1363 case Hexagon::OR_rr_cNotPt :
1364 return Hexagon::OR_rr_cdnNotPt;
1366 // Conditional Subtract
1367 case Hexagon::SUB_rr_cPt :
1368 return Hexagon::SUB_rr_cdnPt;
1369 case Hexagon::SUB_rr_cNotPt :
1370 return Hexagon::SUB_rr_cdnNotPt;
1372 // Conditional combine
1373 case Hexagon::COMBINE_rr_cPt :
1374 return Hexagon::COMBINE_rr_cdnPt;
1375 case Hexagon::COMBINE_rr_cNotPt :
1376 return Hexagon::COMBINE_rr_cdnNotPt;
1378 case Hexagon::ASLH_cPt_V4 :
1379 return Hexagon::ASLH_cdnPt_V4;
1380 case Hexagon::ASLH_cNotPt_V4 :
1381 return Hexagon::ASLH_cdnNotPt_V4;
1383 case Hexagon::ASRH_cPt_V4 :
1384 return Hexagon::ASRH_cdnPt_V4;
1385 case Hexagon::ASRH_cNotPt_V4 :
1386 return Hexagon::ASRH_cdnNotPt_V4;
1388 case Hexagon::SXTB_cPt_V4 :
1389 return Hexagon::SXTB_cdnPt_V4;
1390 case Hexagon::SXTB_cNotPt_V4 :
1391 return Hexagon::SXTB_cdnNotPt_V4;
1393 case Hexagon::SXTH_cPt_V4 :
1394 return Hexagon::SXTH_cdnPt_V4;
1395 case Hexagon::SXTH_cNotPt_V4 :
1396 return Hexagon::SXTH_cdnNotPt_V4;
1398 case Hexagon::ZXTB_cPt_V4 :
1399 return Hexagon::ZXTB_cdnPt_V4;
1400 case Hexagon::ZXTB_cNotPt_V4 :
1401 return Hexagon::ZXTB_cdnNotPt_V4;
1403 case Hexagon::ZXTH_cPt_V4 :
1404 return Hexagon::ZXTH_cdnPt_V4;
1405 case Hexagon::ZXTH_cNotPt_V4 :
1406 return Hexagon::ZXTH_cdnNotPt_V4;
1410 // Returns true if an instruction can be promoted to .new predicate
1411 // or new-value store.
1412 bool HexagonPacketizerList::isNewifiable(MachineInstr* MI) {
1413 if ( isCondInst(MI) || IsNewifyStore(MI))
1419 bool HexagonPacketizerList::isCondInst (MachineInstr* MI) {
1420 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1421 const MCInstrDesc& TID = MI->getDesc();
1422 // bug 5670: until that is fixed,
1423 // this portion is disabled.
1424 if ( TID.isConditionalBranch() // && !IsRegisterJump(MI)) ||
1425 || QII->isConditionalTransfer(MI)
1426 || QII->isConditionalALU32(MI)
1427 || QII->isConditionalLoad(MI)
1428 || QII->isConditionalStore(MI)) {
1435 // Promote an instructiont to its .new form.
1436 // At this time, we have already made a call to CanPromoteToDotNew
1437 // and made sure that it can *indeed* be promoted.
1438 bool HexagonPacketizerList::PromoteToDotNew(MachineInstr* MI,
1439 SDep::Kind DepType, MachineBasicBlock::iterator &MII,
1440 const TargetRegisterClass* RC) {
1442 assert (DepType == SDep::Data);
1443 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
1446 if (RC == &Hexagon::PredRegsRegClass)
1447 NewOpcode = GetDotNewPredOp(MI->getOpcode());
1449 NewOpcode = GetDotNewOp(MI->getOpcode());
1450 MI->setDesc(QII->get(NewOpcode));
1455 // Returns the most basic instruction for the .new predicated instructions and
1456 // new-value stores.
1457 // For example, all of the following instructions will be converted back to the
1458 // same instruction:
1459 // 1) if (p0.new) memw(R0+#0) = R1.new --->
1460 // 2) if (p0) memw(R0+#0)= R1.new -------> if (p0) memw(R0+#0) = R1
1461 // 3) if (p0.new) memw(R0+#0) = R1 --->
1463 // To understand the translation of instruction 1 to its original form, consider
1464 // a packet with 3 instructions.
1465 // { p0 = cmp.eq(R0,R1)
1466 // if (p0.new) R2 = add(R3, R4)
1467 // R5 = add (R3, R1)
1469 // if (p0) memw(R5+#0) = R2 <--- trying to include it in the previous packet
1471 // This instruction can be part of the previous packet only if both p0 and R2
1472 // are promoted to .new values. This promotion happens in steps, first
1473 // predicate register is promoted to .new and in the next iteration R2 is
1474 // promoted. Therefore, in case of dependence check failure (due to R5) during
1475 // next iteration, it should be converted back to its most basic form.
1477 static int GetDotOldOp(const int opc) {
1479 default: llvm_unreachable("Unknown .old type");
1480 case Hexagon::TFR_cdnPt:
1481 return Hexagon::TFR_cPt;
1483 case Hexagon::TFR_cdnNotPt:
1484 return Hexagon::TFR_cNotPt;
1486 case Hexagon::TFRI_cdnPt:
1487 return Hexagon::TFRI_cPt;
1489 case Hexagon::TFRI_cdnNotPt:
1490 return Hexagon::TFRI_cNotPt;
1492 case Hexagon::JMP_cdnPt:
1493 return Hexagon::JMP_c;
1495 case Hexagon::JMP_cdnNotPt:
1496 return Hexagon::JMP_cNot;
1498 case Hexagon::JMPR_cdnPt_V3:
1499 return Hexagon::JMPR_cPt;
1501 case Hexagon::JMPR_cdnNotPt_V3:
1502 return Hexagon::JMPR_cNotPt;
1506 case Hexagon::LDrid_cdnPt :
1507 return Hexagon::LDrid_cPt;
1509 case Hexagon::LDrid_cdnNotPt :
1510 return Hexagon::LDrid_cNotPt;
1512 case Hexagon::LDrid_indexed_cdnPt :
1513 return Hexagon::LDrid_indexed_cPt;
1515 case Hexagon::LDrid_indexed_cdnNotPt :
1516 return Hexagon::LDrid_indexed_cNotPt;
1518 case Hexagon::POST_LDrid_cdnPt_V4 :
1519 return Hexagon::POST_LDrid_cPt;
1521 case Hexagon::POST_LDrid_cdnNotPt_V4 :
1522 return Hexagon::POST_LDrid_cNotPt;
1526 case Hexagon::LDriw_cdnPt :
1527 return Hexagon::LDriw_cPt;
1529 case Hexagon::LDriw_cdnNotPt :
1530 return Hexagon::LDriw_cNotPt;
1532 case Hexagon::LDriw_indexed_cdnPt :
1533 return Hexagon::LDriw_indexed_cPt;
1535 case Hexagon::LDriw_indexed_cdnNotPt :
1536 return Hexagon::LDriw_indexed_cNotPt;
1538 case Hexagon::POST_LDriw_cdnPt_V4 :
1539 return Hexagon::POST_LDriw_cPt;
1541 case Hexagon::POST_LDriw_cdnNotPt_V4 :
1542 return Hexagon::POST_LDriw_cNotPt;
1546 case Hexagon::LDrih_cdnPt :
1547 return Hexagon::LDrih_cPt;
1549 case Hexagon::LDrih_cdnNotPt :
1550 return Hexagon::LDrih_cNotPt;
1552 case Hexagon::LDrih_indexed_cdnPt :
1553 return Hexagon::LDrih_indexed_cPt;
1555 case Hexagon::LDrih_indexed_cdnNotPt :
1556 return Hexagon::LDrih_indexed_cNotPt;
1558 case Hexagon::POST_LDrih_cdnPt_V4 :
1559 return Hexagon::POST_LDrih_cPt;
1561 case Hexagon::POST_LDrih_cdnNotPt_V4 :
1562 return Hexagon::POST_LDrih_cNotPt;
1566 case Hexagon::LDrib_cdnPt :
1567 return Hexagon::LDrib_cPt;
1569 case Hexagon::LDrib_cdnNotPt :
1570 return Hexagon::LDrib_cNotPt;
1572 case Hexagon::LDrib_indexed_cdnPt :
1573 return Hexagon::LDrib_indexed_cPt;
1575 case Hexagon::LDrib_indexed_cdnNotPt :
1576 return Hexagon::LDrib_indexed_cNotPt;
1578 case Hexagon::POST_LDrib_cdnPt_V4 :
1579 return Hexagon::POST_LDrib_cPt;
1581 case Hexagon::POST_LDrib_cdnNotPt_V4 :
1582 return Hexagon::POST_LDrib_cNotPt;
1584 // Load unsigned half
1586 case Hexagon::LDriuh_cdnPt :
1587 return Hexagon::LDriuh_cPt;
1589 case Hexagon::LDriuh_cdnNotPt :
1590 return Hexagon::LDriuh_cNotPt;
1592 case Hexagon::LDriuh_indexed_cdnPt :
1593 return Hexagon::LDriuh_indexed_cPt;
1595 case Hexagon::LDriuh_indexed_cdnNotPt :
1596 return Hexagon::LDriuh_indexed_cNotPt;
1598 case Hexagon::POST_LDriuh_cdnPt_V4 :
1599 return Hexagon::POST_LDriuh_cPt;
1601 case Hexagon::POST_LDriuh_cdnNotPt_V4 :
1602 return Hexagon::POST_LDriuh_cNotPt;
1604 // Load unsigned byte
1605 case Hexagon::LDriub_cdnPt :
1606 return Hexagon::LDriub_cPt;
1608 case Hexagon::LDriub_cdnNotPt :
1609 return Hexagon::LDriub_cNotPt;
1611 case Hexagon::LDriub_indexed_cdnPt :
1612 return Hexagon::LDriub_indexed_cPt;
1614 case Hexagon::LDriub_indexed_cdnNotPt :
1615 return Hexagon::LDriub_indexed_cNotPt;
1617 case Hexagon::POST_LDriub_cdnPt_V4 :
1618 return Hexagon::POST_LDriub_cPt;
1620 case Hexagon::POST_LDriub_cdnNotPt_V4 :
1621 return Hexagon::POST_LDriub_cNotPt;
1623 // V4 indexed+scaled Load
1625 case Hexagon::LDrid_indexed_cdnPt_V4 :
1626 return Hexagon::LDrid_indexed_cPt_V4;
1628 case Hexagon::LDrid_indexed_cdnNotPt_V4 :
1629 return Hexagon::LDrid_indexed_cNotPt_V4;
1631 case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
1632 return Hexagon::LDrid_indexed_shl_cPt_V4;
1634 case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
1635 return Hexagon::LDrid_indexed_shl_cNotPt_V4;
1637 case Hexagon::LDrib_indexed_cdnPt_V4 :
1638 return Hexagon::LDrib_indexed_cPt_V4;
1640 case Hexagon::LDrib_indexed_cdnNotPt_V4 :
1641 return Hexagon::LDrib_indexed_cNotPt_V4;
1643 case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
1644 return Hexagon::LDrib_indexed_shl_cPt_V4;
1646 case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
1647 return Hexagon::LDrib_indexed_shl_cNotPt_V4;
1649 case Hexagon::LDriub_indexed_cdnPt_V4 :
1650 return Hexagon::LDriub_indexed_cPt_V4;
1652 case Hexagon::LDriub_indexed_cdnNotPt_V4 :
1653 return Hexagon::LDriub_indexed_cNotPt_V4;
1655 case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
1656 return Hexagon::LDriub_indexed_shl_cPt_V4;
1658 case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
1659 return Hexagon::LDriub_indexed_shl_cNotPt_V4;
1661 case Hexagon::LDrih_indexed_cdnPt_V4 :
1662 return Hexagon::LDrih_indexed_cPt_V4;
1664 case Hexagon::LDrih_indexed_cdnNotPt_V4 :
1665 return Hexagon::LDrih_indexed_cNotPt_V4;
1667 case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
1668 return Hexagon::LDrih_indexed_shl_cPt_V4;
1670 case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
1671 return Hexagon::LDrih_indexed_shl_cNotPt_V4;
1673 case Hexagon::LDriuh_indexed_cdnPt_V4 :
1674 return Hexagon::LDriuh_indexed_cPt_V4;
1676 case Hexagon::LDriuh_indexed_cdnNotPt_V4 :
1677 return Hexagon::LDriuh_indexed_cNotPt_V4;
1679 case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
1680 return Hexagon::LDriuh_indexed_shl_cPt_V4;
1682 case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
1683 return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1685 case Hexagon::LDriw_indexed_cdnPt_V4 :
1686 return Hexagon::LDriw_indexed_cPt_V4;
1688 case Hexagon::LDriw_indexed_cdnNotPt_V4 :
1689 return Hexagon::LDriw_indexed_cNotPt_V4;
1691 case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
1692 return Hexagon::LDriw_indexed_shl_cPt_V4;
1694 case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
1695 return Hexagon::LDriw_indexed_shl_cNotPt_V4;
1697 // V4 global address load
1699 case Hexagon::LDd_GP_cdnPt_V4:
1700 return Hexagon::LDd_GP_cPt_V4;
1702 case Hexagon::LDd_GP_cdnNotPt_V4:
1703 return Hexagon::LDd_GP_cNotPt_V4;
1705 case Hexagon::LDb_GP_cdnPt_V4:
1706 return Hexagon::LDb_GP_cPt_V4;
1708 case Hexagon::LDb_GP_cdnNotPt_V4:
1709 return Hexagon::LDb_GP_cNotPt_V4;
1711 case Hexagon::LDub_GP_cdnPt_V4:
1712 return Hexagon::LDub_GP_cPt_V4;
1714 case Hexagon::LDub_GP_cdnNotPt_V4:
1715 return Hexagon::LDub_GP_cNotPt_V4;
1717 case Hexagon::LDh_GP_cdnPt_V4:
1718 return Hexagon::LDh_GP_cPt_V4;
1720 case Hexagon::LDh_GP_cdnNotPt_V4:
1721 return Hexagon::LDh_GP_cNotPt_V4;
1723 case Hexagon::LDuh_GP_cdnPt_V4:
1724 return Hexagon::LDuh_GP_cPt_V4;
1726 case Hexagon::LDuh_GP_cdnNotPt_V4:
1727 return Hexagon::LDuh_GP_cNotPt_V4;
1729 case Hexagon::LDw_GP_cdnPt_V4:
1730 return Hexagon::LDw_GP_cPt_V4;
1732 case Hexagon::LDw_GP_cdnNotPt_V4:
1733 return Hexagon::LDw_GP_cNotPt_V4;
1735 case Hexagon::LDrid_GP_cdnPt_V4:
1736 return Hexagon::LDrid_GP_cPt_V4;
1738 case Hexagon::LDrid_GP_cdnNotPt_V4:
1739 return Hexagon::LDrid_GP_cNotPt_V4;
1741 case Hexagon::LDrib_GP_cdnPt_V4:
1742 return Hexagon::LDrib_GP_cPt_V4;
1744 case Hexagon::LDrib_GP_cdnNotPt_V4:
1745 return Hexagon::LDrib_GP_cNotPt_V4;
1747 case Hexagon::LDriub_GP_cdnPt_V4:
1748 return Hexagon::LDriub_GP_cPt_V4;
1750 case Hexagon::LDriub_GP_cdnNotPt_V4:
1751 return Hexagon::LDriub_GP_cNotPt_V4;
1753 case Hexagon::LDrih_GP_cdnPt_V4:
1754 return Hexagon::LDrih_GP_cPt_V4;
1756 case Hexagon::LDrih_GP_cdnNotPt_V4:
1757 return Hexagon::LDrih_GP_cNotPt_V4;
1759 case Hexagon::LDriuh_GP_cdnPt_V4:
1760 return Hexagon::LDriuh_GP_cPt_V4;
1762 case Hexagon::LDriuh_GP_cdnNotPt_V4:
1763 return Hexagon::LDriuh_GP_cNotPt_V4;
1765 case Hexagon::LDriw_GP_cdnPt_V4:
1766 return Hexagon::LDriw_GP_cPt_V4;
1768 case Hexagon::LDriw_GP_cdnNotPt_V4:
1769 return Hexagon::LDriw_GP_cNotPt_V4;
1773 case Hexagon::ADD_ri_cdnPt :
1774 return Hexagon::ADD_ri_cPt;
1775 case Hexagon::ADD_ri_cdnNotPt :
1776 return Hexagon::ADD_ri_cNotPt;
1778 case Hexagon::ADD_rr_cdnPt :
1779 return Hexagon::ADD_rr_cPt;
1780 case Hexagon::ADD_rr_cdnNotPt:
1781 return Hexagon::ADD_rr_cNotPt;
1783 // Conditional logical Operations
1785 case Hexagon::XOR_rr_cdnPt :
1786 return Hexagon::XOR_rr_cPt;
1787 case Hexagon::XOR_rr_cdnNotPt :
1788 return Hexagon::XOR_rr_cNotPt;
1790 case Hexagon::AND_rr_cdnPt :
1791 return Hexagon::AND_rr_cPt;
1792 case Hexagon::AND_rr_cdnNotPt :
1793 return Hexagon::AND_rr_cNotPt;
1795 case Hexagon::OR_rr_cdnPt :
1796 return Hexagon::OR_rr_cPt;
1797 case Hexagon::OR_rr_cdnNotPt :
1798 return Hexagon::OR_rr_cNotPt;
1800 // Conditional Subtract
1802 case Hexagon::SUB_rr_cdnPt :
1803 return Hexagon::SUB_rr_cPt;
1804 case Hexagon::SUB_rr_cdnNotPt :
1805 return Hexagon::SUB_rr_cNotPt;
1807 // Conditional combine
1809 case Hexagon::COMBINE_rr_cdnPt :
1810 return Hexagon::COMBINE_rr_cPt;
1811 case Hexagon::COMBINE_rr_cdnNotPt :
1812 return Hexagon::COMBINE_rr_cNotPt;
1814 // Conditional shift operations
1816 case Hexagon::ASLH_cdnPt_V4 :
1817 return Hexagon::ASLH_cPt_V4;
1818 case Hexagon::ASLH_cdnNotPt_V4 :
1819 return Hexagon::ASLH_cNotPt_V4;
1821 case Hexagon::ASRH_cdnPt_V4 :
1822 return Hexagon::ASRH_cPt_V4;
1823 case Hexagon::ASRH_cdnNotPt_V4 :
1824 return Hexagon::ASRH_cNotPt_V4;
1826 case Hexagon::SXTB_cdnPt_V4 :
1827 return Hexagon::SXTB_cPt_V4;
1828 case Hexagon::SXTB_cdnNotPt_V4 :
1829 return Hexagon::SXTB_cNotPt_V4;
1831 case Hexagon::SXTH_cdnPt_V4 :
1832 return Hexagon::SXTH_cPt_V4;
1833 case Hexagon::SXTH_cdnNotPt_V4 :
1834 return Hexagon::SXTH_cNotPt_V4;
1836 case Hexagon::ZXTB_cdnPt_V4 :
1837 return Hexagon::ZXTB_cPt_V4;
1838 case Hexagon::ZXTB_cdnNotPt_V4 :
1839 return Hexagon::ZXTB_cNotPt_V4;
1841 case Hexagon::ZXTH_cdnPt_V4 :
1842 return Hexagon::ZXTH_cPt_V4;
1843 case Hexagon::ZXTH_cdnNotPt_V4 :
1844 return Hexagon::ZXTH_cNotPt_V4;
1848 case Hexagon::STrib_imm_cdnPt_V4 :
1849 return Hexagon::STrib_imm_cPt_V4;
1851 case Hexagon::STrib_imm_cdnNotPt_V4 :
1852 return Hexagon::STrib_imm_cNotPt_V4;
1854 case Hexagon::STrib_cdnPt_nv_V4 :
1855 case Hexagon::STrib_cPt_nv_V4 :
1856 case Hexagon::STrib_cdnPt_V4 :
1857 return Hexagon::STrib_cPt;
1859 case Hexagon::STrib_cdnNotPt_nv_V4 :
1860 case Hexagon::STrib_cNotPt_nv_V4 :
1861 case Hexagon::STrib_cdnNotPt_V4 :
1862 return Hexagon::STrib_cNotPt;
1864 case Hexagon::STrib_indexed_cdnPt_V4 :
1865 case Hexagon::STrib_indexed_cPt_nv_V4 :
1866 case Hexagon::STrib_indexed_cdnPt_nv_V4 :
1867 return Hexagon::STrib_indexed_cPt;
1869 case Hexagon::STrib_indexed_cdnNotPt_V4 :
1870 case Hexagon::STrib_indexed_cNotPt_nv_V4 :
1871 case Hexagon::STrib_indexed_cdnNotPt_nv_V4 :
1872 return Hexagon::STrib_indexed_cNotPt;
1874 case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:
1875 case Hexagon::STrib_indexed_shl_cPt_nv_V4 :
1876 case Hexagon::STrib_indexed_shl_cdnPt_V4 :
1877 return Hexagon::STrib_indexed_shl_cPt_V4;
1879 case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:
1880 case Hexagon::STrib_indexed_shl_cNotPt_nv_V4 :
1881 case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
1882 return Hexagon::STrib_indexed_shl_cNotPt_V4;
1884 case Hexagon::POST_STbri_cdnPt_nv_V4 :
1885 case Hexagon::POST_STbri_cPt_nv_V4 :
1886 case Hexagon::POST_STbri_cdnPt_V4 :
1887 return Hexagon::POST_STbri_cPt;
1889 case Hexagon::POST_STbri_cdnNotPt_nv_V4 :
1890 case Hexagon::POST_STbri_cNotPt_nv_V4:
1891 case Hexagon::POST_STbri_cdnNotPt_V4 :
1892 return Hexagon::POST_STbri_cNotPt;
1894 case Hexagon::STb_GP_cdnPt_nv_V4:
1895 case Hexagon::STb_GP_cdnPt_V4:
1896 case Hexagon::STb_GP_cPt_nv_V4:
1897 return Hexagon::STb_GP_cPt_V4;
1899 case Hexagon::STb_GP_cdnNotPt_nv_V4:
1900 case Hexagon::STb_GP_cdnNotPt_V4:
1901 case Hexagon::STb_GP_cNotPt_nv_V4:
1902 return Hexagon::STb_GP_cNotPt_V4;
1904 case Hexagon::STrib_GP_cdnPt_nv_V4:
1905 case Hexagon::STrib_GP_cdnPt_V4:
1906 case Hexagon::STrib_GP_cPt_nv_V4:
1907 return Hexagon::STrib_GP_cPt_V4;
1909 case Hexagon::STrib_GP_cdnNotPt_nv_V4:
1910 case Hexagon::STrib_GP_cdnNotPt_V4:
1911 case Hexagon::STrib_GP_cNotPt_nv_V4:
1912 return Hexagon::STrib_GP_cNotPt_V4;
1914 // Store new-value byte - unconditional
1915 case Hexagon::STrib_nv_V4:
1916 return Hexagon::STrib;
1918 case Hexagon::STrib_indexed_nv_V4:
1919 return Hexagon::STrib_indexed;
1921 case Hexagon::STrib_indexed_shl_nv_V4:
1922 return Hexagon::STrib_indexed_shl_V4;
1924 case Hexagon::STrib_shl_nv_V4:
1925 return Hexagon::STrib_shl_V4;
1927 case Hexagon::STrib_GP_nv_V4:
1928 return Hexagon::STrib_GP_V4;
1930 case Hexagon::STb_GP_nv_V4:
1931 return Hexagon::STb_GP_V4;
1933 case Hexagon::POST_STbri_nv_V4:
1934 return Hexagon::POST_STbri;
1937 case Hexagon::STrih_imm_cdnPt_V4 :
1938 return Hexagon::STrih_imm_cPt_V4;
1940 case Hexagon::STrih_imm_cdnNotPt_V4 :
1941 return Hexagon::STrih_imm_cNotPt_V4;
1943 case Hexagon::STrih_cdnPt_nv_V4 :
1944 case Hexagon::STrih_cPt_nv_V4 :
1945 case Hexagon::STrih_cdnPt_V4 :
1946 return Hexagon::STrih_cPt;
1948 case Hexagon::STrih_cdnNotPt_nv_V4 :
1949 case Hexagon::STrih_cNotPt_nv_V4 :
1950 case Hexagon::STrih_cdnNotPt_V4 :
1951 return Hexagon::STrih_cNotPt;
1953 case Hexagon::STrih_indexed_cdnPt_nv_V4:
1954 case Hexagon::STrih_indexed_cPt_nv_V4 :
1955 case Hexagon::STrih_indexed_cdnPt_V4 :
1956 return Hexagon::STrih_indexed_cPt;
1958 case Hexagon::STrih_indexed_cdnNotPt_nv_V4:
1959 case Hexagon::STrih_indexed_cNotPt_nv_V4 :
1960 case Hexagon::STrih_indexed_cdnNotPt_V4 :
1961 return Hexagon::STrih_indexed_cNotPt;
1963 case Hexagon::STrih_indexed_shl_cdnPt_nv_V4 :
1964 case Hexagon::STrih_indexed_shl_cPt_nv_V4 :
1965 case Hexagon::STrih_indexed_shl_cdnPt_V4 :
1966 return Hexagon::STrih_indexed_shl_cPt_V4;
1968 case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4 :
1969 case Hexagon::STrih_indexed_shl_cNotPt_nv_V4 :
1970 case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
1971 return Hexagon::STrih_indexed_shl_cNotPt_V4;
1973 case Hexagon::POST_SThri_cdnPt_nv_V4 :
1974 case Hexagon::POST_SThri_cPt_nv_V4 :
1975 case Hexagon::POST_SThri_cdnPt_V4 :
1976 return Hexagon::POST_SThri_cPt;
1978 case Hexagon::POST_SThri_cdnNotPt_nv_V4 :
1979 case Hexagon::POST_SThri_cNotPt_nv_V4 :
1980 case Hexagon::POST_SThri_cdnNotPt_V4 :
1981 return Hexagon::POST_SThri_cNotPt;
1983 case Hexagon::STh_GP_cdnPt_nv_V4:
1984 case Hexagon::STh_GP_cdnPt_V4:
1985 case Hexagon::STh_GP_cPt_nv_V4:
1986 return Hexagon::STh_GP_cPt_V4;
1988 case Hexagon::STh_GP_cdnNotPt_nv_V4:
1989 case Hexagon::STh_GP_cdnNotPt_V4:
1990 case Hexagon::STh_GP_cNotPt_nv_V4:
1991 return Hexagon::STh_GP_cNotPt_V4;
1993 case Hexagon::STrih_GP_cdnPt_nv_V4:
1994 case Hexagon::STrih_GP_cdnPt_V4:
1995 case Hexagon::STrih_GP_cPt_nv_V4:
1996 return Hexagon::STrih_GP_cPt_V4;
1998 case Hexagon::STrih_GP_cdnNotPt_nv_V4:
1999 case Hexagon::STrih_GP_cdnNotPt_V4:
2000 case Hexagon::STrih_GP_cNotPt_nv_V4:
2001 return Hexagon::STrih_GP_cNotPt_V4;
2003 // Store new-value halfword - unconditional
2005 case Hexagon::STrih_nv_V4:
2006 return Hexagon::STrih;
2008 case Hexagon::STrih_indexed_nv_V4:
2009 return Hexagon::STrih_indexed;
2011 case Hexagon::STrih_indexed_shl_nv_V4:
2012 return Hexagon::STrih_indexed_shl_V4;
2014 case Hexagon::STrih_shl_nv_V4:
2015 return Hexagon::STrih_shl_V4;
2017 case Hexagon::STrih_GP_nv_V4:
2018 return Hexagon::STrih_GP_V4;
2020 case Hexagon::STh_GP_nv_V4:
2021 return Hexagon::STh_GP_V4;
2023 case Hexagon::POST_SThri_nv_V4:
2024 return Hexagon::POST_SThri;
2028 case Hexagon::STriw_imm_cdnPt_V4 :
2029 return Hexagon::STriw_imm_cPt_V4;
2031 case Hexagon::STriw_imm_cdnNotPt_V4 :
2032 return Hexagon::STriw_imm_cNotPt_V4;
2034 case Hexagon::STriw_cdnPt_nv_V4 :
2035 case Hexagon::STriw_cPt_nv_V4 :
2036 case Hexagon::STriw_cdnPt_V4 :
2037 return Hexagon::STriw_cPt;
2039 case Hexagon::STriw_cdnNotPt_nv_V4 :
2040 case Hexagon::STriw_cNotPt_nv_V4 :
2041 case Hexagon::STriw_cdnNotPt_V4 :
2042 return Hexagon::STriw_cNotPt;
2044 case Hexagon::STriw_indexed_cdnPt_nv_V4 :
2045 case Hexagon::STriw_indexed_cPt_nv_V4 :
2046 case Hexagon::STriw_indexed_cdnPt_V4 :
2047 return Hexagon::STriw_indexed_cPt;
2049 case Hexagon::STriw_indexed_cdnNotPt_nv_V4 :
2050 case Hexagon::STriw_indexed_cNotPt_nv_V4 :
2051 case Hexagon::STriw_indexed_cdnNotPt_V4 :
2052 return Hexagon::STriw_indexed_cNotPt;
2054 case Hexagon::STriw_indexed_shl_cdnPt_nv_V4 :
2055 case Hexagon::STriw_indexed_shl_cPt_nv_V4 :
2056 case Hexagon::STriw_indexed_shl_cdnPt_V4 :
2057 return Hexagon::STriw_indexed_shl_cPt_V4;
2059 case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4 :
2060 case Hexagon::STriw_indexed_shl_cNotPt_nv_V4 :
2061 case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
2062 return Hexagon::STriw_indexed_shl_cNotPt_V4;
2064 case Hexagon::POST_STwri_cdnPt_nv_V4 :
2065 case Hexagon::POST_STwri_cPt_nv_V4 :
2066 case Hexagon::POST_STwri_cdnPt_V4 :
2067 return Hexagon::POST_STwri_cPt;
2069 case Hexagon::POST_STwri_cdnNotPt_nv_V4 :
2070 case Hexagon::POST_STwri_cNotPt_nv_V4 :
2071 case Hexagon::POST_STwri_cdnNotPt_V4 :
2072 return Hexagon::POST_STwri_cNotPt;
2074 case Hexagon::STw_GP_cdnPt_nv_V4:
2075 case Hexagon::STw_GP_cdnPt_V4:
2076 case Hexagon::STw_GP_cPt_nv_V4:
2077 return Hexagon::STw_GP_cPt_V4;
2079 case Hexagon::STw_GP_cdnNotPt_nv_V4:
2080 case Hexagon::STw_GP_cdnNotPt_V4:
2081 case Hexagon::STw_GP_cNotPt_nv_V4:
2082 return Hexagon::STw_GP_cNotPt_V4;
2084 case Hexagon::STriw_GP_cdnPt_nv_V4:
2085 case Hexagon::STriw_GP_cdnPt_V4:
2086 case Hexagon::STriw_GP_cPt_nv_V4:
2087 return Hexagon::STriw_GP_cPt_V4;
2089 case Hexagon::STriw_GP_cdnNotPt_nv_V4:
2090 case Hexagon::STriw_GP_cdnNotPt_V4:
2091 case Hexagon::STriw_GP_cNotPt_nv_V4:
2092 return Hexagon::STriw_GP_cNotPt_V4;
2094 // Store new-value word - unconditional
2096 case Hexagon::STriw_nv_V4:
2097 return Hexagon::STriw;
2099 case Hexagon::STriw_indexed_nv_V4:
2100 return Hexagon::STriw_indexed;
2102 case Hexagon::STriw_indexed_shl_nv_V4:
2103 return Hexagon::STriw_indexed_shl_V4;
2105 case Hexagon::STriw_shl_nv_V4:
2106 return Hexagon::STriw_shl_V4;
2108 case Hexagon::STriw_GP_nv_V4:
2109 return Hexagon::STriw_GP_V4;
2111 case Hexagon::STw_GP_nv_V4:
2112 return Hexagon::STw_GP_V4;
2114 case Hexagon::POST_STwri_nv_V4:
2115 return Hexagon::POST_STwri;
2119 case Hexagon::STrid_cdnPt_V4 :
2120 return Hexagon::STrid_cPt;
2122 case Hexagon::STrid_cdnNotPt_V4 :
2123 return Hexagon::STrid_cNotPt;
2125 case Hexagon::STrid_indexed_cdnPt_V4 :
2126 return Hexagon::STrid_indexed_cPt;
2128 case Hexagon::STrid_indexed_cdnNotPt_V4 :
2129 return Hexagon::STrid_indexed_cNotPt;
2131 case Hexagon::STrid_indexed_shl_cdnPt_V4 :
2132 return Hexagon::STrid_indexed_shl_cPt_V4;
2134 case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
2135 return Hexagon::STrid_indexed_shl_cNotPt_V4;
2137 case Hexagon::POST_STdri_cdnPt_V4 :
2138 return Hexagon::POST_STdri_cPt;
2140 case Hexagon::POST_STdri_cdnNotPt_V4 :
2141 return Hexagon::POST_STdri_cNotPt;
2143 case Hexagon::STd_GP_cdnPt_V4 :
2144 return Hexagon::STd_GP_cPt_V4;
2146 case Hexagon::STd_GP_cdnNotPt_V4 :
2147 return Hexagon::STd_GP_cNotPt_V4;
2149 case Hexagon::STrid_GP_cdnPt_V4 :
2150 return Hexagon::STrid_GP_cPt_V4;
2152 case Hexagon::STrid_GP_cdnNotPt_V4 :
2153 return Hexagon::STrid_GP_cNotPt_V4;
2157 bool HexagonPacketizerList::DemoteToDotOld(MachineInstr* MI) {
2158 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2159 int NewOpcode = GetDotOldOp(MI->getOpcode());
2160 MI->setDesc(QII->get(NewOpcode));
2164 // Returns true if an instruction is predicated on p0 and false if it's
2165 // predicated on !p0.
2167 static bool GetPredicateSense(MachineInstr* MI,
2168 const HexagonInstrInfo *QII) {
2170 switch (MI->getOpcode()) {
2171 default: llvm_unreachable("Unknown predicate sense of the instruction");
2172 case Hexagon::TFR_cPt:
2173 case Hexagon::TFR_cdnPt:
2174 case Hexagon::TFRI_cPt:
2175 case Hexagon::TFRI_cdnPt:
2176 case Hexagon::STrib_cPt :
2177 case Hexagon::STrib_cdnPt_V4 :
2178 case Hexagon::STrib_indexed_cPt :
2179 case Hexagon::STrib_indexed_cdnPt_V4 :
2180 case Hexagon::STrib_indexed_shl_cPt_V4 :
2181 case Hexagon::STrib_indexed_shl_cdnPt_V4 :
2182 case Hexagon::POST_STbri_cPt :
2183 case Hexagon::POST_STbri_cdnPt_V4 :
2184 case Hexagon::STrih_cPt :
2185 case Hexagon::STrih_cdnPt_V4 :
2186 case Hexagon::STrih_indexed_cPt :
2187 case Hexagon::STrih_indexed_cdnPt_V4 :
2188 case Hexagon::STrih_indexed_shl_cPt_V4 :
2189 case Hexagon::STrih_indexed_shl_cdnPt_V4 :
2190 case Hexagon::POST_SThri_cPt :
2191 case Hexagon::POST_SThri_cdnPt_V4 :
2192 case Hexagon::STriw_cPt :
2193 case Hexagon::STriw_cdnPt_V4 :
2194 case Hexagon::STriw_indexed_cPt :
2195 case Hexagon::STriw_indexed_cdnPt_V4 :
2196 case Hexagon::STriw_indexed_shl_cPt_V4 :
2197 case Hexagon::STriw_indexed_shl_cdnPt_V4 :
2198 case Hexagon::POST_STwri_cPt :
2199 case Hexagon::POST_STwri_cdnPt_V4 :
2200 case Hexagon::STrib_imm_cPt_V4 :
2201 case Hexagon::STrib_imm_cdnPt_V4 :
2202 case Hexagon::STrid_cPt :
2203 case Hexagon::STrid_cdnPt_V4 :
2204 case Hexagon::STrid_indexed_cPt :
2205 case Hexagon::STrid_indexed_cdnPt_V4 :
2206 case Hexagon::STrid_indexed_shl_cPt_V4 :
2207 case Hexagon::STrid_indexed_shl_cdnPt_V4 :
2208 case Hexagon::POST_STdri_cPt :
2209 case Hexagon::POST_STdri_cdnPt_V4 :
2210 case Hexagon::STrih_imm_cPt_V4 :
2211 case Hexagon::STrih_imm_cdnPt_V4 :
2212 case Hexagon::STriw_imm_cPt_V4 :
2213 case Hexagon::STriw_imm_cdnPt_V4 :
2214 case Hexagon::JMP_cdnPt :
2215 case Hexagon::LDrid_cPt :
2216 case Hexagon::LDrid_cdnPt :
2217 case Hexagon::LDrid_indexed_cPt :
2218 case Hexagon::LDrid_indexed_cdnPt :
2219 case Hexagon::POST_LDrid_cPt :
2220 case Hexagon::POST_LDrid_cdnPt_V4 :
2221 case Hexagon::LDriw_cPt :
2222 case Hexagon::LDriw_cdnPt :
2223 case Hexagon::LDriw_indexed_cPt :
2224 case Hexagon::LDriw_indexed_cdnPt :
2225 case Hexagon::POST_LDriw_cPt :
2226 case Hexagon::POST_LDriw_cdnPt_V4 :
2227 case Hexagon::LDrih_cPt :
2228 case Hexagon::LDrih_cdnPt :
2229 case Hexagon::LDrih_indexed_cPt :
2230 case Hexagon::LDrih_indexed_cdnPt :
2231 case Hexagon::POST_LDrih_cPt :
2232 case Hexagon::POST_LDrih_cdnPt_V4 :
2233 case Hexagon::LDrib_cPt :
2234 case Hexagon::LDrib_cdnPt :
2235 case Hexagon::LDrib_indexed_cPt :
2236 case Hexagon::LDrib_indexed_cdnPt :
2237 case Hexagon::POST_LDrib_cPt :
2238 case Hexagon::POST_LDrib_cdnPt_V4 :
2239 case Hexagon::LDriuh_cPt :
2240 case Hexagon::LDriuh_cdnPt :
2241 case Hexagon::LDriuh_indexed_cPt :
2242 case Hexagon::LDriuh_indexed_cdnPt :
2243 case Hexagon::POST_LDriuh_cPt :
2244 case Hexagon::POST_LDriuh_cdnPt_V4 :
2245 case Hexagon::LDriub_cPt :
2246 case Hexagon::LDriub_cdnPt :
2247 case Hexagon::LDriub_indexed_cPt :
2248 case Hexagon::LDriub_indexed_cdnPt :
2249 case Hexagon::POST_LDriub_cPt :
2250 case Hexagon::POST_LDriub_cdnPt_V4 :
2251 case Hexagon::LDrid_indexed_cPt_V4 :
2252 case Hexagon::LDrid_indexed_cdnPt_V4 :
2253 case Hexagon::LDrid_indexed_shl_cPt_V4 :
2254 case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
2255 case Hexagon::LDrib_indexed_cPt_V4 :
2256 case Hexagon::LDrib_indexed_cdnPt_V4 :
2257 case Hexagon::LDrib_indexed_shl_cPt_V4 :
2258 case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
2259 case Hexagon::LDriub_indexed_cPt_V4 :
2260 case Hexagon::LDriub_indexed_cdnPt_V4 :
2261 case Hexagon::LDriub_indexed_shl_cPt_V4 :
2262 case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
2263 case Hexagon::LDrih_indexed_cPt_V4 :
2264 case Hexagon::LDrih_indexed_cdnPt_V4 :
2265 case Hexagon::LDrih_indexed_shl_cPt_V4 :
2266 case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
2267 case Hexagon::LDriuh_indexed_cPt_V4 :
2268 case Hexagon::LDriuh_indexed_cdnPt_V4 :
2269 case Hexagon::LDriuh_indexed_shl_cPt_V4 :
2270 case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
2271 case Hexagon::LDriw_indexed_cPt_V4 :
2272 case Hexagon::LDriw_indexed_cdnPt_V4 :
2273 case Hexagon::LDriw_indexed_shl_cPt_V4 :
2274 case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
2275 case Hexagon::ADD_ri_cPt :
2276 case Hexagon::ADD_ri_cdnPt :
2277 case Hexagon::ADD_rr_cPt :
2278 case Hexagon::ADD_rr_cdnPt :
2279 case Hexagon::XOR_rr_cPt :
2280 case Hexagon::XOR_rr_cdnPt :
2281 case Hexagon::AND_rr_cPt :
2282 case Hexagon::AND_rr_cdnPt :
2283 case Hexagon::OR_rr_cPt :
2284 case Hexagon::OR_rr_cdnPt :
2285 case Hexagon::SUB_rr_cPt :
2286 case Hexagon::SUB_rr_cdnPt :
2287 case Hexagon::COMBINE_rr_cPt :
2288 case Hexagon::COMBINE_rr_cdnPt :
2289 case Hexagon::ASLH_cPt_V4 :
2290 case Hexagon::ASLH_cdnPt_V4 :
2291 case Hexagon::ASRH_cPt_V4 :
2292 case Hexagon::ASRH_cdnPt_V4 :
2293 case Hexagon::SXTB_cPt_V4 :
2294 case Hexagon::SXTB_cdnPt_V4 :
2295 case Hexagon::SXTH_cPt_V4 :
2296 case Hexagon::SXTH_cdnPt_V4 :
2297 case Hexagon::ZXTB_cPt_V4 :
2298 case Hexagon::ZXTB_cdnPt_V4 :
2299 case Hexagon::ZXTH_cPt_V4 :
2300 case Hexagon::ZXTH_cdnPt_V4 :
2301 case Hexagon::LDrid_GP_cPt_V4 :
2302 case Hexagon::LDrib_GP_cPt_V4 :
2303 case Hexagon::LDriub_GP_cPt_V4 :
2304 case Hexagon::LDrih_GP_cPt_V4 :
2305 case Hexagon::LDriuh_GP_cPt_V4 :
2306 case Hexagon::LDriw_GP_cPt_V4 :
2307 case Hexagon::LDd_GP_cPt_V4 :
2308 case Hexagon::LDb_GP_cPt_V4 :
2309 case Hexagon::LDub_GP_cPt_V4 :
2310 case Hexagon::LDh_GP_cPt_V4 :
2311 case Hexagon::LDuh_GP_cPt_V4 :
2312 case Hexagon::LDw_GP_cPt_V4 :
2313 case Hexagon::STrid_GP_cPt_V4 :
2314 case Hexagon::STrib_GP_cPt_V4 :
2315 case Hexagon::STrih_GP_cPt_V4 :
2316 case Hexagon::STriw_GP_cPt_V4 :
2317 case Hexagon::STd_GP_cPt_V4 :
2318 case Hexagon::STb_GP_cPt_V4 :
2319 case Hexagon::STh_GP_cPt_V4 :
2320 case Hexagon::STw_GP_cPt_V4 :
2321 case Hexagon::LDrid_GP_cdnPt_V4 :
2322 case Hexagon::LDrib_GP_cdnPt_V4 :
2323 case Hexagon::LDriub_GP_cdnPt_V4 :
2324 case Hexagon::LDrih_GP_cdnPt_V4 :
2325 case Hexagon::LDriuh_GP_cdnPt_V4 :
2326 case Hexagon::LDriw_GP_cdnPt_V4 :
2327 case Hexagon::LDd_GP_cdnPt_V4 :
2328 case Hexagon::LDb_GP_cdnPt_V4 :
2329 case Hexagon::LDub_GP_cdnPt_V4 :
2330 case Hexagon::LDh_GP_cdnPt_V4 :
2331 case Hexagon::LDuh_GP_cdnPt_V4 :
2332 case Hexagon::LDw_GP_cdnPt_V4 :
2333 case Hexagon::STrid_GP_cdnPt_V4 :
2334 case Hexagon::STrib_GP_cdnPt_V4 :
2335 case Hexagon::STrih_GP_cdnPt_V4 :
2336 case Hexagon::STriw_GP_cdnPt_V4 :
2337 case Hexagon::STd_GP_cdnPt_V4 :
2338 case Hexagon::STb_GP_cdnPt_V4 :
2339 case Hexagon::STh_GP_cdnPt_V4 :
2340 case Hexagon::STw_GP_cdnPt_V4 :
2343 case Hexagon::TFR_cNotPt:
2344 case Hexagon::TFR_cdnNotPt:
2345 case Hexagon::TFRI_cNotPt:
2346 case Hexagon::TFRI_cdnNotPt:
2347 case Hexagon::STrib_cNotPt :
2348 case Hexagon::STrib_cdnNotPt_V4 :
2349 case Hexagon::STrib_indexed_cNotPt :
2350 case Hexagon::STrib_indexed_cdnNotPt_V4 :
2351 case Hexagon::STrib_indexed_shl_cNotPt_V4 :
2352 case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
2353 case Hexagon::POST_STbri_cNotPt :
2354 case Hexagon::POST_STbri_cdnNotPt_V4 :
2355 case Hexagon::STrih_cNotPt :
2356 case Hexagon::STrih_cdnNotPt_V4 :
2357 case Hexagon::STrih_indexed_cNotPt :
2358 case Hexagon::STrih_indexed_cdnNotPt_V4 :
2359 case Hexagon::STrih_indexed_shl_cNotPt_V4 :
2360 case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
2361 case Hexagon::POST_SThri_cNotPt :
2362 case Hexagon::POST_SThri_cdnNotPt_V4 :
2363 case Hexagon::STriw_cNotPt :
2364 case Hexagon::STriw_cdnNotPt_V4 :
2365 case Hexagon::STriw_indexed_cNotPt :
2366 case Hexagon::STriw_indexed_cdnNotPt_V4 :
2367 case Hexagon::STriw_indexed_shl_cNotPt_V4 :
2368 case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
2369 case Hexagon::POST_STwri_cNotPt :
2370 case Hexagon::POST_STwri_cdnNotPt_V4 :
2371 case Hexagon::STrib_imm_cNotPt_V4 :
2372 case Hexagon::STrib_imm_cdnNotPt_V4 :
2373 case Hexagon::STrid_cNotPt :
2374 case Hexagon::STrid_cdnNotPt_V4 :
2375 case Hexagon::STrid_indexed_cdnNotPt_V4 :
2376 case Hexagon::STrid_indexed_cNotPt :
2377 case Hexagon::STrid_indexed_shl_cNotPt_V4 :
2378 case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
2379 case Hexagon::POST_STdri_cNotPt :
2380 case Hexagon::POST_STdri_cdnNotPt_V4 :
2381 case Hexagon::STrih_imm_cNotPt_V4 :
2382 case Hexagon::STrih_imm_cdnNotPt_V4 :
2383 case Hexagon::STriw_imm_cNotPt_V4 :
2384 case Hexagon::STriw_imm_cdnNotPt_V4 :
2385 case Hexagon::JMP_cdnNotPt :
2386 case Hexagon::LDrid_cNotPt :
2387 case Hexagon::LDrid_cdnNotPt :
2388 case Hexagon::LDrid_indexed_cNotPt :
2389 case Hexagon::LDrid_indexed_cdnNotPt :
2390 case Hexagon::POST_LDrid_cNotPt :
2391 case Hexagon::POST_LDrid_cdnNotPt_V4 :
2392 case Hexagon::LDriw_cNotPt :
2393 case Hexagon::LDriw_cdnNotPt :
2394 case Hexagon::LDriw_indexed_cNotPt :
2395 case Hexagon::LDriw_indexed_cdnNotPt :
2396 case Hexagon::POST_LDriw_cNotPt :
2397 case Hexagon::POST_LDriw_cdnNotPt_V4 :
2398 case Hexagon::LDrih_cNotPt :
2399 case Hexagon::LDrih_cdnNotPt :
2400 case Hexagon::LDrih_indexed_cNotPt :
2401 case Hexagon::LDrih_indexed_cdnNotPt :
2402 case Hexagon::POST_LDrih_cNotPt :
2403 case Hexagon::POST_LDrih_cdnNotPt_V4 :
2404 case Hexagon::LDrib_cNotPt :
2405 case Hexagon::LDrib_cdnNotPt :
2406 case Hexagon::LDrib_indexed_cNotPt :
2407 case Hexagon::LDrib_indexed_cdnNotPt :
2408 case Hexagon::POST_LDrib_cNotPt :
2409 case Hexagon::POST_LDrib_cdnNotPt_V4 :
2410 case Hexagon::LDriuh_cNotPt :
2411 case Hexagon::LDriuh_cdnNotPt :
2412 case Hexagon::LDriuh_indexed_cNotPt :
2413 case Hexagon::LDriuh_indexed_cdnNotPt :
2414 case Hexagon::POST_LDriuh_cNotPt :
2415 case Hexagon::POST_LDriuh_cdnNotPt_V4 :
2416 case Hexagon::LDriub_cNotPt :
2417 case Hexagon::LDriub_cdnNotPt :
2418 case Hexagon::LDriub_indexed_cNotPt :
2419 case Hexagon::LDriub_indexed_cdnNotPt :
2420 case Hexagon::POST_LDriub_cNotPt :
2421 case Hexagon::POST_LDriub_cdnNotPt_V4 :
2422 case Hexagon::LDrid_indexed_cNotPt_V4 :
2423 case Hexagon::LDrid_indexed_cdnNotPt_V4 :
2424 case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
2425 case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
2426 case Hexagon::LDrib_indexed_cNotPt_V4 :
2427 case Hexagon::LDrib_indexed_cdnNotPt_V4 :
2428 case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
2429 case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
2430 case Hexagon::LDriub_indexed_cNotPt_V4 :
2431 case Hexagon::LDriub_indexed_cdnNotPt_V4 :
2432 case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
2433 case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
2434 case Hexagon::LDrih_indexed_cNotPt_V4 :
2435 case Hexagon::LDrih_indexed_cdnNotPt_V4 :
2436 case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
2437 case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
2438 case Hexagon::LDriuh_indexed_cNotPt_V4 :
2439 case Hexagon::LDriuh_indexed_cdnNotPt_V4 :
2440 case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
2441 case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
2442 case Hexagon::LDriw_indexed_cNotPt_V4 :
2443 case Hexagon::LDriw_indexed_cdnNotPt_V4 :
2444 case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
2445 case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
2446 case Hexagon::ADD_ri_cNotPt :
2447 case Hexagon::ADD_ri_cdnNotPt :
2448 case Hexagon::ADD_rr_cNotPt :
2449 case Hexagon::ADD_rr_cdnNotPt :
2450 case Hexagon::XOR_rr_cNotPt :
2451 case Hexagon::XOR_rr_cdnNotPt :
2452 case Hexagon::AND_rr_cNotPt :
2453 case Hexagon::AND_rr_cdnNotPt :
2454 case Hexagon::OR_rr_cNotPt :
2455 case Hexagon::OR_rr_cdnNotPt :
2456 case Hexagon::SUB_rr_cNotPt :
2457 case Hexagon::SUB_rr_cdnNotPt :
2458 case Hexagon::COMBINE_rr_cNotPt :
2459 case Hexagon::COMBINE_rr_cdnNotPt :
2460 case Hexagon::ASLH_cNotPt_V4 :
2461 case Hexagon::ASLH_cdnNotPt_V4 :
2462 case Hexagon::ASRH_cNotPt_V4 :
2463 case Hexagon::ASRH_cdnNotPt_V4 :
2464 case Hexagon::SXTB_cNotPt_V4 :
2465 case Hexagon::SXTB_cdnNotPt_V4 :
2466 case Hexagon::SXTH_cNotPt_V4 :
2467 case Hexagon::SXTH_cdnNotPt_V4 :
2468 case Hexagon::ZXTB_cNotPt_V4 :
2469 case Hexagon::ZXTB_cdnNotPt_V4 :
2470 case Hexagon::ZXTH_cNotPt_V4 :
2471 case Hexagon::ZXTH_cdnNotPt_V4 :
2473 case Hexagon::LDrid_GP_cNotPt_V4 :
2474 case Hexagon::LDrib_GP_cNotPt_V4 :
2475 case Hexagon::LDriub_GP_cNotPt_V4 :
2476 case Hexagon::LDrih_GP_cNotPt_V4 :
2477 case Hexagon::LDriuh_GP_cNotPt_V4 :
2478 case Hexagon::LDriw_GP_cNotPt_V4 :
2479 case Hexagon::LDd_GP_cNotPt_V4 :
2480 case Hexagon::LDb_GP_cNotPt_V4 :
2481 case Hexagon::LDub_GP_cNotPt_V4 :
2482 case Hexagon::LDh_GP_cNotPt_V4 :
2483 case Hexagon::LDuh_GP_cNotPt_V4 :
2484 case Hexagon::LDw_GP_cNotPt_V4 :
2485 case Hexagon::STrid_GP_cNotPt_V4 :
2486 case Hexagon::STrib_GP_cNotPt_V4 :
2487 case Hexagon::STrih_GP_cNotPt_V4 :
2488 case Hexagon::STriw_GP_cNotPt_V4 :
2489 case Hexagon::STd_GP_cNotPt_V4 :
2490 case Hexagon::STb_GP_cNotPt_V4 :
2491 case Hexagon::STh_GP_cNotPt_V4 :
2492 case Hexagon::STw_GP_cNotPt_V4 :
2493 case Hexagon::LDrid_GP_cdnNotPt_V4 :
2494 case Hexagon::LDrib_GP_cdnNotPt_V4 :
2495 case Hexagon::LDriub_GP_cdnNotPt_V4 :
2496 case Hexagon::LDrih_GP_cdnNotPt_V4 :
2497 case Hexagon::LDriuh_GP_cdnNotPt_V4 :
2498 case Hexagon::LDriw_GP_cdnNotPt_V4 :
2499 case Hexagon::LDd_GP_cdnNotPt_V4 :
2500 case Hexagon::LDb_GP_cdnNotPt_V4 :
2501 case Hexagon::LDub_GP_cdnNotPt_V4 :
2502 case Hexagon::LDh_GP_cdnNotPt_V4 :
2503 case Hexagon::LDuh_GP_cdnNotPt_V4 :
2504 case Hexagon::LDw_GP_cdnNotPt_V4 :
2505 case Hexagon::STrid_GP_cdnNotPt_V4 :
2506 case Hexagon::STrib_GP_cdnNotPt_V4 :
2507 case Hexagon::STrih_GP_cdnNotPt_V4 :
2508 case Hexagon::STriw_GP_cdnNotPt_V4 :
2509 case Hexagon::STd_GP_cdnNotPt_V4 :
2510 case Hexagon::STb_GP_cdnNotPt_V4 :
2511 case Hexagon::STh_GP_cdnNotPt_V4 :
2512 case Hexagon::STw_GP_cdnNotPt_V4 :
2515 // return *some value* to avoid compiler warning
2519 bool HexagonPacketizerList::isDotNewInst(MachineInstr* MI) {
2520 if (isNewValueInst(MI))
2523 switch (MI->getOpcode()) {
2524 case Hexagon::TFR_cdnNotPt:
2525 case Hexagon::TFR_cdnPt:
2526 case Hexagon::TFRI_cdnNotPt:
2527 case Hexagon::TFRI_cdnPt:
2528 case Hexagon::LDrid_cdnPt :
2529 case Hexagon::LDrid_cdnNotPt :
2530 case Hexagon::LDrid_indexed_cdnPt :
2531 case Hexagon::LDrid_indexed_cdnNotPt :
2532 case Hexagon::POST_LDrid_cdnPt_V4 :
2533 case Hexagon::POST_LDrid_cdnNotPt_V4 :
2534 case Hexagon::LDriw_cdnPt :
2535 case Hexagon::LDriw_cdnNotPt :
2536 case Hexagon::LDriw_indexed_cdnPt :
2537 case Hexagon::LDriw_indexed_cdnNotPt :
2538 case Hexagon::POST_LDriw_cdnPt_V4 :
2539 case Hexagon::POST_LDriw_cdnNotPt_V4 :
2540 case Hexagon::LDrih_cdnPt :
2541 case Hexagon::LDrih_cdnNotPt :
2542 case Hexagon::LDrih_indexed_cdnPt :
2543 case Hexagon::LDrih_indexed_cdnNotPt :
2544 case Hexagon::POST_LDrih_cdnPt_V4 :
2545 case Hexagon::POST_LDrih_cdnNotPt_V4 :
2546 case Hexagon::LDrib_cdnPt :
2547 case Hexagon::LDrib_cdnNotPt :
2548 case Hexagon::LDrib_indexed_cdnPt :
2549 case Hexagon::LDrib_indexed_cdnNotPt :
2550 case Hexagon::POST_LDrib_cdnPt_V4 :
2551 case Hexagon::POST_LDrib_cdnNotPt_V4 :
2552 case Hexagon::LDriuh_cdnPt :
2553 case Hexagon::LDriuh_cdnNotPt :
2554 case Hexagon::LDriuh_indexed_cdnPt :
2555 case Hexagon::LDriuh_indexed_cdnNotPt :
2556 case Hexagon::POST_LDriuh_cdnPt_V4 :
2557 case Hexagon::POST_LDriuh_cdnNotPt_V4 :
2558 case Hexagon::LDriub_cdnPt :
2559 case Hexagon::LDriub_cdnNotPt :
2560 case Hexagon::LDriub_indexed_cdnPt :
2561 case Hexagon::LDriub_indexed_cdnNotPt :
2562 case Hexagon::POST_LDriub_cdnPt_V4 :
2563 case Hexagon::POST_LDriub_cdnNotPt_V4 :
2565 case Hexagon::LDrid_indexed_cdnPt_V4 :
2566 case Hexagon::LDrid_indexed_cdnNotPt_V4 :
2567 case Hexagon::LDrid_indexed_shl_cdnPt_V4 :
2568 case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 :
2569 case Hexagon::LDrib_indexed_cdnPt_V4 :
2570 case Hexagon::LDrib_indexed_cdnNotPt_V4 :
2571 case Hexagon::LDrib_indexed_shl_cdnPt_V4 :
2572 case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 :
2573 case Hexagon::LDriub_indexed_cdnPt_V4 :
2574 case Hexagon::LDriub_indexed_cdnNotPt_V4 :
2575 case Hexagon::LDriub_indexed_shl_cdnPt_V4 :
2576 case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 :
2577 case Hexagon::LDrih_indexed_cdnPt_V4 :
2578 case Hexagon::LDrih_indexed_cdnNotPt_V4 :
2579 case Hexagon::LDrih_indexed_shl_cdnPt_V4 :
2580 case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 :
2581 case Hexagon::LDriuh_indexed_cdnPt_V4 :
2582 case Hexagon::LDriuh_indexed_cdnNotPt_V4 :
2583 case Hexagon::LDriuh_indexed_shl_cdnPt_V4 :
2584 case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 :
2585 case Hexagon::LDriw_indexed_cdnPt_V4 :
2586 case Hexagon::LDriw_indexed_cdnNotPt_V4 :
2587 case Hexagon::LDriw_indexed_shl_cdnPt_V4 :
2588 case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 :
2591 case Hexagon::ADD_ri_cdnPt:
2592 case Hexagon::ADD_ri_cdnNotPt:
2593 case Hexagon::ADD_rr_cdnPt:
2594 case Hexagon::ADD_rr_cdnNotPt:
2596 // Conditional logical operations
2597 case Hexagon::XOR_rr_cdnPt :
2598 case Hexagon::XOR_rr_cdnNotPt :
2599 case Hexagon::AND_rr_cdnPt :
2600 case Hexagon::AND_rr_cdnNotPt :
2601 case Hexagon::OR_rr_cdnPt :
2602 case Hexagon::OR_rr_cdnNotPt :
2604 // Conditonal subtract
2605 case Hexagon::SUB_rr_cdnPt :
2606 case Hexagon::SUB_rr_cdnNotPt :
2608 // Conditional combine
2609 case Hexagon::COMBINE_rr_cdnPt :
2610 case Hexagon::COMBINE_rr_cdnNotPt :
2612 // Conditional shift operations
2613 case Hexagon::ASLH_cdnPt_V4:
2614 case Hexagon::ASLH_cdnNotPt_V4:
2615 case Hexagon::ASRH_cdnPt_V4:
2616 case Hexagon::ASRH_cdnNotPt_V4:
2617 case Hexagon::SXTB_cdnPt_V4:
2618 case Hexagon::SXTB_cdnNotPt_V4:
2619 case Hexagon::SXTH_cdnPt_V4:
2620 case Hexagon::SXTH_cdnNotPt_V4:
2621 case Hexagon::ZXTB_cdnPt_V4:
2622 case Hexagon::ZXTB_cdnNotPt_V4:
2623 case Hexagon::ZXTH_cdnPt_V4:
2624 case Hexagon::ZXTH_cdnNotPt_V4:
2626 // Conditional stores
2627 case Hexagon::STrib_imm_cdnPt_V4 :
2628 case Hexagon::STrib_imm_cdnNotPt_V4 :
2629 case Hexagon::STrib_cdnPt_V4 :
2630 case Hexagon::STrib_cdnNotPt_V4 :
2631 case Hexagon::STrib_indexed_cdnPt_V4 :
2632 case Hexagon::STrib_indexed_cdnNotPt_V4 :
2633 case Hexagon::POST_STbri_cdnPt_V4 :
2634 case Hexagon::POST_STbri_cdnNotPt_V4 :
2635 case Hexagon::STrib_indexed_shl_cdnPt_V4 :
2636 case Hexagon::STrib_indexed_shl_cdnNotPt_V4 :
2638 // Store doubleword conditionally
2639 case Hexagon::STrid_indexed_cdnPt_V4 :
2640 case Hexagon::STrid_indexed_cdnNotPt_V4 :
2641 case Hexagon::STrid_indexed_shl_cdnPt_V4 :
2642 case Hexagon::STrid_indexed_shl_cdnNotPt_V4 :
2643 case Hexagon::POST_STdri_cdnPt_V4 :
2644 case Hexagon::POST_STdri_cdnNotPt_V4 :
2646 // Store halfword conditionally
2647 case Hexagon::STrih_cdnPt_V4 :
2648 case Hexagon::STrih_cdnNotPt_V4 :
2649 case Hexagon::STrih_indexed_cdnPt_V4 :
2650 case Hexagon::STrih_indexed_cdnNotPt_V4 :
2651 case Hexagon::STrih_imm_cdnPt_V4 :
2652 case Hexagon::STrih_imm_cdnNotPt_V4 :
2653 case Hexagon::STrih_indexed_shl_cdnPt_V4 :
2654 case Hexagon::STrih_indexed_shl_cdnNotPt_V4 :
2655 case Hexagon::POST_SThri_cdnPt_V4 :
2656 case Hexagon::POST_SThri_cdnNotPt_V4 :
2658 // Store word conditionally
2659 case Hexagon::STriw_cdnPt_V4 :
2660 case Hexagon::STriw_cdnNotPt_V4 :
2661 case Hexagon::STriw_indexed_cdnPt_V4 :
2662 case Hexagon::STriw_indexed_cdnNotPt_V4 :
2663 case Hexagon::STriw_imm_cdnPt_V4 :
2664 case Hexagon::STriw_imm_cdnNotPt_V4 :
2665 case Hexagon::STriw_indexed_shl_cdnPt_V4 :
2666 case Hexagon::STriw_indexed_shl_cdnNotPt_V4 :
2667 case Hexagon::POST_STwri_cdnPt_V4 :
2668 case Hexagon::POST_STwri_cdnNotPt_V4 :
2670 case Hexagon::LDd_GP_cdnPt_V4:
2671 case Hexagon::LDd_GP_cdnNotPt_V4:
2672 case Hexagon::LDb_GP_cdnPt_V4:
2673 case Hexagon::LDb_GP_cdnNotPt_V4:
2674 case Hexagon::LDub_GP_cdnPt_V4:
2675 case Hexagon::LDub_GP_cdnNotPt_V4:
2676 case Hexagon::LDh_GP_cdnPt_V4:
2677 case Hexagon::LDh_GP_cdnNotPt_V4:
2678 case Hexagon::LDuh_GP_cdnPt_V4:
2679 case Hexagon::LDuh_GP_cdnNotPt_V4:
2680 case Hexagon::LDw_GP_cdnPt_V4:
2681 case Hexagon::LDw_GP_cdnNotPt_V4:
2682 case Hexagon::LDrid_GP_cdnPt_V4:
2683 case Hexagon::LDrid_GP_cdnNotPt_V4:
2684 case Hexagon::LDrib_GP_cdnPt_V4:
2685 case Hexagon::LDrib_GP_cdnNotPt_V4:
2686 case Hexagon::LDriub_GP_cdnPt_V4:
2687 case Hexagon::LDriub_GP_cdnNotPt_V4:
2688 case Hexagon::LDrih_GP_cdnPt_V4:
2689 case Hexagon::LDrih_GP_cdnNotPt_V4:
2690 case Hexagon::LDriuh_GP_cdnPt_V4:
2691 case Hexagon::LDriuh_GP_cdnNotPt_V4:
2692 case Hexagon::LDriw_GP_cdnPt_V4:
2693 case Hexagon::LDriw_GP_cdnNotPt_V4:
2695 case Hexagon::STrid_GP_cdnPt_V4:
2696 case Hexagon::STrid_GP_cdnNotPt_V4:
2697 case Hexagon::STrib_GP_cdnPt_V4:
2698 case Hexagon::STrib_GP_cdnNotPt_V4:
2699 case Hexagon::STrih_GP_cdnPt_V4:
2700 case Hexagon::STrih_GP_cdnNotPt_V4:
2701 case Hexagon::STriw_GP_cdnPt_V4:
2702 case Hexagon::STriw_GP_cdnNotPt_V4:
2703 case Hexagon::STd_GP_cdnPt_V4:
2704 case Hexagon::STd_GP_cdnNotPt_V4:
2705 case Hexagon::STb_GP_cdnPt_V4:
2706 case Hexagon::STb_GP_cdnNotPt_V4:
2707 case Hexagon::STh_GP_cdnPt_V4:
2708 case Hexagon::STh_GP_cdnNotPt_V4:
2709 case Hexagon::STw_GP_cdnPt_V4:
2710 case Hexagon::STw_GP_cdnNotPt_V4:
2716 static MachineOperand& GetPostIncrementOperand(MachineInstr *MI,
2717 const HexagonInstrInfo *QII) {
2718 assert(QII->isPostIncrement(MI) && "Not a post increment operation.");
2720 // Post Increment means duplicates. Use dense map to find duplicates in the
2721 // list. Caution: Densemap initializes with the minimum of 64 buckets,
2722 // whereas there are at most 5 operands in the post increment.
2723 DenseMap<unsigned, unsigned> DefRegsSet;
2724 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
2725 if (MI->getOperand(opNum).isReg() &&
2726 MI->getOperand(opNum).isDef()) {
2727 DefRegsSet[MI->getOperand(opNum).getReg()] = 1;
2730 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++)
2731 if (MI->getOperand(opNum).isReg() &&
2732 MI->getOperand(opNum).isUse()) {
2733 if (DefRegsSet[MI->getOperand(opNum).getReg()]) {
2734 return MI->getOperand(opNum);
2738 if (MI->getDesc().mayLoad()) {
2739 // The 2nd operand is always the post increment operand in load.
2740 assert(MI->getOperand(1).isReg() &&
2741 "Post increment operand has be to a register.");
2742 return (MI->getOperand(1));
2744 if (MI->getDesc().mayStore()) {
2745 // The 1st operand is always the post increment operand in store.
2746 assert(MI->getOperand(0).isReg() &&
2747 "Post increment operand has be to a register.");
2748 return (MI->getOperand(0));
2751 // we should never come here.
2752 llvm_unreachable("mayLoad or mayStore not set for Post Increment operation");
2755 // get the value being stored
2756 static MachineOperand& GetStoreValueOperand(MachineInstr *MI) {
2757 // value being stored is always the last operand.
2758 return (MI->getOperand(MI->getNumOperands()-1));
2761 // can be new value store?
2762 // Following restrictions are to be respected in convert a store into
2763 // a new value store.
2764 // 1. If an instruction uses auto-increment, its address register cannot
2765 // be a new-value register. Arch Spec 5.4.2.1
2766 // 2. If an instruction uses absolute-set addressing mode,
2767 // its address register cannot be a new-value register.
2768 // Arch Spec 5.4.2.1.TODO: This is not enabled as
2769 // as absolute-set address mode patters are not implemented.
2770 // 3. If an instruction produces a 64-bit result, its registers cannot be used
2771 // as new-value registers. Arch Spec 5.4.2.2.
2772 // 4. If the instruction that sets a new-value register is conditional, then
2773 // the instruction that uses the new-value register must also be conditional,
2774 // and both must always have their predicates evaluate identically.
2775 // Arch Spec 5.4.2.3.
2776 // 5. There is an implied restriction of a packet can not have another store,
2777 // if there is a new value store in the packet. Corollary, if there is
2778 // already a store in a packet, there can not be a new value store.
2779 // Arch Spec: 3.4.4.2
2780 bool HexagonPacketizerList::CanPromoteToNewValueStore( MachineInstr *MI,
2781 MachineInstr *PacketMI, unsigned DepReg,
2782 std::map <MachineInstr*, SUnit*> MIToSUnit)
2784 // Make sure we are looking at the store
2785 if (!IsNewifyStore(MI))
2788 // Make sure there is dependency and can be new value'ed
2789 if (GetStoreValueOperand(MI).isReg() &&
2790 GetStoreValueOperand(MI).getReg() != DepReg)
2793 const HexagonRegisterInfo* QRI =
2794 (const HexagonRegisterInfo *) TM.getRegisterInfo();
2795 const MCInstrDesc& MCID = PacketMI->getDesc();
2796 // first operand is always the result
2798 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
2799 const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI, MF);
2801 // if there is already an store in the packet, no can do new value store
2802 // Arch Spec 3.4.4.2.
2803 for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
2804 VE = CurrentPacketMIs.end();
2806 SUnit* PacketSU = MIToSUnit[*VI];
2807 if (PacketSU->getInstr()->getDesc().mayStore() ||
2808 // if we have mayStore = 1 set on ALLOCFRAME and DEALLOCFRAME,
2809 // then we don't need this
2810 PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
2811 PacketSU->getInstr()->getOpcode() == Hexagon::DEALLOCFRAME)
2815 if (PacketRC == &Hexagon::DoubleRegsRegClass) {
2816 // new value store constraint: double regs can not feed into new value store
2817 // arch spec section: 5.4.2.2
2821 // Make sure it's NOT the post increment register that we are going to
2823 if (QII->isPostIncrement(MI) &&
2824 MI->getDesc().mayStore() &&
2825 GetPostIncrementOperand(MI, QII).getReg() == DepReg) {
2829 if (QII->isPostIncrement(PacketMI) &&
2830 PacketMI->getDesc().mayLoad() &&
2831 GetPostIncrementOperand(PacketMI, QII).getReg() == DepReg) {
2832 // if source is post_inc, or absolute-set addressing,
2833 // it can not feed into new value store
2834 // r3 = memw(r2++#4)
2835 // memw(r30 + #-1404) = r2.new -> can not be new value store
2836 // arch spec section: 5.4.2.1
2840 // If the source that feeds the store is predicated, new value store must
2841 // also be also predicated.
2842 if (QII->isPredicated(PacketMI)) {
2843 if (!QII->isPredicated(MI))
2846 // Check to make sure that they both will have their predicates
2847 // evaluate identically
2848 unsigned predRegNumSrc = 0;
2849 unsigned predRegNumDst = 0;
2850 const TargetRegisterClass* predRegClass = NULL;
2852 // Get predicate register used in the source instruction
2853 for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
2854 if ( PacketMI->getOperand(opNum).isReg())
2855 predRegNumSrc = PacketMI->getOperand(opNum).getReg();
2856 predRegClass = QRI->getMinimalPhysRegClass(predRegNumSrc);
2857 if (predRegClass == &Hexagon::PredRegsRegClass) {
2861 assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
2862 ("predicate register not found in a predicated PacketMI instruction"));
2864 // Get predicate register used in new-value store instruction
2865 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
2866 if ( MI->getOperand(opNum).isReg())
2867 predRegNumDst = MI->getOperand(opNum).getReg();
2868 predRegClass = QRI->getMinimalPhysRegClass(predRegNumDst);
2869 if (predRegClass == &Hexagon::PredRegsRegClass) {
2873 assert ((predRegClass == &Hexagon::PredRegsRegClass ) &&
2874 ("predicate register not found in a predicated MI instruction"));
2876 // New-value register producer and user (store) need to satisfy these
2878 // 1) Both instructions should be predicated on the same register.
2879 // 2) If producer of the new-value register is .new predicated then store
2880 // should also be .new predicated and if producer is not .new predicated
2881 // then store should not be .new predicated.
2882 // 3) Both new-value register producer and user should have same predicate
2883 // sense, i.e, either both should be negated or both should be none negated.
2885 if (( predRegNumDst != predRegNumSrc) ||
2886 isDotNewInst(PacketMI) != isDotNewInst(MI) ||
2887 GetPredicateSense(MI, QII) != GetPredicateSense(PacketMI, QII)) {
2892 // Make sure that other than the new-value register no other store instruction
2893 // register has been modified in the same packet. Predicate registers can be
2894 // modified by they should not be modified between the producer and the store
2895 // instruction as it will make them both conditional on different values.
2896 // We already know this to be true for all the instructions before and
2897 // including PacketMI. Howerver, we need to perform the check for the
2898 // remaining instructions in the packet.
2900 std::vector<MachineInstr*>::iterator VI;
2901 std::vector<MachineInstr*>::iterator VE;
2902 unsigned StartCheck = 0;
2904 for (VI=CurrentPacketMIs.begin(), VE = CurrentPacketMIs.end();
2906 SUnit* TempSU = MIToSUnit[*VI];
2907 MachineInstr* TempMI = TempSU->getInstr();
2909 // Following condition is true for all the instructions until PacketMI is
2910 // reached (StartCheck is set to 0 before the for loop).
2911 // StartCheck flag is 1 for all the instructions after PacketMI.
2912 if (TempMI != PacketMI && !StartCheck) // start processing only after
2913 continue; // encountering PacketMI
2916 if (TempMI == PacketMI) // We don't want to check PacketMI for dependence
2919 for(unsigned opNum = 0; opNum < MI->getNumOperands(); opNum++) {
2920 if (MI->getOperand(opNum).isReg() &&
2921 TempSU->getInstr()->modifiesRegister(MI->getOperand(opNum).getReg(),
2927 // Make sure that for non POST_INC stores:
2928 // 1. The only use of reg is DepReg and no other registers.
2929 // This handles V4 base+index registers.
2930 // The following store can not be dot new.
2931 // Eg. r0 = add(r0, #3)a
2932 // memw(r1+r0<<#2) = r0
2933 if (!QII->isPostIncrement(MI) &&
2934 GetStoreValueOperand(MI).isReg() &&
2935 GetStoreValueOperand(MI).getReg() == DepReg) {
2936 for(unsigned opNum = 0; opNum < MI->getNumOperands()-1; opNum++) {
2937 if (MI->getOperand(opNum).isReg() &&
2938 MI->getOperand(opNum).getReg() == DepReg) {
2942 // 2. If data definition is because of implicit definition of the register,
2943 // do not newify the store. Eg.
2944 // %R9<def> = ZXTH %R12, %D6<imp-use>, %R12<imp-def>
2945 // STrih_indexed %R8, 2, %R12<kill>; mem:ST2[%scevgep343]
2946 for(unsigned opNum = 0; opNum < PacketMI->getNumOperands(); opNum++) {
2947 if (PacketMI->getOperand(opNum).isReg() &&
2948 PacketMI->getOperand(opNum).getReg() == DepReg &&
2949 PacketMI->getOperand(opNum).isDef() &&
2950 PacketMI->getOperand(opNum).isImplicit()) {
2956 // Can be dot new store.
2960 // can this MI to promoted to either
2961 // new value store or new value jump
2962 bool HexagonPacketizerList::CanPromoteToNewValue( MachineInstr *MI,
2963 SUnit *PacketSU, unsigned DepReg,
2964 std::map <MachineInstr*, SUnit*> MIToSUnit,
2965 MachineBasicBlock::iterator &MII)
2968 const HexagonRegisterInfo* QRI =
2969 (const HexagonRegisterInfo *) TM.getRegisterInfo();
2970 if (!QRI->Subtarget.hasV4TOps() ||
2974 MachineInstr *PacketMI = PacketSU->getInstr();
2976 // Check to see the store can be new value'ed.
2977 if (CanPromoteToNewValueStore(MI, PacketMI, DepReg, MIToSUnit))
2980 // Check to see the compare/jump can be new value'ed.
2981 // This is done as a pass on its own. Don't need to check it here.
2985 // Check to see if an instruction can be dot new
2986 // There are three kinds.
2987 // 1. dot new on predicate - V2/V3/V4
2988 // 2. dot new on stores NV/ST - V4
2989 // 3. dot new on jump NV/J - V4 -- This is generated in a pass.
2990 bool HexagonPacketizerList::CanPromoteToDotNew( MachineInstr *MI,
2991 SUnit *PacketSU, unsigned DepReg,
2992 std::map <MachineInstr*, SUnit*> MIToSUnit,
2993 MachineBasicBlock::iterator &MII,
2994 const TargetRegisterClass* RC )
2996 // already a dot new instruction
2997 if (isDotNewInst(MI) && !IsNewifyStore(MI))
3000 if (!isNewifiable(MI))
3004 if (RC == &Hexagon::PredRegsRegClass && isCondInst(MI))
3006 else if (RC != &Hexagon::PredRegsRegClass &&
3007 !IsNewifyStore(MI)) // MI is not a new-value store
3010 // Create a dot new machine instruction to see if resources can be
3011 // allocated. If not, bail out now.
3012 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
3013 int NewOpcode = GetDotNewOp(MI->getOpcode());
3014 const MCInstrDesc &desc = QII->get(NewOpcode);
3016 MachineInstr *NewMI =
3017 MI->getParent()->getParent()->CreateMachineInstr(desc, dl);
3018 bool ResourcesAvailable = ResourceTracker->canReserveResources(NewMI);
3019 MI->getParent()->getParent()->DeleteMachineInstr(NewMI);
3021 if (!ResourcesAvailable)
3024 // new value store only
3025 // new new value jump generated as a passes
3026 if (!CanPromoteToNewValue(MI, PacketSU, DepReg, MIToSUnit, MII)) {
3033 // Go through the packet instructions and search for anti dependency
3034 // between them and DepReg from MI
3035 // Consider this case:
3037 // a) %R1<def> = TFRI_cdNotPt %P3, 2
3040 // b) %P0<def> = OR_pp %P3<kill>, %P0<kill>
3041 // c) %P3<def> = TFR_PdRs %R23
3042 // d) %R1<def> = TFRI_cdnPt %P3, 4
3044 // The P3 from a) and d) will be complements after
3045 // a)'s P3 is converted to .new form
3046 // Anti Dep between c) and b) is irrelevant for this case
3047 bool HexagonPacketizerList::RestrictingDepExistInPacket (MachineInstr* MI,
3049 std::map <MachineInstr*, SUnit*> MIToSUnit) {
3051 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
3052 SUnit* PacketSUDep = MIToSUnit[MI];
3054 for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
3055 VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
3057 // We only care for dependencies to predicated instructions
3058 if(!QII->isPredicated(*VIN)) continue;
3060 // Scheduling Unit for current insn in the packet
3061 SUnit* PacketSU = MIToSUnit[*VIN];
3063 // Look at dependencies between current members of the packet
3064 // and predicate defining instruction MI.
3065 // Make sure that dependency is on the exact register
3067 if (PacketSU->isSucc(PacketSUDep)) {
3068 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
3069 if ((PacketSU->Succs[i].getSUnit() == PacketSUDep) &&
3070 (PacketSU->Succs[i].getKind() == SDep::Anti) &&
3071 (PacketSU->Succs[i].getReg() == DepReg)) {
3082 // Given two predicated instructions, this function detects whether
3083 // the predicates are complements
3084 bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1,
3085 MachineInstr* MI2, std::map <MachineInstr*, SUnit*> MIToSUnit) {
3087 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
3088 // Currently can only reason about conditional transfers
3089 if (!QII->isConditionalTransfer(MI1) || !QII->isConditionalTransfer(MI2)) {
3093 // Scheduling unit for candidate
3094 SUnit* SU = MIToSUnit[MI1];
3096 // One corner case deals with the following scenario:
3098 // a) %R24<def> = TFR_cPt %P0, %R25
3102 // b) %R25<def> = TFR_cNotPt %P0, %R24
3103 // c) %P0<def> = CMPEQri %R26, 1
3106 // On general check a) and b) are complements, but
3107 // presence of c) will convert a) to .new form, and
3108 // then it is not a complement
3109 // We attempt to detect it by analyzing existing
3110 // dependencies in the packet
3112 // Analyze relationships between all existing members of the packet.
3113 // Look for Anti dependecy on the same predicate reg
3114 // as used in the candidate
3115 for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
3116 VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
3118 // Scheduling Unit for current insn in the packet
3119 SUnit* PacketSU = MIToSUnit[*VIN];
3121 // If this instruction in the packet is succeeded by the candidate...
3122 if (PacketSU->isSucc(SU)) {
3123 for (unsigned i = 0; i < PacketSU->Succs.size(); ++i) {
3124 // The corner case exist when there is true data
3125 // dependency between candidate and one of current
3126 // packet members, this dep is on predicate reg, and
3127 // there already exist anti dep on the same pred in
3129 if (PacketSU->Succs[i].getSUnit() == SU &&
3130 Hexagon::PredRegsRegClass.contains(
3131 PacketSU->Succs[i].getReg()) &&
3132 PacketSU->Succs[i].getKind() == SDep::Data &&
3133 // Here I know that *VIN is predicate setting instruction
3134 // with true data dep to candidate on the register
3135 // we care about - c) in the above example.
3136 // Now I need to see if there is an anti dependency
3137 // from c) to any other instruction in the
3138 // same packet on the pred reg of interest
3139 RestrictingDepExistInPacket(*VIN,PacketSU->Succs[i].getReg(),
3147 // If the above case does not apply, check regular
3148 // complement condition.
3149 // Check that the predicate register is the same and
3150 // that the predicate sense is different
3151 // We also need to differentiate .old vs. .new:
3152 // !p0 is not complimentary to p0.new
3153 return ((MI1->getOperand(1).getReg() == MI2->getOperand(1).getReg()) &&
3154 (GetPredicateSense(MI1, QII) != GetPredicateSense(MI2, QII)) &&
3155 (isDotNewInst(MI1) == isDotNewInst(MI2)));
3158 // initPacketizerState - Initialize packetizer flags
3159 void HexagonPacketizerList::initPacketizerState() {
3162 PromotedToDotNew = false;
3163 GlueToNewValueJump = false;
3164 GlueAllocframeStore = false;
3165 FoundSequentialDependence = false;
3170 // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
3171 bool HexagonPacketizerList::ignorePseudoInstruction(MachineInstr *MI,
3172 MachineBasicBlock *MBB) {
3173 if (MI->isDebugValue())
3176 // We must print out inline assembly
3177 if (MI->isInlineAsm())
3180 // We check if MI has any functional units mapped to it.
3181 // If it doesn't, we ignore the instruction.
3182 const MCInstrDesc& TID = MI->getDesc();
3183 unsigned SchedClass = TID.getSchedClass();
3184 const InstrStage* IS =
3185 ResourceTracker->getInstrItins()->beginStage(SchedClass);
3186 unsigned FuncUnits = IS->getUnits();
3190 // isSoloInstruction: - Returns true for instructions that must be
3191 // scheduled in their own packet.
3192 bool HexagonPacketizerList::isSoloInstruction(MachineInstr *MI) {
3194 if (MI->isInlineAsm())
3197 if (MI->isEHLabel())
3200 // From Hexagon V4 Programmer's Reference Manual 3.4.4 Grouping constraints:
3201 // trap, pause, barrier, icinva, isync, and syncht are solo instructions.
3202 // They must not be grouped with other instructions in a packet.
3203 if (IsSchedBarrier(MI))
3209 // isLegalToPacketizeTogether:
3210 // SUI is the current instruction that is out side of the current packet.
3211 // SUJ is the current instruction inside the current packet against which that
3212 // SUI will be packetized.
3213 bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
3214 MachineInstr *I = SUI->getInstr();
3215 MachineInstr *J = SUJ->getInstr();
3216 assert(I && J && "Unable to packetize null instruction!");
3218 const MCInstrDesc &MCIDI = I->getDesc();
3219 const MCInstrDesc &MCIDJ = J->getDesc();
3221 MachineBasicBlock::iterator II = I;
3223 const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
3224 const HexagonRegisterInfo* QRI =
3225 (const HexagonRegisterInfo *) TM.getRegisterInfo();
3226 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
3228 // Inline asm cannot go in the packet.
3229 if (I->getOpcode() == Hexagon::INLINEASM)
3230 llvm_unreachable("Should not meet inline asm here!");
3232 if (isSoloInstruction(I))
3233 llvm_unreachable("Should not meet solo instr here!");
3235 // A save callee-save register function call can only be in a packet
3236 // with instructions that don't write to the callee-save registers.
3237 if ((QII->isSaveCalleeSavedRegsCall(I) &&
3238 DoesModifyCalleeSavedReg(J, QRI)) ||
3239 (QII->isSaveCalleeSavedRegsCall(J) &&
3240 DoesModifyCalleeSavedReg(I, QRI))) {
3245 // Two control flow instructions cannot go in the same packet.
3246 if (IsControlFlow(I) && IsControlFlow(J)) {
3251 // A LoopN instruction cannot appear in the same packet as a jump or call.
3252 if (IsLoopN(I) && ( IsDirectJump(J)
3254 || QII->isDeallocRet(J))) {
3258 if (IsLoopN(J) && ( IsDirectJump(I)
3260 || QII->isDeallocRet(I))) {
3265 // dealloc_return cannot appear in the same packet as a conditional or
3266 // unconditional jump.
3267 if (QII->isDeallocRet(I) && ( MCIDJ.isBranch()
3269 || MCIDJ.isBarrier())) {
3275 // V4 allows dual store. But does not allow second store, if the
3276 // first store is not in SLOT0. New value store, new value jump,
3277 // dealloc_return and memop always take SLOT0.
3278 // Arch spec 3.4.4.2
3279 if (QRI->Subtarget.hasV4TOps()) {
3281 if (MCIDI.mayStore() && MCIDJ.mayStore() && isNewValueInst(J)) {
3286 if ( (QII->isMemOp(J) && MCIDI.mayStore())
3287 || (MCIDJ.mayStore() && QII->isMemOp(I))
3288 || (QII->isMemOp(J) && QII->isMemOp(I))) {
3294 if (MCIDJ.mayStore() && QII->isDeallocRet(I)){
3299 // If an instruction feeds new value jump, glue it.
3300 MachineBasicBlock::iterator NextMII = I;
3302 MachineInstr *NextMI = NextMII;
3304 if (QII->isNewValueJump(NextMI)) {
3306 bool secondRegMatch = false;
3307 bool maintainNewValueJump = false;
3309 if (NextMI->getOperand(1).isReg() &&
3310 I->getOperand(0).getReg() == NextMI->getOperand(1).getReg()) {
3311 secondRegMatch = true;
3312 maintainNewValueJump = true;
3315 if (!secondRegMatch &&
3316 I->getOperand(0).getReg() == NextMI->getOperand(0).getReg()) {
3317 maintainNewValueJump = true;
3320 for (std::vector<MachineInstr*>::iterator
3321 VI = CurrentPacketMIs.begin(),
3322 VE = CurrentPacketMIs.end();
3323 (VI != VE && maintainNewValueJump); ++VI) {
3324 SUnit* PacketSU = MIToSUnit[*VI];
3326 // NVJ can not be part of the dual jump - Arch Spec: section 7.8
3327 if (PacketSU->getInstr()->getDesc().isCall()) {
3332 // 1. Packet does not have a store in it.
3333 // 2. If the first operand of the nvj is newified, and the second
3334 // operand is also a reg, it (second reg) is not defined in
3336 // 3. If the second operand of the nvj is newified, (which means
3337 // first operand is also a reg), first reg is not defined in
3339 if (PacketSU->getInstr()->getDesc().mayStore() ||
3340 PacketSU->getInstr()->getOpcode() == Hexagon::ALLOCFRAME ||
3342 (!secondRegMatch && NextMI->getOperand(1).isReg() &&
3343 PacketSU->getInstr()->modifiesRegister(
3344 NextMI->getOperand(1).getReg(), QRI)) ||
3347 PacketSU->getInstr()->modifiesRegister(
3348 NextMI->getOperand(0).getReg(), QRI))) {
3354 GlueToNewValueJump = true;
3360 if (SUJ->isSucc(SUI)) {
3361 for (unsigned i = 0;
3362 (i < SUJ->Succs.size()) && !FoundSequentialDependence;
3365 if (SUJ->Succs[i].getSUnit() != SUI) {
3369 SDep::Kind DepType = SUJ->Succs[i].getKind();
3371 // For direct calls:
3372 // Ignore register dependences for call instructions for
3373 // packetization purposes except for those due to r31 and
3374 // predicate registers.
3376 // For indirect calls:
3377 // Same as direct calls + check for true dependences to the register
3378 // used in the indirect call.
3380 // We completely ignore Order dependences for call instructions
3383 // Ignore register dependences for return instructions like jumpr,
3384 // dealloc return unless we have dependencies on the explicit uses
3385 // of the registers used by jumpr (like r31) or dealloc return
3386 // (like r29 or r30).
3388 // TODO: Currently, jumpr is handling only return of r31. So, the
3389 // following logic (specificaly IsCallDependent) is working fine.
3390 // We need to enable jumpr for register other than r31 and then,
3391 // we need to rework the last part, where it handles indirect call
3392 // of that (IsCallDependent) function. Bug 6216 is opened for this.
3394 unsigned DepReg = 0;
3395 const TargetRegisterClass* RC = NULL;
3396 if (DepType == SDep::Data) {
3397 DepReg = SUJ->Succs[i].getReg();
3398 RC = QRI->getMinimalPhysRegClass(DepReg);
3400 if ((MCIDI.isCall() || MCIDI.isReturn()) &&
3401 (!IsRegDependence(DepType) ||
3402 !IsCallDependent(I, DepType, SUJ->Succs[i].getReg()))) {
3406 // For instructions that can be promoted to dot-new, try to promote.
3407 else if ((DepType == SDep::Data) &&
3408 CanPromoteToDotNew(I, SUJ, DepReg, MIToSUnit, II, RC) &&
3409 PromoteToDotNew(I, DepType, II, RC)) {
3410 PromotedToDotNew = true;
3414 else if ((DepType == SDep::Data) &&
3415 (QII->isNewValueJump(I))) {
3419 // For predicated instructions, if the predicates are complements
3420 // then there can be no dependence.
3421 else if (QII->isPredicated(I) &&
3422 QII->isPredicated(J) &&
3423 ArePredicatesComplements(I, J, MIToSUnit)) {
3427 else if (IsDirectJump(I) &&
3428 !MCIDJ.isBranch() &&
3430 (DepType == SDep::Order)) {
3431 // Ignore Order dependences between unconditional direct branches
3432 // and non-control-flow instructions
3435 else if (MCIDI.isConditionalBranch() && (DepType != SDep::Data) &&
3436 (DepType != SDep::Output)) {
3437 // Ignore all dependences for jumps except for true and output
3442 // Ignore output dependences due to superregs. We can
3443 // write to two different subregisters of R1:0 for instance
3444 // in the same cycle
3449 // If neither I nor J defines DepReg, then this is a
3450 // superfluous output dependence. The dependence must be of the
3454 // and there is an output dependence between the two instructions
3457 // We want to ignore these dependences.
3458 // Ideally, the dependence constructor should annotate such
3459 // dependences. We can then avoid this relatively expensive check.
3461 else if (DepType == SDep::Output) {
3462 // DepReg is the register that's responsible for the dependence.
3463 unsigned DepReg = SUJ->Succs[i].getReg();
3465 // Check if I and J really defines DepReg.
3466 if (I->definesRegister(DepReg) ||
3467 J->definesRegister(DepReg)) {
3468 FoundSequentialDependence = true;
3473 // We ignore Order dependences for
3474 // 1. Two loads unless they are volatile.
3475 // 2. Two stores in V4 unless they are volatile.
3476 else if ((DepType == SDep::Order) &&
3477 !I->hasVolatileMemoryRef() &&
3478 !J->hasVolatileMemoryRef()) {
3479 if (QRI->Subtarget.hasV4TOps() &&
3480 // hexagonv4 allows dual store.
3481 MCIDI.mayStore() && MCIDJ.mayStore()) {
3484 // store followed by store-- not OK on V2
3485 // store followed by load -- not OK on all (OK if addresses
3487 // load followed by store -- OK on all
3488 // load followed by load -- OK on all
3489 else if ( !MCIDJ.mayStore()) {
3493 FoundSequentialDependence = true;
3498 // For V4, special case ALLOCFRAME. Even though there is dependency
3499 // between ALLOCAFRAME and subsequent store, allow it to be
3500 // packetized in a same packet. This implies that the store is using
3501 // caller's SP. Hense, offset needs to be updated accordingly.
3502 else if (DepType == SDep::Data
3503 && QRI->Subtarget.hasV4TOps()
3504 && J->getOpcode() == Hexagon::ALLOCFRAME
3505 && (I->getOpcode() == Hexagon::STrid
3506 || I->getOpcode() == Hexagon::STriw
3507 || I->getOpcode() == Hexagon::STrib)
3508 && I->getOperand(0).getReg() == QRI->getStackRegister()
3509 && QII->isValidOffset(I->getOpcode(),
3510 I->getOperand(1).getImm() -
3511 (FrameSize + HEXAGON_LRFP_SIZE)))
3513 GlueAllocframeStore = true;
3514 // Since this store is to be glued with allocframe in the same
3515 // packet, it will use SP of the previous stack frame, i.e
3516 // caller's SP. Therefore, we need to recalculate offset according
3518 I->getOperand(1).setImm(I->getOperand(1).getImm() -
3519 (FrameSize + HEXAGON_LRFP_SIZE));
3523 // Skip over anti-dependences. Two instructions that are
3524 // anti-dependent can share a packet
3526 else if (DepType != SDep::Anti) {
3527 FoundSequentialDependence = true;
3532 if (FoundSequentialDependence) {
3541 // isLegalToPruneDependencies
3542 bool HexagonPacketizerList::isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
3543 MachineInstr *I = SUI->getInstr();
3544 assert(I && SUJ->getInstr() && "Unable to packetize null instruction!");
3546 const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
3550 // Check if the instruction was promoted to a dot-new. If so, demote it
3551 // back into a dot-old.
3552 if (PromotedToDotNew) {
3556 // Check if the instruction (must be a store) was glued with an Allocframe
3557 // instruction. If so, restore its offset to its original value, i.e. use
3558 // curent SP instead of caller's SP.
3559 if (GlueAllocframeStore) {
3560 I->getOperand(1).setImm(I->getOperand(1).getImm() +
3561 FrameSize + HEXAGON_LRFP_SIZE);
3569 MachineBasicBlock::iterator
3570 HexagonPacketizerList::addToPacket(MachineInstr *MI) {
3572 MachineBasicBlock::iterator MII = MI;
3573 MachineBasicBlock *MBB = MI->getParent();
3575 const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
3577 if (GlueToNewValueJump) {
3580 MachineInstr *nvjMI = MII;
3581 assert(ResourceTracker->canReserveResources(MI));
3582 ResourceTracker->reserveResources(MI);
3583 if (QII->isExtended(MI) &&
3584 !tryAllocateResourcesForConstExt(MI)) {
3586 ResourceTracker->reserveResources(MI);
3587 assert(canReserveResourcesForConstExt(MI) &&
3588 "Ensure that there is a slot");
3589 reserveResourcesForConstExt(MI);
3590 // Reserve resources for new value jump constant extender.
3591 assert(canReserveResourcesForConstExt(MI) &&
3592 "Ensure that there is a slot");
3593 reserveResourcesForConstExt(nvjMI);
3594 assert(ResourceTracker->canReserveResources(nvjMI) &&
3595 "Ensure that there is a slot");
3597 } else if ( // Extended instruction takes two slots in the packet.
3598 // Try reserve and allocate 4-byte in the current packet first.
3599 (QII->isExtended(nvjMI)
3600 && (!tryAllocateResourcesForConstExt(nvjMI)
3601 || !ResourceTracker->canReserveResources(nvjMI)))
3602 || // For non-extended instruction, no need to allocate extra 4 bytes.
3603 (!QII->isExtended(nvjMI) &&
3604 !ResourceTracker->canReserveResources(nvjMI)))
3607 // A new and empty packet starts.
3608 // We are sure that the resources requirements can be satisfied.
3609 // Therefore, do not need to call "canReserveResources" anymore.
3610 ResourceTracker->reserveResources(MI);
3611 if (QII->isExtended(nvjMI))
3612 reserveResourcesForConstExt(nvjMI);
3614 // Here, we are sure that "reserveResources" would succeed.
3615 ResourceTracker->reserveResources(nvjMI);
3616 CurrentPacketMIs.push_back(MI);
3617 CurrentPacketMIs.push_back(nvjMI);
3619 if ( QII->isExtended(MI)
3620 && ( !tryAllocateResourcesForConstExt(MI)
3621 || !ResourceTracker->canReserveResources(MI)))
3624 // Check if the instruction was promoted to a dot-new. If so, demote it
3625 // back into a dot-old
3626 if (PromotedToDotNew) {
3629 reserveResourcesForConstExt(MI);
3631 // In case that "MI" is not an extended insn,
3632 // the resource availability has already been checked.
3633 ResourceTracker->reserveResources(MI);
3634 CurrentPacketMIs.push_back(MI);
3639 //===----------------------------------------------------------------------===//
3640 // Public Constructor Functions
3641 //===----------------------------------------------------------------------===//
3643 FunctionPass *llvm::createHexagonPacketizer() {
3644 return new HexagonPacketizer();