1 //===- HexagonInstPrinter.cpp - Convert Hexagon MCInst to assembly syntax -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an Hexagon MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonAsmPrinter.h"
16 #include "HexagonInstPrinter.h"
17 #include "MCTargetDesc/HexagonMCInst.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/Support/raw_ostream.h"
26 #define DEBUG_TYPE "asm-printer"
28 #define GET_INSTRUCTION_NAME
29 #include "HexagonGenAsmWriter.inc"
31 const char HexagonInstPrinter::PacketPadding = '\t';
32 // Return the minimum value that a constant extendable operand can have
33 // without being extended.
34 static int getMinValue(uint64_t TSFlags) {
36 (TSFlags >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
38 (TSFlags >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
41 return -1U << (bits - 1);
46 // Return the maximum value that a constant extendable operand can have
47 // without being extended.
48 static int getMaxValue(uint64_t TSFlags) {
50 (TSFlags >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
52 (TSFlags >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
55 return ~(-1U << (bits - 1));
57 return ~(-1U << bits);
60 // Return true if the instruction must be extended.
61 static bool isExtended(uint64_t TSFlags) {
62 return (TSFlags >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
65 // Return true if the instruction may be extended based on the operand value.
66 static bool isExtendable(uint64_t TSFlags) {
67 return (TSFlags >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
70 StringRef HexagonInstPrinter::getOpcodeName(unsigned Opcode) const {
71 return MII.getName(Opcode);
74 StringRef HexagonInstPrinter::getRegName(unsigned RegNo) const {
75 return getRegisterName(RegNo);
78 void HexagonInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
80 printInst((const HexagonMCInst*)(MI), O, Annot);
83 void HexagonInstPrinter::printInst(const HexagonMCInst *MI, raw_ostream &O,
85 const char startPacket = '{',
87 // TODO: add outer HW loop when it's supported too.
88 if (MI->getOpcode() == Hexagon::ENDLOOP0) {
89 // Ending a harware loop is different from ending an regular packet.
90 assert(MI->isPacketEnd() && "Loop-end must also end the packet");
92 if (MI->isPacketStart()) {
93 // There must be a packet to end a loop.
94 // FIXME: when shuffling is always run, this shouldn't be needed.
98 Nop.setOpcode (Hexagon::NOP);
99 Nop.setPacketStart (MI->isPacketStart());
100 printInst (&Nop, O, NoAnnot);
104 if (MI->isPacketEnd())
105 O << PacketPadding << endPacket;
107 printInstruction(MI, O);
110 // Prefix the insn opening the packet.
111 if (MI->isPacketStart())
112 O << PacketPadding << startPacket << '\n';
114 printInstruction(MI, O);
116 // Suffix the insn closing the packet.
117 if (MI->isPacketEnd())
118 // Suffix the packet in a new line always, since the GNU assembler has
119 // issues with a closing brace on the same line as CONST{32,64}.
120 O << '\n' << PacketPadding << endPacket;
123 printAnnotation(O, Annot);
126 void HexagonInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
127 raw_ostream &O) const {
128 const MCOperand& MO = MI->getOperand(OpNo);
131 O << getRegisterName(MO.getReg());
132 } else if(MO.isExpr()) {
134 } else if(MO.isImm()) {
135 printImmOperand(MI, OpNo, O);
137 llvm_unreachable("Unknown operand");
141 void HexagonInstPrinter::printImmOperand(const MCInst *MI, unsigned OpNo,
142 raw_ostream &O) const {
143 const MCOperand& MO = MI->getOperand(OpNo);
147 } else if(MO.isImm()) {
148 O << MI->getOperand(OpNo).getImm();
150 llvm_unreachable("Unknown operand");
154 void HexagonInstPrinter::printExtOperand(const MCInst *MI, unsigned OpNo,
155 raw_ostream &O) const {
156 const MCOperand &MO = MI->getOperand(OpNo);
157 const MCInstrDesc &MII = getMII().get(MI->getOpcode());
159 assert((isExtendable(MII.TSFlags) || isExtended(MII.TSFlags)) &&
160 "Expecting an extendable operand");
162 if (MO.isExpr() || isExtended(MII.TSFlags)) {
164 } else if (MO.isImm()) {
165 int ImmValue = MO.getImm();
166 if (ImmValue < getMinValue(MII.TSFlags) ||
167 ImmValue > getMaxValue(MII.TSFlags))
170 printOperand(MI, OpNo, O);
173 void HexagonInstPrinter::printUnsignedImmOperand(const MCInst *MI,
174 unsigned OpNo, raw_ostream &O) const {
175 O << MI->getOperand(OpNo).getImm();
178 void HexagonInstPrinter::printNegImmOperand(const MCInst *MI, unsigned OpNo,
179 raw_ostream &O) const {
180 O << -MI->getOperand(OpNo).getImm();
183 void HexagonInstPrinter::printNOneImmOperand(const MCInst *MI, unsigned OpNo,
184 raw_ostream &O) const {
188 void HexagonInstPrinter::printMEMriOperand(const MCInst *MI, unsigned OpNo,
189 raw_ostream &O) const {
190 const MCOperand& MO0 = MI->getOperand(OpNo);
191 const MCOperand& MO1 = MI->getOperand(OpNo + 1);
193 O << getRegisterName(MO0.getReg());
194 O << " + #" << MO1.getImm();
197 void HexagonInstPrinter::printFrameIndexOperand(const MCInst *MI, unsigned OpNo,
198 raw_ostream &O) const {
199 const MCOperand& MO0 = MI->getOperand(OpNo);
200 const MCOperand& MO1 = MI->getOperand(OpNo + 1);
202 O << getRegisterName(MO0.getReg()) << ", #" << MO1.getImm();
205 void HexagonInstPrinter::printGlobalOperand(const MCInst *MI, unsigned OpNo,
206 raw_ostream &O) const {
207 assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");
209 printOperand(MI, OpNo, O);
212 void HexagonInstPrinter::printJumpTable(const MCInst *MI, unsigned OpNo,
213 raw_ostream &O) const {
214 assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");
216 printOperand(MI, OpNo, O);
219 void HexagonInstPrinter::printConstantPool(const MCInst *MI, unsigned OpNo,
220 raw_ostream &O) const {
221 assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");
223 printOperand(MI, OpNo, O);
226 void HexagonInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
227 raw_ostream &O) const {
228 // Branches can take an immediate operand. This is used by the branch
229 // selection pass to print $+8, an eight byte displacement from the PC.
230 llvm_unreachable("Unknown branch operand.");
233 void HexagonInstPrinter::printCallOperand(const MCInst *MI, unsigned OpNo,
234 raw_ostream &O) const {
237 void HexagonInstPrinter::printAbsAddrOperand(const MCInst *MI, unsigned OpNo,
238 raw_ostream &O) const {
241 void HexagonInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
242 raw_ostream &O) const {
245 void HexagonInstPrinter::printSymbol(const MCInst *MI, unsigned OpNo,
246 raw_ostream &O, bool hi) const {
247 assert(MI->getOperand(OpNo).isImm() && "Unknown symbol operand");
249 O << '#' << (hi ? "HI" : "LO") << "(#";
250 printOperand(MI, OpNo, O);