1 //===-- HexagonAsmBackend.cpp - Hexagon Assembler Backend -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "HexagonFixupKinds.h"
12 #include "HexagonMCTargetDesc.h"
13 #include "MCTargetDesc/HexagonBaseInfo.h"
14 #include "MCTargetDesc/HexagonMCInstrInfo.h"
15 #include "llvm/MC/MCAsmBackend.h"
16 #include "llvm/MC/MCAssembler.h"
17 #include "llvm/MC/MCELFObjectWriter.h"
18 #include "llvm/MC/MCFixupKindInfo.h"
19 #include "llvm/Support/TargetRegistry.h"
22 using namespace Hexagon;
26 class HexagonAsmBackend : public MCAsmBackend {
29 mutable uint64_t relaxedCnt;
30 std::unique_ptr <MCInstrInfo> MCII;
31 std::unique_ptr <MCInst *> RelaxTarget;
33 HexagonAsmBackend(Target const &T, uint8_t OSABI, StringRef CPU) :
34 MCII (T.createMCInstrInfo()), RelaxTarget(new MCInst *){}
36 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
37 return createHexagonELFObjectWriter(OS, OSABI, CPU);
40 unsigned getNumFixupKinds() const override {
41 return Hexagon::NumTargetFixupKinds;
44 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
45 const static MCFixupKindInfo Infos[Hexagon::NumTargetFixupKinds] = {
46 // This table *must* be in same the order of fixup_* kinds in
47 // HexagonFixupKinds.h.
49 // namei offset bits flags
50 {"fixup_Hexagon_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
51 {"fixup_Hexagon_B15_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
52 {"fixup_Hexagon_B7_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
53 {"fixup_Hexagon_LO16", 0, 32, 0},
54 {"fixup_Hexagon_HI16", 0, 32, 0},
55 {"fixup_Hexagon_32", 0, 32, 0},
56 {"fixup_Hexagon_16", 0, 32, 0},
57 {"fixup_Hexagon_8", 0, 32, 0},
58 {"fixup_Hexagon_GPREL16_0", 0, 32, 0},
59 {"fixup_Hexagon_GPREL16_1", 0, 32, 0},
60 {"fixup_Hexagon_GPREL16_2", 0, 32, 0},
61 {"fixup_Hexagon_GPREL16_3", 0, 32, 0},
62 {"fixup_Hexagon_HL16", 0, 32, 0},
63 {"fixup_Hexagon_B13_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
64 {"fixup_Hexagon_B9_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
65 {"fixup_Hexagon_B32_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
66 {"fixup_Hexagon_32_6_X", 0, 32, 0},
67 {"fixup_Hexagon_B22_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
68 {"fixup_Hexagon_B15_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
69 {"fixup_Hexagon_B13_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
70 {"fixup_Hexagon_B9_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
71 {"fixup_Hexagon_B7_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
72 {"fixup_Hexagon_16_X", 0, 32, 0},
73 {"fixup_Hexagon_12_X", 0, 32, 0},
74 {"fixup_Hexagon_11_X", 0, 32, 0},
75 {"fixup_Hexagon_10_X", 0, 32, 0},
76 {"fixup_Hexagon_9_X", 0, 32, 0},
77 {"fixup_Hexagon_8_X", 0, 32, 0},
78 {"fixup_Hexagon_7_X", 0, 32, 0},
79 {"fixup_Hexagon_6_X", 0, 32, 0},
80 {"fixup_Hexagon_32_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
81 {"fixup_Hexagon_COPY", 0, 32, 0},
82 {"fixup_Hexagon_GLOB_DAT", 0, 32, 0},
83 {"fixup_Hexagon_JMP_SLOT", 0, 32, 0},
84 {"fixup_Hexagon_RELATIVE", 0, 32, 0},
85 {"fixup_Hexagon_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
86 {"fixup_Hexagon_GOTREL_LO16", 0, 32, 0},
87 {"fixup_Hexagon_GOTREL_HI16", 0, 32, 0},
88 {"fixup_Hexagon_GOTREL_32", 0, 32, 0},
89 {"fixup_Hexagon_GOT_LO16", 0, 32, 0},
90 {"fixup_Hexagon_GOT_HI16", 0, 32, 0},
91 {"fixup_Hexagon_GOT_32", 0, 32, 0},
92 {"fixup_Hexagon_GOT_16", 0, 32, 0},
93 {"fixup_Hexagon_DTPMOD_32", 0, 32, 0},
94 {"fixup_Hexagon_DTPREL_LO16", 0, 32, 0},
95 {"fixup_Hexagon_DTPREL_HI16", 0, 32, 0},
96 {"fixup_Hexagon_DTPREL_32", 0, 32, 0},
97 {"fixup_Hexagon_DTPREL_16", 0, 32, 0},
98 {"fixup_Hexagon_GD_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
99 {"fixup_Hexagon_LD_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
100 {"fixup_Hexagon_GD_GOT_LO16", 0, 32, 0},
101 {"fixup_Hexagon_GD_GOT_HI16", 0, 32, 0},
102 {"fixup_Hexagon_GD_GOT_32", 0, 32, 0},
103 {"fixup_Hexagon_GD_GOT_16", 0, 32, 0},
104 {"fixup_Hexagon_LD_GOT_LO16", 0, 32, 0},
105 {"fixup_Hexagon_LD_GOT_HI16", 0, 32, 0},
106 {"fixup_Hexagon_LD_GOT_32", 0, 32, 0},
107 {"fixup_Hexagon_LD_GOT_16", 0, 32, 0},
108 {"fixup_Hexagon_IE_LO16", 0, 32, 0},
109 {"fixup_Hexagon_IE_HI16", 0, 32, 0},
110 {"fixup_Hexagon_IE_32", 0, 32, 0},
111 {"fixup_Hexagon_IE_16", 0, 32, 0},
112 {"fixup_Hexagon_IE_GOT_LO16", 0, 32, 0},
113 {"fixup_Hexagon_IE_GOT_HI16", 0, 32, 0},
114 {"fixup_Hexagon_IE_GOT_32", 0, 32, 0},
115 {"fixup_Hexagon_IE_GOT_16", 0, 32, 0},
116 {"fixup_Hexagon_TPREL_LO16", 0, 32, 0},
117 {"fixup_Hexagon_TPREL_HI16", 0, 32, 0},
118 {"fixup_Hexagon_TPREL_32", 0, 32, 0},
119 {"fixup_Hexagon_TPREL_16", 0, 32, 0},
120 {"fixup_Hexagon_6_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
121 {"fixup_Hexagon_GOTREL_32_6_X", 0, 32, 0},
122 {"fixup_Hexagon_GOTREL_16_X", 0, 32, 0},
123 {"fixup_Hexagon_GOTREL_11_X", 0, 32, 0},
124 {"fixup_Hexagon_GOT_32_6_X", 0, 32, 0},
125 {"fixup_Hexagon_GOT_16_X", 0, 32, 0},
126 {"fixup_Hexagon_GOT_11_X", 0, 32, 0},
127 {"fixup_Hexagon_DTPREL_32_6_X", 0, 32, 0},
128 {"fixup_Hexagon_DTPREL_16_X", 0, 32, 0},
129 {"fixup_Hexagon_DTPREL_11_X", 0, 32, 0},
130 {"fixup_Hexagon_GD_GOT_32_6_X", 0, 32, 0},
131 {"fixup_Hexagon_GD_GOT_16_X", 0, 32, 0},
132 {"fixup_Hexagon_GD_GOT_11_X", 0, 32, 0},
133 {"fixup_Hexagon_LD_GOT_32_6_X", 0, 32, 0},
134 {"fixup_Hexagon_LD_GOT_16_X", 0, 32, 0},
135 {"fixup_Hexagon_LD_GOT_11_X", 0, 32, 0},
136 {"fixup_Hexagon_IE_32_6_X", 0, 32, 0},
137 {"fixup_Hexagon_IE_16_X", 0, 32, 0},
138 {"fixup_Hexagon_IE_GOT_32_6_X", 0, 32, 0},
139 {"fixup_Hexagon_IE_GOT_16_X", 0, 32, 0},
140 {"fixup_Hexagon_IE_GOT_11_X", 0, 32, 0},
141 {"fixup_Hexagon_TPREL_32_6_X", 0, 32, 0},
142 {"fixup_Hexagon_TPREL_16_X", 0, 32, 0},
143 {"fixup_Hexagon_TPREL_11_X", 0, 32, 0}};
145 if (Kind < FirstTargetFixupKind) {
146 return MCAsmBackend::getFixupKindInfo(Kind);
149 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
151 return Infos[Kind - FirstTargetFixupKind];
154 void applyFixup(MCFixup const & /*Fixup*/, char * /*Data*/,
155 unsigned /*DataSize*/, uint64_t /*Value*/,
156 bool /*IsPCRel*/) const override {
160 bool isInstRelaxable(MCInst const &HMI) const {
161 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI);
162 bool Relaxable = false;
163 // Branches and loop-setup insns are handled as necessary by relaxation.
164 if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ ||
165 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNV &&
167 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCR &&
168 HMI.getOpcode() != Hexagon::C4_addipc))
169 if (HexagonMCInstrInfo::isExtendable(*MCII, HMI))
175 /// MayNeedRelaxation - Check whether the given instruction may need
178 /// \param Inst - The instruction to test.
179 bool mayNeedRelaxation(MCInst const &Inst) const override {
180 assert(HexagonMCInstrInfo::isBundle(Inst));
181 bool PreviousIsExtender = false;
182 for (auto const &I : HexagonMCInstrInfo::bundleInstructions(Inst)) {
183 auto const &Inst = *I.getInst();
184 if (!PreviousIsExtender) {
185 if (isInstRelaxable(Inst))
188 PreviousIsExtender = HexagonMCInstrInfo::isImmext(Inst);
193 /// fixupNeedsRelaxation - Target specific predicate for whether a given
194 /// fixup requires the associated instruction to be relaxed.
195 bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved,
197 const MCRelaxableFragment *DF,
198 const MCAsmLayout &Layout) const override {
199 MCInst const &MCB = DF->getInst();
200 assert(HexagonMCInstrInfo::isBundle(MCB));
202 *RelaxTarget = nullptr;
203 MCInst &MCI = const_cast<MCInst &>(HexagonMCInstrInfo::instruction(
204 MCB, Fixup.getOffset() / HEXAGON_INSTR_SIZE));
205 // If we cannot resolve the fixup value, it requires relaxation.
207 switch ((unsigned)Fixup.getKind()) {
208 case fixup_Hexagon_B22_PCREL:
209 // GetFixupCount assumes B22 won't relax
214 case fixup_Hexagon_B13_PCREL:
215 case fixup_Hexagon_B15_PCREL:
216 case fixup_Hexagon_B9_PCREL:
217 case fixup_Hexagon_B7_PCREL: {
218 if (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_SIZE) {
229 bool Relaxable = isInstRelaxable(MCI);
230 if (Relaxable == false)
233 MCFixupKind Kind = Fixup.getKind();
234 int64_t sValue = Value;
237 switch ((unsigned)Kind) {
238 case fixup_Hexagon_B7_PCREL:
241 case fixup_Hexagon_B9_PCREL:
244 case fixup_Hexagon_B15_PCREL:
247 case fixup_Hexagon_B22_PCREL:
251 maxValue = INT64_MAX;
255 bool isFarAway = -maxValue > sValue || sValue > maxValue - 1;
258 if (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_SIZE) {
268 /// Simple predicate for targets where !Resolved implies requiring relaxation
269 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
270 const MCRelaxableFragment *DF,
271 const MCAsmLayout &Layout) const override {
272 llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced");
275 void relaxInstruction(MCInst const & /*Inst*/,
276 MCInst & /*Res*/) const override {
277 llvm_unreachable("relaxInstruction() unimplemented");
280 bool writeNopData(uint64_t /*Count*/,
281 MCObjectWriter * /*OW*/) const override {
285 } // end anonymous namespace
288 MCAsmBackend *createHexagonAsmBackend(Target const &T,
289 MCRegisterInfo const & /*MRI*/,
290 StringRef TT, StringRef CPU) {
291 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS());
292 return new HexagonAsmBackend(T, OSABI, CPU);