1 //===-- HexagonAsmBackend.cpp - Hexagon Assembler Backend -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "HexagonFixupKinds.h"
12 #include "HexagonMCTargetDesc.h"
13 #include "MCTargetDesc/HexagonBaseInfo.h"
14 #include "MCTargetDesc/HexagonMCInstrInfo.h"
15 #include "llvm/MC/MCAsmBackend.h"
16 #include "llvm/MC/MCAssembler.h"
17 #include "llvm/MC/MCELFObjectWriter.h"
20 using namespace Hexagon;
24 class HexagonAsmBackend : public MCAsmBackend {
25 mutable uint64_t relaxedCnt;
26 std::unique_ptr <MCInstrInfo> MCII;
27 std::unique_ptr <MCInst *> RelaxTarget;
29 HexagonAsmBackend(Target const & /*T*/) :
30 MCII (createHexagonMCInstrInfo()), RelaxTarget(new MCInst *){}
32 unsigned getNumFixupKinds() const override { return 0; }
34 void applyFixup(MCFixup const & /*Fixup*/, char * /*Data*/,
35 unsigned /*DataSize*/, uint64_t /*Value*/,
36 bool /*IsPCRel*/) const override {
40 bool isInstRelaxable(MCInst const &HMI) const {
41 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI);
42 bool Relaxable = false;
43 // Branches and loop-setup insns are handled as necessary by relaxation.
44 if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ ||
45 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNV &&
47 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCR &&
48 HMI.getOpcode() != Hexagon::C4_addipc))
49 if (HexagonMCInstrInfo::isExtendable(*MCII, HMI))
55 /// MayNeedRelaxation - Check whether the given instruction may need
58 /// \param Inst - The instruction to test.
59 bool mayNeedRelaxation(MCInst const &Inst) const override {
60 assert(HexagonMCInstrInfo::isBundle(Inst));
61 bool PreviousIsExtender = false;
62 for (auto const &I : HexagonMCInstrInfo::bundleInstructions(Inst)) {
63 auto const &Inst = *I.getInst();
64 if (!PreviousIsExtender) {
65 if (isInstRelaxable(Inst))
68 PreviousIsExtender = HexagonMCInstrInfo::isImmext(Inst);
73 /// fixupNeedsRelaxation - Target specific predicate for whether a given
74 /// fixup requires the associated instruction to be relaxed.
75 bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved,
77 const MCRelaxableFragment *DF,
78 const MCAsmLayout &Layout) const override {
79 MCInst const &MCB = DF->getInst();
80 assert(HexagonMCInstrInfo::isBundle(MCB));
82 *RelaxTarget = nullptr;
83 MCInst &MCI = const_cast<MCInst &>(HexagonMCInstrInfo::instruction(
84 MCB, Fixup.getOffset() / HEXAGON_INSTR_SIZE));
85 // If we cannot resolve the fixup value, it requires relaxation.
87 switch ((unsigned)Fixup.getKind()) {
88 case fixup_Hexagon_B22_PCREL:
89 // GetFixupCount assumes B22 won't relax
94 case fixup_Hexagon_B13_PCREL:
95 case fixup_Hexagon_B15_PCREL:
96 case fixup_Hexagon_B9_PCREL:
97 case fixup_Hexagon_B7_PCREL: {
98 if (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_SIZE) {
109 bool Relaxable = isInstRelaxable(MCI);
110 if (Relaxable == false)
113 MCFixupKind Kind = Fixup.getKind();
114 int64_t sValue = Value;
117 switch ((unsigned)Kind) {
118 case fixup_Hexagon_B7_PCREL:
121 case fixup_Hexagon_B9_PCREL:
124 case fixup_Hexagon_B15_PCREL:
127 case fixup_Hexagon_B22_PCREL:
131 maxValue = INT64_MAX;
135 bool isFarAway = -maxValue > sValue || sValue > maxValue - 1;
138 if (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_SIZE) {
148 /// Simple predicate for targets where !Resolved implies requiring relaxation
149 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
150 const MCRelaxableFragment *DF,
151 const MCAsmLayout &Layout) const override {
152 llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced");
155 void relaxInstruction(MCInst const & /*Inst*/,
156 MCInst & /*Res*/) const override {
157 llvm_unreachable("relaxInstruction() unimplemented");
160 bool writeNopData(uint64_t /*Count*/,
161 MCObjectWriter * /*OW*/) const override {
165 } // end anonymous namespace
168 class ELFHexagonAsmBackend : public HexagonAsmBackend {
172 ELFHexagonAsmBackend(Target const &T, uint8_t OSABI)
173 : HexagonAsmBackend(T), OSABI(OSABI) {}
175 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
176 StringRef CPU("HexagonV4");
177 return createHexagonELFObjectWriter(OS, OSABI, CPU);
180 } // end anonymous namespace
183 MCAsmBackend *createHexagonAsmBackend(Target const &T,
184 MCRegisterInfo const & /*MRI*/,
185 StringRef TT, StringRef /*CPU*/) {
186 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS());
187 return new ELFHexagonAsmBackend(T, OSABI);