1 //===-- HexagonBaseInfo.h - Top level definitions for Hexagon --*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains small standalone helper functions and enum definitions for
11 // the Hexagon target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
15 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
18 #define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONBASEINFO_H
20 #include "HexagonMCTargetDesc.h"
21 #include "llvm/Support/ErrorHandling.h"
26 /// HexagonII - This namespace holds all of the target specific flags that
27 /// instruction info tracks.
30 // *** The code below must match HexagonInstrFormat*.td *** //
33 // *** Must match HexagonInstrFormat*.td ***
47 TypePREFIX = 30, // Such as extenders.
48 TypeENDLOOP = 31 // Such as end of a HW loop.
65 NoAddrMode = 0, // No addressing mode
66 Absolute = 1, // Absolute addressing mode
67 AbsoluteSet = 2, // Absolute set addressing mode
68 BaseImmOffset = 3, // Indirect with offset
69 BaseLongOffset = 4, // Indirect with long offset
70 BaseRegOffset = 5, // Indirect with register offset
71 PostInc = 6 // Post increment addressing mode
74 enum class MemAccessSize {
75 NoMemAccess = 0, // Not a memory acces instruction.
76 ByteAccess = 1, // Byte access instruction (memb).
77 HalfWordAccess = 2, // Half word access instruction (memh).
78 WordAccess = 3, // Word access instruction (memw).
79 DoubleWordAccess = 4 // Double word access instruction (memd)
82 // MCInstrDesc TSFlags
83 // *** Must match HexagonInstrFormat*.td ***
85 // This 5-bit field describes the insn type.
92 // Packed only with A or X-type instructions.
95 // Only A-type instruction in first slot or nothing.
99 // Predicated instructions.
101 PredicatedMask = 0x1,
102 PredicatedFalsePos = 9,
103 PredicatedFalseMask = 0x1,
104 PredicatedNewPos = 10,
105 PredicatedNewMask = 0x1,
106 PredicateLatePos = 11,
107 PredicateLateMask = 0x1,
109 // New-Value consumer instructions.
112 // New-Value producer instructions.
114 hasNewValueMask = 0x1,
115 // Which operand consumes or produces a new value.
117 NewValueOpMask = 0x7,
118 // Stores that can become new-value stores.
120 mayNVStoreMask = 0x1,
121 // New-value store instructions.
124 // Loads that can become current-value loads.
127 // Current-value load instructions.
133 ExtendableMask = 0x1,
134 // Insns must be extended.
137 // Which operand may be extended.
138 ExtendableOpPos = 23,
139 ExtendableOpMask = 0x7,
140 // Signed or unsigned range.
141 ExtentSignedPos = 26,
142 ExtentSignedMask = 0x1,
143 // Number of bits of range before extending operand.
145 ExtentBitsMask = 0x1f,
146 // Alignment power-of-two before extending operand.
148 ExtentAlignMask = 0x3,
151 validSubTargetPos = 34,
152 validSubTargetMask = 0xf,
154 // Addressing mode for load/store instructions.
157 // Access size for load/store instructions.
158 MemAccessSizePos = 43,
159 MemAccesSizeMask = 0x7,
161 // Branch predicted taken.
165 // Floating-point instructions.
170 // *** The code above must match HexagonInstrFormat*.td *** //
172 // Hexagon specific MO operand flag mask.
173 enum HexagonMOTargetFlagVal {
174 //===------------------------------------------------------------------===//
175 // Hexagon Specific MachineOperand flags.
178 HMOTF_ConstExtended = 1,
180 /// MO_PCREL - On a symbol operand, indicates a PC-relative relocation
181 /// Used for computing a global address for PIC compilations
184 /// MO_GOT - Indicates a GOT-relative relocation
187 // Low or high part of a symbol.
190 // Offset from the base of the SDA.
194 // Hexagon Sub-instruction classes.
195 enum SubInstructionGroup {
206 INST_PARSE_MASK = 0x0000c000,
207 INST_PARSE_PACKET_END = 0x0000c000,
208 INST_PARSE_LOOP_END = 0x00008000,
209 INST_PARSE_NOT_END = 0x00004000,
210 INST_PARSE_DUPLEX = 0x00000000,
211 INST_PARSE_EXTENDER = 0x00000000
214 } // End namespace HexagonII.
216 } // End namespace llvm.