1 //===-- HexagonBaseInfo.h - Top level definitions for Hexagon --*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains small standalone helper functions and enum definitions for
11 // the Hexagon target useful for the compiler back-end and the MC libraries.
12 // As such, it deliberately does not include references to LLVM core
13 // code gen types, passes, etc..
15 //===----------------------------------------------------------------------===//
17 #ifndef HEXAGONBASEINFO_H
18 #define HEXAGONBASEINFO_H
20 #include "HexagonMCTargetDesc.h"
21 #include "llvm/Support/ErrorHandling.h"
25 /// HexagonII - This namespace holds all of the target specific flags that
26 /// instruction info tracks.
29 // *** The code below must match HexagonInstrFormat*.td *** //
32 // *** Must match HexagonInstrFormat*.td ***
45 TypePREFIX = 30, // Such as extenders.
46 TypeENDLOOP = 31 // Such as end of a HW loop.
63 NoAddrMode = 0, // No addressing mode
64 Absolute = 1, // Absolute addressing mode
65 AbsoluteSet = 2, // Absolute set addressing mode
66 BaseImmOffset = 3, // Indirect with offset
67 BaseLongOffset = 4, // Indirect with long offset
68 BaseRegOffset = 5, // Indirect with register offset
69 PostInc = 6 // Post increment addressing mode
73 NoMemAccess = 0, // Not a memory acces instruction.
74 ByteAccess = 1, // Byte access instruction (memb).
75 HalfWordAccess = 2, // Half word access instruction (memh).
76 WordAccess = 3, // Word access instruction (memw).
77 DoubleWordAccess = 4 // Double word access instruction (memd)
80 // MCInstrDesc TSFlags
81 // *** Must match HexagonInstrFormat*.td ***
83 // This 5-bit field describes the insn type.
90 // Packed only with A or X-type instructions.
93 // Only A-type instruction in first slot or nothing.
97 // Predicated instructions.
100 PredicatedFalsePos = 9,
101 PredicatedFalseMask = 0x1,
102 PredicatedNewPos = 10,
103 PredicatedNewMask = 0x1,
104 PredicateLatePos = 11,
105 PredicateLateMask = 0x1,
107 // New-Value consumer instructions.
110 // New-Value producer instructions.
112 hasNewValueMask = 0x1,
113 // Which operand consumes or produces a new value.
115 NewValueOpMask = 0x7,
116 // Stores that can become new-value stores.
118 mayNVStoreMask = 0x1,
119 // New-value store instructions.
122 // Loads that can become current-value loads.
125 // Current-value load instructions.
131 ExtendableMask = 0x1,
132 // Insns must be extended.
135 // Which operand may be extended.
136 ExtendableOpPos = 23,
137 ExtendableOpMask = 0x7,
138 // Signed or unsigned range.
139 ExtentSignedPos = 26,
140 ExtentSignedMask = 0x1,
141 // Number of bits of range before extending operand.
143 ExtentBitsMask = 0x1f,
144 // Alignment power-of-two before extending operand.
146 ExtentAlignMask = 0x3,
149 validSubTargetPos = 34,
150 validSubTargetMask = 0xf,
152 // Addressing mode for load/store instructions.
155 // Access size for load/store instructions.
156 MemAccessSizePos = 43,
157 MemAccesSizeMask = 0x7,
159 // Branch predicted taken.
163 // Floating-point instructions.
168 // *** The code above must match HexagonInstrFormat*.td *** //
170 // Hexagon specific MO operand flag mask.
171 enum HexagonMOTargetFlagVal {
172 //===------------------------------------------------------------------===//
173 // Hexagon Specific MachineOperand flags.
176 HMOTF_ConstExtended = 1,
178 /// MO_PCREL - On a symbol operand, indicates a PC-relative relocation
179 /// Used for computing a global address for PIC compilations
182 /// MO_GOT - Indicates a GOT-relative relocation
185 // Low or high part of a symbol.
188 // Offset from the base of the SDA.
192 } // End namespace HexagonII.
194 } // End namespace llvm.