1 //===- HexagonInstPrinter.cpp - Convert Hexagon MCInst to assembly syntax -===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an Hexagon MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #include "HexagonAsmPrinter.h"
16 #include "HexagonInstPrinter.h"
17 #include "MCTargetDesc/HexagonMCInstrInfo.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/Support/raw_ostream.h"
26 #define DEBUG_TYPE "asm-printer"
28 #define GET_INSTRUCTION_NAME
29 #include "HexagonGenAsmWriter.inc"
31 const char HexagonInstPrinter::PacketPadding = '\t';
32 // Return the minimum value that a constant extendable operand can have
33 // without being extended.
34 static int getMinValue(uint64_t TSFlags) {
36 (TSFlags >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
38 (TSFlags >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
41 return -1U << (bits - 1);
46 // Return the maximum value that a constant extendable operand can have
47 // without being extended.
48 static int getMaxValue(uint64_t TSFlags) {
50 (TSFlags >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
52 (TSFlags >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
55 return ~(-1U << (bits - 1));
57 return ~(-1U << bits);
60 // Return true if the instruction must be extended.
61 static bool isExtended(uint64_t TSFlags) {
62 return (TSFlags >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
65 // Currently just used in an assert statement
66 static bool isExtendable(uint64_t TSFlags) LLVM_ATTRIBUTE_UNUSED;
67 // Return true if the instruction may be extended based on the operand value.
68 static bool isExtendable(uint64_t TSFlags) {
69 return (TSFlags >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
72 StringRef HexagonInstPrinter::getOpcodeName(unsigned Opcode) const {
73 return MII.getName(Opcode);
76 StringRef HexagonInstPrinter::getRegName(unsigned RegNo) const {
77 return getRegisterName(RegNo);
80 void HexagonInstPrinter::printInst(MCInst const *MI, raw_ostream &O,
82 const char startPacket = '{',
84 // TODO: add outer HW loop when it's supported too.
85 if (MI->getOpcode() == Hexagon::ENDLOOP0) {
86 // Ending a harware loop is different from ending an regular packet.
87 assert(HexagonMCInstrInfo::isPacketEnd(*MI) && "Loop-end must also end the packet");
89 if (HexagonMCInstrInfo::isPacketBegin(*MI)) {
90 // There must be a packet to end a loop.
91 // FIXME: when shuffling is always run, this shouldn't be needed.
95 Nop.setOpcode (Hexagon::A2_nop);
96 HexagonMCInstrInfo::setPacketBegin (Nop, HexagonMCInstrInfo::isPacketBegin(*MI));
97 printInst (&Nop, O, NoAnnot);
101 if (HexagonMCInstrInfo::isPacketEnd(*MI))
102 O << PacketPadding << endPacket;
104 printInstruction(MI, O);
107 // Prefix the insn opening the packet.
108 if (HexagonMCInstrInfo::isPacketBegin(*MI))
109 O << PacketPadding << startPacket << '\n';
111 printInstruction(MI, O);
113 // Suffix the insn closing the packet.
114 if (HexagonMCInstrInfo::isPacketEnd(*MI))
115 // Suffix the packet in a new line always, since the GNU assembler has
116 // issues with a closing brace on the same line as CONST{32,64}.
117 O << '\n' << PacketPadding << endPacket;
120 printAnnotation(O, Annot);
123 void HexagonInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
124 raw_ostream &O) const {
125 const MCOperand& MO = MI->getOperand(OpNo);
128 O << getRegisterName(MO.getReg());
129 } else if(MO.isExpr()) {
131 } else if(MO.isImm()) {
132 printImmOperand(MI, OpNo, O);
134 llvm_unreachable("Unknown operand");
138 void HexagonInstPrinter::printImmOperand(const MCInst *MI, unsigned OpNo,
139 raw_ostream &O) const {
140 const MCOperand& MO = MI->getOperand(OpNo);
144 } else if(MO.isImm()) {
145 O << MI->getOperand(OpNo).getImm();
147 llvm_unreachable("Unknown operand");
151 void HexagonInstPrinter::printExtOperand(const MCInst *MI, unsigned OpNo,
152 raw_ostream &O) const {
153 const MCOperand &MO = MI->getOperand(OpNo);
154 const MCInstrDesc &MII = getMII().get(MI->getOpcode());
156 assert((isExtendable(MII.TSFlags) || isExtended(MII.TSFlags)) &&
157 "Expecting an extendable operand");
159 if (MO.isExpr() || isExtended(MII.TSFlags)) {
161 } else if (MO.isImm()) {
162 int ImmValue = MO.getImm();
163 if (ImmValue < getMinValue(MII.TSFlags) ||
164 ImmValue > getMaxValue(MII.TSFlags))
167 printOperand(MI, OpNo, O);
170 void HexagonInstPrinter::printUnsignedImmOperand(const MCInst *MI,
171 unsigned OpNo, raw_ostream &O) const {
172 O << MI->getOperand(OpNo).getImm();
175 void HexagonInstPrinter::printNegImmOperand(const MCInst *MI, unsigned OpNo,
176 raw_ostream &O) const {
177 O << -MI->getOperand(OpNo).getImm();
180 void HexagonInstPrinter::printNOneImmOperand(const MCInst *MI, unsigned OpNo,
181 raw_ostream &O) const {
185 void HexagonInstPrinter::printMEMriOperand(const MCInst *MI, unsigned OpNo,
186 raw_ostream &O) const {
187 const MCOperand& MO0 = MI->getOperand(OpNo);
188 const MCOperand& MO1 = MI->getOperand(OpNo + 1);
190 O << getRegisterName(MO0.getReg());
191 O << " + #" << MO1.getImm();
194 void HexagonInstPrinter::printFrameIndexOperand(const MCInst *MI, unsigned OpNo,
195 raw_ostream &O) const {
196 const MCOperand& MO0 = MI->getOperand(OpNo);
197 const MCOperand& MO1 = MI->getOperand(OpNo + 1);
199 O << getRegisterName(MO0.getReg()) << ", #" << MO1.getImm();
202 void HexagonInstPrinter::printGlobalOperand(const MCInst *MI, unsigned OpNo,
203 raw_ostream &O) const {
204 assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");
206 printOperand(MI, OpNo, O);
209 void HexagonInstPrinter::printJumpTable(const MCInst *MI, unsigned OpNo,
210 raw_ostream &O) const {
211 assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");
213 printOperand(MI, OpNo, O);
216 void HexagonInstPrinter::printConstantPool(const MCInst *MI, unsigned OpNo,
217 raw_ostream &O) const {
218 assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");
220 printOperand(MI, OpNo, O);
223 void HexagonInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,
224 raw_ostream &O) const {
225 // Branches can take an immediate operand. This is used by the branch
226 // selection pass to print $+8, an eight byte displacement from the PC.
227 llvm_unreachable("Unknown branch operand.");
230 void HexagonInstPrinter::printCallOperand(const MCInst *MI, unsigned OpNo,
231 raw_ostream &O) const {
234 void HexagonInstPrinter::printAbsAddrOperand(const MCInst *MI, unsigned OpNo,
235 raw_ostream &O) const {
238 void HexagonInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,
239 raw_ostream &O) const {
242 void HexagonInstPrinter::printSymbol(const MCInst *MI, unsigned OpNo,
243 raw_ostream &O, bool hi) const {
244 assert(MI->getOperand(OpNo).isImm() && "Unknown symbol operand");
246 O << '#' << (hi ? "HI" : "LO") << "(#";
247 printOperand(MI, OpNo, O);