1 //===-- IA64Bundling.cpp - IA-64 instruction bundling pass. ------------ --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Add stops where required to prevent read-after-write and write-after-write
11 // dependencies, for both registers and memory addresses. There are exceptions:
13 // - Compare instructions (cmp*, tbit, tnat, fcmp, frcpa) are OK with
14 // WAW dependencies so long as they all target p0, or are of parallel
17 // FIXME: bundling, for now, is left to the assembler.
18 // FIXME: this might be an appropriate place to translate between different
19 // instructions that do the same thing, if this helps bundling.
21 //===----------------------------------------------------------------------===//
23 #define DEBUG_TYPE "ia64-codegen"
25 #include "IA64InstrInfo.h"
26 #include "IA64TargetMachine.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/ADT/SetOperations.h"
30 #include "llvm/ADT/Statistic.h"
31 #include "llvm/Support/Debug.h"
35 STATISTIC(StopBitsAdded, "Number of stop bits added");
38 struct IA64BundlingPass : public MachineFunctionPass {
39 /// Target machine description which we query for reg. names, data
42 IA64TargetMachine &TM;
44 IA64BundlingPass(IA64TargetMachine &tm) : TM(tm) { }
46 virtual const char *getPassName() const {
47 return "IA64 (Itanium) Bundling Pass";
50 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
51 bool runOnMachineFunction(MachineFunction &F) {
53 for (MachineFunction::iterator FI = F.begin(), FE = F.end();
55 Changed |= runOnMachineBasicBlock(*FI);
59 // XXX: ugly global, but pending writes can cross basic blocks. Note that
60 // taken branches end instruction groups. So we only need to worry about
62 std::set<unsigned> PendingRegWrites;
64 } // end of anonymous namespace
66 /// createIA64BundlingPass - Returns a pass that adds STOP (;;) instructions
67 /// and arranges the result into bundles.
69 FunctionPass *llvm::createIA64BundlingPass(IA64TargetMachine &tm) {
70 return new IA64BundlingPass(tm);
73 /// runOnMachineBasicBlock - add stops and bundle this MBB.
75 bool IA64BundlingPass::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
78 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
79 MachineInstr *CurrentInsn = I++;
80 std::set<unsigned> CurrentReads, CurrentWrites, OrigWrites;
82 for(unsigned i=0; i < CurrentInsn->getNumOperands(); i++) {
83 MachineOperand &MO=CurrentInsn->getOperand(i);
85 if(MO.isUse()) { // TODO: exclude p0
86 CurrentReads.insert(MO.getReg());
88 if(MO.isDef()) { // TODO: exclude p0
89 CurrentWrites.insert(MO.getReg());
90 OrigWrites.insert(MO.getReg()); // FIXME: use a nondestructive
91 // set_intersect instead?
96 // CurrentReads/CurrentWrites contain info for the current instruction.
97 // Does it read or write any registers that are pending a write?
98 // (i.e. not separated by a stop)
99 set_intersect(CurrentReads, PendingRegWrites);
100 set_intersect(CurrentWrites, PendingRegWrites);
102 if(! (CurrentReads.empty() && CurrentWrites.empty()) ) {
103 // there is a conflict, insert a stop and reset PendingRegWrites
104 CurrentInsn = BuildMI(MBB, CurrentInsn,
105 TM.getInstrInfo()->get(IA64::STOP), 0);
106 PendingRegWrites=OrigWrites; // carry over current writes to next insn
107 Changed=true; StopBitsAdded++; // update stats
108 } else { // otherwise, track additional pending writes
109 set_union(PendingRegWrites, OrigWrites);
111 } // onto the next insn in the MBB