1 //===---- IA64ISelDAGToDAG.cpp - IA64 pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for IA64,
11 // converting a legalized dag to an IA64 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "ia64-codegen"
17 #include "IA64TargetMachine.h"
18 #include "IA64ISelLowering.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/Constants.h"
25 #include "llvm/GlobalValue.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
35 //===--------------------------------------------------------------------===//
36 /// IA64DAGToDAGISel - IA64 specific code to select IA64 machine
37 /// instructions for SelectionDAG operations.
39 class IA64DAGToDAGISel : public SelectionDAGISel {
40 IA64TargetLowering IA64Lowering;
41 unsigned GlobalBaseReg;
43 explicit IA64DAGToDAGISel(IA64TargetMachine &TM)
44 : SelectionDAGISel(IA64Lowering), IA64Lowering(*TM.getTargetLowering()) {}
46 virtual bool runOnFunction(Function &Fn) {
47 // Make sure we re-emit a set of the global base reg if necessary
49 return SelectionDAGISel::runOnFunction(Fn);
52 /// getI64Imm - Return a target constant with the specified value, of type
54 inline SDOperand getI64Imm(uint64_t Imm) {
55 return CurDAG->getTargetConstant(Imm, MVT::i64);
58 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
59 /// base register. Return the virtual register that holds this value.
60 // SDOperand getGlobalBaseReg(); TODO: hmm
62 // Select - Convert the specified operand from a target-independent to a
63 // target-specific node if it hasn't already been changed.
64 SDNode *Select(SDOperand N);
66 SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
67 unsigned OCHi, unsigned OCLo,
68 bool IsArithmetic = false,
70 SDNode *SelectBitfieldInsert(SDNode *N);
72 /// SelectCC - Select a comparison of the specified values with the
73 /// specified condition code, returning the CR# of the expression.
74 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
76 /// SelectAddr - Given the specified address, return the two operands for a
77 /// load/store instruction, and return true if it should be an indexed [r+r]
79 bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
81 /// InstructionSelect - This callback is invoked by
82 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
83 virtual void InstructionSelect(SelectionDAG &DAG);
85 virtual const char *getPassName() const {
86 return "IA64 (Itanium) DAG->DAG Instruction Selector";
89 // Include the pieces autogenerated from the target description.
90 #include "IA64GenDAGISel.inc"
93 SDNode *SelectDIV(SDOperand Op);
97 /// InstructionSelect - This callback is invoked by
98 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
99 void IA64DAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
102 // Select target instructions for the DAG.
103 DAG.setRoot(SelectRoot(DAG.getRoot()));
104 DAG.RemoveDeadNodes();
107 SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
109 SDOperand Chain = N->getOperand(0);
110 SDOperand Tmp1 = N->getOperand(0);
111 SDOperand Tmp2 = N->getOperand(1);
112 AddToISelQueue(Chain);
114 AddToISelQueue(Tmp1);
115 AddToISelQueue(Tmp2);
119 if(Tmp1.getValueType().isFloatingPoint())
122 bool isModulus=false; // is it a division or a modulus?
125 switch(N->getOpcode()) {
127 case ISD::SDIV: isModulus=false; isSigned=true; break;
128 case ISD::UDIV: isModulus=false; isSigned=false; break;
130 case ISD::SREM: isModulus=true; isSigned=true; break;
131 case ISD::UREM: isModulus=true; isSigned=false; break;
134 // TODO: check for integer divides by powers of 2 (or other simple patterns?)
136 SDOperand TmpPR, TmpPR2;
137 SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
138 SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
141 // we'll need copies of F0 and F1
142 SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
143 SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
145 // OK, emit some code:
148 // first, load the inputs into FP regs.
150 SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0);
151 Chain = TmpF1.getValue(1);
153 SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0);
154 Chain = TmpF2.getValue(1);
156 // next, convert the inputs to FP
159 SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0);
160 Chain = TmpF3.getValue(1);
162 SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0);
163 Chain = TmpF4.getValue(1);
164 } else { // is unsigned
166 SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1), 0);
167 Chain = TmpF3.getValue(1);
169 SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2), 0);
170 Chain = TmpF4.getValue(1);
173 } else { // this is an FP divide/remainder, so we 'leak' some temp
174 // regs and assign TmpF3=Tmp1, TmpF4=Tmp2
179 // we start by computing an approximate reciprocal (good to 9 bits?)
180 // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
182 TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
185 TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
188 TmpPR = TmpF5.getValue(1);
189 Chain = TmpF5.getValue(2);
192 if(isModulus) { // for remainders, it'll be handy to have
193 // copies of -input_b
194 minusB = SDOperand(CurDAG->getTargetNode(IA64::SUB, MVT::i64,
195 CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0);
196 Chain = minusB.getValue(1);
199 SDOperand TmpE0, TmpY1, TmpE1, TmpY2;
201 SDOperand OpsE0[] = { TmpF4, TmpF5, F1, TmpPR };
202 TmpE0 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
204 Chain = TmpE0.getValue(1);
205 SDOperand OpsY1[] = { TmpF5, TmpE0, TmpF5, TmpPR };
206 TmpY1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
208 Chain = TmpY1.getValue(1);
209 SDOperand OpsE1[] = { TmpE0, TmpE0, F0, TmpPR };
210 TmpE1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
212 Chain = TmpE1.getValue(1);
213 SDOperand OpsY2[] = { TmpY1, TmpE1, TmpY1, TmpPR };
214 TmpY2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
216 Chain = TmpY2.getValue(1);
218 if(isFP) { // if this is an FP divide, we finish up here and exit early
220 assert(0 && "Sorry, try another FORTRAN compiler.");
222 SDOperand TmpE2, TmpY3, TmpQ0, TmpR0;
224 SDOperand OpsE2[] = { TmpE1, TmpE1, F0, TmpPR };
225 TmpE2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
227 Chain = TmpE2.getValue(1);
228 SDOperand OpsY3[] = { TmpY2, TmpE2, TmpY2, TmpPR };
229 TmpY3 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
231 Chain = TmpY3.getValue(1);
232 SDOperand OpsQ0[] = { Tmp1, TmpY3, F0, TmpPR };
234 SDOperand(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
236 Chain = TmpQ0.getValue(1);
237 SDOperand OpsR0[] = { Tmp2, TmpQ0, Tmp1, TmpPR };
239 SDOperand(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
241 Chain = TmpR0.getValue(1);
243 // we want Result to have the same target register as the frcpa, so
244 // we two-address hack it. See the comment "for this to work..." on
245 // page 48 of Intel application note #245415
246 SDOperand Ops[] = { TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR };
247 Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
249 Chain = SDOperand(Result, 1);
250 return Result; // XXX: early exit!
251 } else { // this is *not* an FP divide, so there's a bit left to do:
253 SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ;
255 SDOperand OpsQ2[] = { TmpF3, TmpY2, F0, TmpPR };
256 TmpQ2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
258 Chain = TmpQ2.getValue(1);
259 SDOperand OpsR2[] = { TmpF4, TmpQ2, TmpF3, TmpPR };
260 TmpR2 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
262 Chain = TmpR2.getValue(1);
264 // we want TmpQ3 to have the same target register as the frcpa? maybe we
265 // should two-address hack it. See the comment "for this to work..." on page
266 // 48 of Intel application note #245415
267 SDOperand OpsQ3[] = { TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR };
268 TmpQ3 = SDOperand(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
270 Chain = TmpQ3.getValue(1);
272 // STORY: without these two-address instructions (TCFMAS1 and TCFMADS0)
273 // the FPSWA won't be able to help out in the case of large/tiny
274 // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
277 TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1,
278 MVT::f64, TmpQ3), 0);
280 TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1,
281 MVT::f64, TmpQ3), 0);
283 Chain = TmpQ.getValue(1);
287 SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, minusB), 0);
288 Chain = FPminusB.getValue(1);
289 SDOperand Remainder =
290 SDOperand(CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
291 TmpQ, FPminusB, TmpF1), 0);
292 Chain = Remainder.getValue(1);
293 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder);
294 Chain = SDOperand(Result, 1);
295 } else { // just an integer divide
296 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ);
297 Chain = SDOperand(Result, 1);
301 } // wasn't an FP divide
304 // Select - Convert the specified operand from a target-independent to a
305 // target-specific node if it hasn't already been changed.
306 SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
308 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
309 N->getOpcode() < IA64ISD::FIRST_NUMBER)
310 return NULL; // Already selected.
312 switch (N->getOpcode()) {
315 case IA64ISD::BRCALL: { // XXX: this is also a hack!
316 SDOperand Chain = N->getOperand(0);
317 SDOperand InFlag; // Null incoming flag value.
319 AddToISelQueue(Chain);
320 if(N->getNumOperands()==3) { // we have an incoming chain, callee and flag
321 InFlag = N->getOperand(2);
322 AddToISelQueue(InFlag);
326 SDOperand CallOperand;
328 // if we can call directly, do so
329 if (GlobalAddressSDNode *GASD =
330 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
331 CallOpcode = IA64::BRCALL_IPREL_GA;
332 CallOperand = CurDAG->getTargetGlobalAddress(GASD->getGlobal(), MVT::i64);
333 } else if (isa<ExternalSymbolSDNode>(N->getOperand(1))) {
334 // FIXME: we currently NEED this case for correctness, to avoid
335 // "non-pic code with imm reloc.n against dynamic symbol" errors
336 CallOpcode = IA64::BRCALL_IPREL_ES;
337 CallOperand = N->getOperand(1);
339 // otherwise we need to load the function descriptor,
340 // load the branch target (function)'s entry point and GP,
341 // branch (call) then restore the GP
342 SDOperand FnDescriptor = N->getOperand(1);
343 AddToISelQueue(FnDescriptor);
345 // load the branch target's entry point [mem] and
347 SDOperand targetEntryPoint=
348 SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, MVT::Other,
349 FnDescriptor, CurDAG->getEntryNode()), 0);
350 Chain = targetEntryPoint.getValue(1);
351 SDOperand targetGPAddr=
352 SDOperand(CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
354 CurDAG->getConstant(8, MVT::i64)), 0);
355 Chain = targetGPAddr.getValue(1);
357 SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64,MVT::Other,
358 targetGPAddr, CurDAG->getEntryNode()), 0);
359 Chain = targetGP.getValue(1);
361 Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag);
362 InFlag = Chain.getValue(1);
363 Chain = CurDAG->getCopyToReg(Chain, IA64::B6, targetEntryPoint, InFlag); // FLAG these?
364 InFlag = Chain.getValue(1);
366 CallOperand = CurDAG->getRegister(IA64::B6, MVT::i64);
367 CallOpcode = IA64::BRCALL_INDIRECT;
370 // Finally, once everything is setup, emit the call itself
372 Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
373 CallOperand, InFlag), 0);
374 else // there might be no arguments
375 Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
376 CallOperand, Chain), 0);
377 InFlag = Chain.getValue(1);
379 std::vector<SDOperand> CallResults;
381 CallResults.push_back(Chain);
382 CallResults.push_back(InFlag);
384 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
385 ReplaceUses(Op.getValue(i), CallResults[i]);
389 case IA64ISD::GETFD: {
390 SDOperand Input = N->getOperand(0);
391 AddToISelQueue(Input);
392 return CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input);
400 return SelectDIV(Op);
402 case ISD::TargetConstantFP: {
403 SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
406 ConstantFPSDNode* N2 = cast<ConstantFPSDNode>(N);
407 if (N2->getValueAPF().isPosZero()) {
408 V = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
409 } else if (N2->isExactlyValue(N2->getValueType(0) == MVT::f32 ?
410 APFloat(+1.0f) : APFloat(+1.0))) {
411 V = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
413 assert(0 && "Unexpected FP constant!");
415 ReplaceUses(SDOperand(N, 0), V);
419 case ISD::FrameIndex: { // TODO: reduce creepyness
420 int FI = cast<FrameIndexSDNode>(N)->getIndex();
422 return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
423 CurDAG->getTargetFrameIndex(FI, MVT::i64));
425 return CurDAG->getTargetNode(IA64::MOV, MVT::i64,
426 CurDAG->getTargetFrameIndex(FI, MVT::i64));
429 case ISD::ConstantPool: { // TODO: nuke the constant pool
430 // (ia64 doesn't need one)
431 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
432 Constant *C = CP->getConstVal();
433 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
435 return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
436 CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
439 case ISD::GlobalAddress: {
440 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
441 SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
443 SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
444 CurDAG->getRegister(IA64::r1,
446 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, MVT::Other, Tmp,
447 CurDAG->getEntryNode());
451 case ISD::ExternalSymbol: {
452 SDOperand EA = CurDAG->getTargetExternalSymbol(
453 cast<ExternalSymbolSDNode>(N)->getSymbol(),
455 SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
456 CurDAG->getRegister(IA64::r1,
459 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
463 case ISD::LOAD: { // FIXME: load -1, not 1, for bools?
464 LoadSDNode *LD = cast<LoadSDNode>(N);
465 SDOperand Chain = LD->getChain();
466 SDOperand Address = LD->getBasePtr();
467 AddToISelQueue(Chain);
468 AddToISelQueue(Address);
470 MVT TypeBeingLoaded = LD->getMemoryVT();
472 switch (TypeBeingLoaded.getSimpleVT()) {
477 assert(0 && "Cannot load this type!");
478 case MVT::i1: { // this is a bool
479 Opc = IA64::LD1; // first we load a byte, then compare for != 0
480 if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
481 return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
482 SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0),
483 CurDAG->getRegister(IA64::r0, MVT::i64),
486 /* otherwise, we want to load a bool into something bigger: LD1
487 will do that for us, so we just fall through */
489 case MVT::i8: Opc = IA64::LD1; break;
490 case MVT::i16: Opc = IA64::LD2; break;
491 case MVT::i32: Opc = IA64::LD4; break;
492 case MVT::i64: Opc = IA64::LD8; break;
494 case MVT::f32: Opc = IA64::LDF4; break;
495 case MVT::f64: Opc = IA64::LDF8; break;
498 // TODO: comment this
499 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
504 StoreSDNode *ST = cast<StoreSDNode>(N);
505 SDOperand Address = ST->getBasePtr();
506 SDOperand Chain = ST->getChain();
507 AddToISelQueue(Address);
508 AddToISelQueue(Chain);
511 if (ISD::isNON_TRUNCStore(N)) {
512 switch (N->getOperand(1).getValueType().getSimpleVT()) {
513 default: assert(0 && "unknown type in store");
514 case MVT::i1: { // this is a bool
515 Opc = IA64::ST1; // we store either 0 or 1 as a byte
517 SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
518 Chain = Initial.getValue(1);
519 // then load 1 into the same reg iff the predicate to store is 1
520 SDOperand Tmp = ST->getValue();
523 SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
524 CurDAG->getTargetConstant(1, MVT::i64),
526 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
528 case MVT::i64: Opc = IA64::ST8; break;
529 case MVT::f64: Opc = IA64::STF8; break;
531 } else { // Truncating store
532 switch(ST->getMemoryVT().getSimpleVT()) {
533 default: assert(0 && "unknown type in truncstore");
534 case MVT::i8: Opc = IA64::ST1; break;
535 case MVT::i16: Opc = IA64::ST2; break;
536 case MVT::i32: Opc = IA64::ST4; break;
537 case MVT::f32: Opc = IA64::STF4; break;
541 SDOperand N1 = N->getOperand(1);
542 SDOperand N2 = N->getOperand(2);
545 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
549 SDOperand Chain = N->getOperand(0);
550 SDOperand CC = N->getOperand(1);
551 AddToISelQueue(Chain);
553 MachineBasicBlock *Dest =
554 cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
555 //FIXME - we do NOT need long branches all the time
556 return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
557 CurDAG->getBasicBlock(Dest), Chain);
560 case ISD::CALLSEQ_START:
561 case ISD::CALLSEQ_END: {
562 int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
563 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
564 IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
565 SDOperand N0 = N->getOperand(0);
567 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
571 // FIXME: we don't need long branches all the time!
572 SDOperand N0 = N->getOperand(0);
574 return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
575 N->getOperand(1), N0);
578 return SelectCode(Op);
582 /// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG
583 /// into an IA64-specific DAG, ready for instruction scheduling.
586 *llvm::createIA64DAGToDAGInstructionSelector(IA64TargetMachine &TM) {
587 return new IA64DAGToDAGISel(TM);