1 //===---- IA64ISelDAGToDAG.cpp - IA64 pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for IA64,
11 // converting a legalized dag to an IA64 dag.
13 //===----------------------------------------------------------------------===//
16 #include "IA64TargetMachine.h"
17 #include "IA64ISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Constants.h"
26 #include "llvm/GlobalValue.h"
27 #include "llvm/Intrinsics.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
36 Statistic<> FusedFP ("ia64-codegen", "Number of fused fp operations");
37 Statistic<> FrameOff("ia64-codegen", "Number of frame idx offsets collapsed");
39 //===--------------------------------------------------------------------===//
40 /// IA64DAGToDAGISel - IA64 specific code to select IA64 machine
41 /// instructions for SelectionDAG operations.
43 class IA64DAGToDAGISel : public SelectionDAGISel {
44 IA64TargetLowering IA64Lowering;
45 unsigned GlobalBaseReg;
47 IA64DAGToDAGISel(IA64TargetMachine &TM)
48 : SelectionDAGISel(IA64Lowering), IA64Lowering(*TM.getTargetLowering()) {}
50 virtual bool runOnFunction(Function &Fn) {
51 // Make sure we re-emit a set of the global base reg if necessary
53 return SelectionDAGISel::runOnFunction(Fn);
56 /// getI64Imm - Return a target constant with the specified value, of type
58 inline SDOperand getI64Imm(uint64_t Imm) {
59 return CurDAG->getTargetConstant(Imm, MVT::i64);
62 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
63 /// base register. Return the virtual register that holds this value.
64 // SDOperand getGlobalBaseReg(); TODO: hmm
66 // Select - Convert the specified operand from a target-independent to a
67 // target-specific node if it hasn't already been changed.
68 SDNode *Select(SDOperand N);
70 SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
71 unsigned OCHi, unsigned OCLo,
72 bool IsArithmetic = false,
74 SDNode *SelectBitfieldInsert(SDNode *N);
76 /// SelectCC - Select a comparison of the specified values with the
77 /// specified condition code, returning the CR# of the expression.
78 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
80 /// SelectAddr - Given the specified address, return the two operands for a
81 /// load/store instruction, and return true if it should be an indexed [r+r]
83 bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
85 /// InstructionSelectBasicBlock - This callback is invoked by
86 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
87 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
89 virtual const char *getPassName() const {
90 return "IA64 (Itanium) DAG->DAG Instruction Selector";
93 // Include the pieces autogenerated from the target description.
94 #include "IA64GenDAGISel.inc"
97 SDNode *SelectDIV(SDOperand Op);
101 /// InstructionSelectBasicBlock - This callback is invoked by
102 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
103 void IA64DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
106 // Select target instructions for the DAG.
107 DAG.setRoot(SelectRoot(DAG.getRoot()));
108 DAG.RemoveDeadNodes();
110 // Emit machine code to BB.
111 ScheduleAndEmitDAG(DAG);
114 SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
116 SDOperand Chain = N->getOperand(0);
117 SDOperand Tmp1 = N->getOperand(0);
118 SDOperand Tmp2 = N->getOperand(1);
119 AddToISelQueue(Chain);
121 AddToISelQueue(Tmp1);
122 AddToISelQueue(Tmp2);
126 if(MVT::isFloatingPoint(Tmp1.getValueType()))
129 bool isModulus=false; // is it a division or a modulus?
132 switch(N->getOpcode()) {
134 case ISD::SDIV: isModulus=false; isSigned=true; break;
135 case ISD::UDIV: isModulus=false; isSigned=false; break;
137 case ISD::SREM: isModulus=true; isSigned=true; break;
138 case ISD::UREM: isModulus=true; isSigned=false; break;
141 // TODO: check for integer divides by powers of 2 (or other simple patterns?)
143 SDOperand TmpPR, TmpPR2;
144 SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
145 SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
148 // we'll need copies of F0 and F1
149 SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
150 SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
152 // OK, emit some code:
155 // first, load the inputs into FP regs.
157 SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0);
158 Chain = TmpF1.getValue(1);
160 SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0);
161 Chain = TmpF2.getValue(1);
163 // next, convert the inputs to FP
166 SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0);
167 Chain = TmpF3.getValue(1);
169 SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0);
170 Chain = TmpF4.getValue(1);
171 } else { // is unsigned
173 SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1), 0);
174 Chain = TmpF3.getValue(1);
176 SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2), 0);
177 Chain = TmpF4.getValue(1);
180 } else { // this is an FP divide/remainder, so we 'leak' some temp
181 // regs and assign TmpF3=Tmp1, TmpF4=Tmp2
186 // we start by computing an approximate reciprocal (good to 9 bits?)
187 // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
189 TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
192 TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
195 TmpPR = TmpF5.getValue(1);
196 Chain = TmpF5.getValue(2);
199 if(isModulus) { // for remainders, it'll be handy to have
200 // copies of -input_b
201 minusB = SDOperand(CurDAG->getTargetNode(IA64::SUB, MVT::i64,
202 CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0);
203 Chain = minusB.getValue(1);
206 SDOperand TmpE0, TmpY1, TmpE1, TmpY2;
208 TmpE0 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
209 TmpF4, TmpF5, F1, TmpPR), 0);
210 Chain = TmpE0.getValue(1);
211 TmpY1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
212 TmpF5, TmpE0, TmpF5, TmpPR), 0);
213 Chain = TmpY1.getValue(1);
214 TmpE1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
215 TmpE0, TmpE0, F0, TmpPR), 0);
216 Chain = TmpE1.getValue(1);
217 TmpY2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
218 TmpY1, TmpE1, TmpY1, TmpPR), 0);
219 Chain = TmpY2.getValue(1);
221 if(isFP) { // if this is an FP divide, we finish up here and exit early
223 assert(0 && "Sorry, try another FORTRAN compiler.");
225 SDOperand TmpE2, TmpY3, TmpQ0, TmpR0;
227 TmpE2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
228 TmpE1, TmpE1, F0, TmpPR), 0);
229 Chain = TmpE2.getValue(1);
230 TmpY3 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
231 TmpY2, TmpE2, TmpY2, TmpPR), 0);
232 Chain = TmpY3.getValue(1);
234 SDOperand(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
235 Tmp1, TmpY3, F0, TmpPR), 0);
236 Chain = TmpQ0.getValue(1);
238 SDOperand(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
239 Tmp2, TmpQ0, Tmp1, TmpPR), 0);
240 Chain = TmpR0.getValue(1);
242 // we want Result to have the same target register as the frcpa, so
243 // we two-address hack it. See the comment "for this to work..." on
244 // page 48 of Intel application note #245415
245 Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
246 TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR);
247 Chain = SDOperand(Result, 1);
248 return Result; // XXX: early exit!
249 } else { // this is *not* an FP divide, so there's a bit left to do:
251 SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ;
253 TmpQ2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
254 TmpF3, TmpY2, F0, TmpPR), 0);
255 Chain = TmpQ2.getValue(1);
256 TmpR2 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
257 TmpF4, TmpQ2, TmpF3, TmpPR), 0);
258 Chain = TmpR2.getValue(1);
260 // we want TmpQ3 to have the same target register as the frcpa? maybe we
261 // should two-address hack it. See the comment "for this to work..." on page
262 // 48 of Intel application note #245415
263 TmpQ3 = SDOperand(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
264 TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR), 0);
265 Chain = TmpQ3.getValue(1);
267 // STORY: without these two-address instructions (TCFMAS1 and TCFMADS0)
268 // the FPSWA won't be able to help out in the case of large/tiny
269 // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
272 TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1,
273 MVT::f64, TmpQ3), 0);
275 TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1,
276 MVT::f64, TmpQ3), 0);
278 Chain = TmpQ.getValue(1);
282 SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, minusB), 0);
283 Chain = FPminusB.getValue(1);
284 SDOperand Remainder =
285 SDOperand(CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
286 TmpQ, FPminusB, TmpF1), 0);
287 Chain = Remainder.getValue(1);
288 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder);
289 Chain = SDOperand(Result, 1);
290 } else { // just an integer divide
291 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ);
292 Chain = SDOperand(Result, 1);
296 } // wasn't an FP divide
299 // Select - Convert the specified operand from a target-independent to a
300 // target-specific node if it hasn't already been changed.
301 SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
303 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
304 N->getOpcode() < IA64ISD::FIRST_NUMBER)
305 return NULL; // Already selected.
307 switch (N->getOpcode()) {
310 case IA64ISD::BRCALL: { // XXX: this is also a hack!
311 SDOperand Chain = N->getOperand(0);
312 SDOperand InFlag; // Null incoming flag value.
314 AddToISelQueue(Chain);
315 if(N->getNumOperands()==3) { // we have an incoming chain, callee and flag
316 InFlag = N->getOperand(2);
317 AddToISelQueue(InFlag);
321 SDOperand CallOperand;
323 // if we can call directly, do so
324 if (GlobalAddressSDNode *GASD =
325 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
326 CallOpcode = IA64::BRCALL_IPREL_GA;
327 CallOperand = CurDAG->getTargetGlobalAddress(GASD->getGlobal(), MVT::i64);
328 } else if (ExternalSymbolSDNode *ESSDN = // FIXME: we currently NEED this
329 // case for correctness, to avoid
330 // "non-pic code with imm reloc.n
331 // against dynamic symbol" errors
332 dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
333 CallOpcode = IA64::BRCALL_IPREL_ES;
334 CallOperand = N->getOperand(1);
336 // otherwise we need to load the function descriptor,
337 // load the branch target (function)'s entry point and GP,
338 // branch (call) then restore the GP
339 SDOperand FnDescriptor = N->getOperand(1);
340 AddToISelQueue(FnDescriptor);
342 // load the branch target's entry point [mem] and
344 SDOperand targetEntryPoint=
345 SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, FnDescriptor), 0);
346 Chain = targetEntryPoint.getValue(1);
347 SDOperand targetGPAddr=
348 SDOperand(CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
349 FnDescriptor, CurDAG->getConstant(8, MVT::i64)), 0);
350 Chain = targetGPAddr.getValue(1);
352 SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, targetGPAddr), 0);
353 Chain = targetGP.getValue(1);
355 Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag);
356 InFlag = Chain.getValue(1);
357 Chain = CurDAG->getCopyToReg(Chain, IA64::B6, targetEntryPoint, InFlag); // FLAG these?
358 InFlag = Chain.getValue(1);
360 CallOperand = CurDAG->getRegister(IA64::B6, MVT::i64);
361 CallOpcode = IA64::BRCALL_INDIRECT;
364 // Finally, once everything is setup, emit the call itself
366 Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
367 CallOperand, InFlag), 0);
368 else // there might be no arguments
369 Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
370 CallOperand, Chain), 0);
371 InFlag = Chain.getValue(1);
373 std::vector<SDOperand> CallResults;
375 CallResults.push_back(Chain);
376 CallResults.push_back(InFlag);
378 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
379 ReplaceUses(Op.getValue(i), CallResults[i]);
383 case IA64ISD::GETFD: {
384 SDOperand Input = N->getOperand(0);
385 AddToISelQueue(Input);
386 return CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input);
394 return SelectDIV(Op);
396 case ISD::TargetConstantFP: {
397 SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
399 if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0)) {
400 return CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64).Val;
401 } else if (cast<ConstantFPSDNode>(N)->isExactlyValue(+1.0)) {
402 return CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64).Val;
404 assert(0 && "Unexpected FP constant!");
407 case ISD::FrameIndex: { // TODO: reduce creepyness
408 int FI = cast<FrameIndexSDNode>(N)->getIndex();
410 return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
411 CurDAG->getTargetFrameIndex(FI, MVT::i64));
413 return CurDAG->getTargetNode(IA64::MOV, MVT::i64,
414 CurDAG->getTargetFrameIndex(FI, MVT::i64));
417 case ISD::ConstantPool: { // TODO: nuke the constant pool
418 // (ia64 doesn't need one)
419 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
420 Constant *C = CP->get();
421 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
423 return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
424 CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
427 case ISD::GlobalAddress: {
428 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
429 SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
430 SDOperand Tmp = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
431 CurDAG->getRegister(IA64::r1, MVT::i64), GA), 0);
432 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
435 /* XXX case ISD::ExternalSymbol: {
436 SDOperand EA = CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(),
438 SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
439 CurDAG->getRegister(IA64::r1, MVT::i64), EA);
440 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
445 case ISD::EXTLOAD: // FIXME: load -1, not 1, for bools?
446 case ISD::ZEXTLOAD: {
447 SDOperand Chain = N->getOperand(0);
448 SDOperand Address = N->getOperand(1);
449 AddToISelQueue(Chain);
450 AddToISelQueue(Address);
452 MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
453 N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
455 switch (TypeBeingLoaded) {
460 assert(0 && "Cannot load this type!");
461 case MVT::i1: { // this is a bool
462 Opc = IA64::LD1; // first we load a byte, then compare for != 0
463 if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
464 return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
465 SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0),
466 CurDAG->getRegister(IA64::r0, MVT::i64),
469 /* otherwise, we want to load a bool into something bigger: LD1
470 will do that for us, so we just fall through */
472 case MVT::i8: Opc = IA64::LD1; break;
473 case MVT::i16: Opc = IA64::LD2; break;
474 case MVT::i32: Opc = IA64::LD4; break;
475 case MVT::i64: Opc = IA64::LD8; break;
477 case MVT::f32: Opc = IA64::LDF4; break;
478 case MVT::f64: Opc = IA64::LDF8; break;
481 // TODO: comment this
482 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
486 case ISD::TRUNCSTORE:
488 SDOperand Address = N->getOperand(2);
489 SDOperand Chain = N->getOperand(0);
490 AddToISelQueue(Address);
491 AddToISelQueue(Chain);
494 if (N->getOpcode() == ISD::STORE) {
495 switch (N->getOperand(1).getValueType()) {
496 default: assert(0 && "unknown type in store");
497 case MVT::i1: { // this is a bool
498 Opc = IA64::ST1; // we store either 0 or 1 as a byte
500 SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
501 Chain = Initial.getValue(1);
502 // then load 1 into the same reg iff the predicate to store is 1
503 SDOperand Tmp = N->getOperand(1);
505 Tmp = SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
506 CurDAG->getConstant(1, MVT::i64),
508 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
510 case MVT::i64: Opc = IA64::ST8; break;
511 case MVT::f64: Opc = IA64::STF8; break;
513 } else { //ISD::TRUNCSTORE
514 switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
515 default: assert(0 && "unknown type in truncstore");
516 case MVT::i8: Opc = IA64::ST1; break;
517 case MVT::i16: Opc = IA64::ST2; break;
518 case MVT::i32: Opc = IA64::ST4; break;
519 case MVT::f32: Opc = IA64::STF4; break;
523 SDOperand N1 = N->getOperand(1);
524 SDOperand N2 = N->getOperand(2);
527 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
531 SDOperand Chain = N->getOperand(0);
532 SDOperand CC = N->getOperand(1);
533 AddToISelQueue(Chain);
535 MachineBasicBlock *Dest =
536 cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
537 //FIXME - we do NOT need long branches all the time
538 return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
539 CurDAG->getBasicBlock(Dest), Chain);
542 case ISD::CALLSEQ_START:
543 case ISD::CALLSEQ_END: {
544 int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
545 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
546 IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
547 SDOperand N0 = N->getOperand(0);
549 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
553 // FIXME: we don't need long branches all the time!
554 SDOperand N0 = N->getOperand(0);
556 return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
557 N->getOperand(1), N0);
560 return SelectCode(Op);
564 /// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG
565 /// into an IA64-specific DAG, ready for instruction scheduling.
568 *llvm::createIA64DAGToDAGInstructionSelector(IA64TargetMachine &TM) {
569 return new IA64DAGToDAGISel(TM);