1 //===---- IA64ISelDAGToDAG.cpp - IA64 pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for IA64,
11 // converting a legalized dag to an IA64 dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "ia64-codegen"
17 #include "IA64TargetMachine.h"
18 #include "IA64ISelLowering.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Constants.h"
26 #include "llvm/GlobalValue.h"
27 #include "llvm/Intrinsics.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
35 //===--------------------------------------------------------------------===//
36 /// IA64DAGToDAGISel - IA64 specific code to select IA64 machine
37 /// instructions for SelectionDAG operations.
39 class IA64DAGToDAGISel : public SelectionDAGISel {
40 IA64TargetLowering IA64Lowering;
41 unsigned GlobalBaseReg;
43 IA64DAGToDAGISel(IA64TargetMachine &TM)
44 : SelectionDAGISel(IA64Lowering), IA64Lowering(*TM.getTargetLowering()) {}
46 virtual bool runOnFunction(Function &Fn) {
47 // Make sure we re-emit a set of the global base reg if necessary
49 return SelectionDAGISel::runOnFunction(Fn);
52 /// getI64Imm - Return a target constant with the specified value, of type
54 inline SDOperand getI64Imm(uint64_t Imm) {
55 return CurDAG->getTargetConstant(Imm, MVT::i64);
58 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
59 /// base register. Return the virtual register that holds this value.
60 // SDOperand getGlobalBaseReg(); TODO: hmm
62 // Select - Convert the specified operand from a target-independent to a
63 // target-specific node if it hasn't already been changed.
64 SDNode *Select(SDOperand N);
66 SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
67 unsigned OCHi, unsigned OCLo,
68 bool IsArithmetic = false,
70 SDNode *SelectBitfieldInsert(SDNode *N);
72 /// SelectCC - Select a comparison of the specified values with the
73 /// specified condition code, returning the CR# of the expression.
74 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
76 /// SelectAddr - Given the specified address, return the two operands for a
77 /// load/store instruction, and return true if it should be an indexed [r+r]
79 bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
81 /// InstructionSelectBasicBlock - This callback is invoked by
82 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
83 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
85 virtual const char *getPassName() const {
86 return "IA64 (Itanium) DAG->DAG Instruction Selector";
89 // Include the pieces autogenerated from the target description.
90 #include "IA64GenDAGISel.inc"
93 SDNode *SelectDIV(SDOperand Op);
97 /// InstructionSelectBasicBlock - This callback is invoked by
98 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
99 void IA64DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
102 // Select target instructions for the DAG.
103 DAG.setRoot(SelectRoot(DAG.getRoot()));
104 DAG.RemoveDeadNodes();
106 // Emit machine code to BB.
107 ScheduleAndEmitDAG(DAG);
110 SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
112 SDOperand Chain = N->getOperand(0);
113 SDOperand Tmp1 = N->getOperand(0);
114 SDOperand Tmp2 = N->getOperand(1);
115 AddToISelQueue(Chain);
117 AddToISelQueue(Tmp1);
118 AddToISelQueue(Tmp2);
122 if(MVT::isFloatingPoint(Tmp1.getValueType()))
125 bool isModulus=false; // is it a division or a modulus?
128 switch(N->getOpcode()) {
130 case ISD::SDIV: isModulus=false; isSigned=true; break;
131 case ISD::UDIV: isModulus=false; isSigned=false; break;
133 case ISD::SREM: isModulus=true; isSigned=true; break;
134 case ISD::UREM: isModulus=true; isSigned=false; break;
137 // TODO: check for integer divides by powers of 2 (or other simple patterns?)
139 SDOperand TmpPR, TmpPR2;
140 SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
141 SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
144 // we'll need copies of F0 and F1
145 SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
146 SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
148 // OK, emit some code:
151 // first, load the inputs into FP regs.
153 SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0);
154 Chain = TmpF1.getValue(1);
156 SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0);
157 Chain = TmpF2.getValue(1);
159 // next, convert the inputs to FP
162 SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0);
163 Chain = TmpF3.getValue(1);
165 SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0);
166 Chain = TmpF4.getValue(1);
167 } else { // is unsigned
169 SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1), 0);
170 Chain = TmpF3.getValue(1);
172 SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2), 0);
173 Chain = TmpF4.getValue(1);
176 } else { // this is an FP divide/remainder, so we 'leak' some temp
177 // regs and assign TmpF3=Tmp1, TmpF4=Tmp2
182 // we start by computing an approximate reciprocal (good to 9 bits?)
183 // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
185 TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
188 TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
191 TmpPR = TmpF5.getValue(1);
192 Chain = TmpF5.getValue(2);
195 if(isModulus) { // for remainders, it'll be handy to have
196 // copies of -input_b
197 minusB = SDOperand(CurDAG->getTargetNode(IA64::SUB, MVT::i64,
198 CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0);
199 Chain = minusB.getValue(1);
202 SDOperand TmpE0, TmpY1, TmpE1, TmpY2;
204 SDOperand OpsE0[] = { TmpF4, TmpF5, F1, TmpPR };
205 TmpE0 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
207 Chain = TmpE0.getValue(1);
208 SDOperand OpsY1[] = { TmpF5, TmpE0, TmpF5, TmpPR };
209 TmpY1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
211 Chain = TmpY1.getValue(1);
212 SDOperand OpsE1[] = { TmpE0, TmpE0, F0, TmpPR };
213 TmpE1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
215 Chain = TmpE1.getValue(1);
216 SDOperand OpsY2[] = { TmpY1, TmpE1, TmpY1, TmpPR };
217 TmpY2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
219 Chain = TmpY2.getValue(1);
221 if(isFP) { // if this is an FP divide, we finish up here and exit early
223 assert(0 && "Sorry, try another FORTRAN compiler.");
225 SDOperand TmpE2, TmpY3, TmpQ0, TmpR0;
227 SDOperand OpsE2[] = { TmpE1, TmpE1, F0, TmpPR };
228 TmpE2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
230 Chain = TmpE2.getValue(1);
231 SDOperand OpsY3[] = { TmpY2, TmpE2, TmpY2, TmpPR };
232 TmpY3 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
234 Chain = TmpY3.getValue(1);
235 SDOperand OpsQ0[] = { Tmp1, TmpY3, F0, TmpPR };
237 SDOperand(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
239 Chain = TmpQ0.getValue(1);
240 SDOperand OpsR0[] = { Tmp2, TmpQ0, Tmp1, TmpPR };
242 SDOperand(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
244 Chain = TmpR0.getValue(1);
246 // we want Result to have the same target register as the frcpa, so
247 // we two-address hack it. See the comment "for this to work..." on
248 // page 48 of Intel application note #245415
249 SDOperand Ops[] = { TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR };
250 Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
252 Chain = SDOperand(Result, 1);
253 return Result; // XXX: early exit!
254 } else { // this is *not* an FP divide, so there's a bit left to do:
256 SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ;
258 SDOperand OpsQ2[] = { TmpF3, TmpY2, F0, TmpPR };
259 TmpQ2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
261 Chain = TmpQ2.getValue(1);
262 SDOperand OpsR2[] = { TmpF4, TmpQ2, TmpF3, TmpPR };
263 TmpR2 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
265 Chain = TmpR2.getValue(1);
267 // we want TmpQ3 to have the same target register as the frcpa? maybe we
268 // should two-address hack it. See the comment "for this to work..." on page
269 // 48 of Intel application note #245415
270 SDOperand OpsQ3[] = { TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR };
271 TmpQ3 = SDOperand(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
273 Chain = TmpQ3.getValue(1);
275 // STORY: without these two-address instructions (TCFMAS1 and TCFMADS0)
276 // the FPSWA won't be able to help out in the case of large/tiny
277 // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
280 TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1,
281 MVT::f64, TmpQ3), 0);
283 TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1,
284 MVT::f64, TmpQ3), 0);
286 Chain = TmpQ.getValue(1);
290 SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, minusB), 0);
291 Chain = FPminusB.getValue(1);
292 SDOperand Remainder =
293 SDOperand(CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
294 TmpQ, FPminusB, TmpF1), 0);
295 Chain = Remainder.getValue(1);
296 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder);
297 Chain = SDOperand(Result, 1);
298 } else { // just an integer divide
299 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ);
300 Chain = SDOperand(Result, 1);
304 } // wasn't an FP divide
307 // Select - Convert the specified operand from a target-independent to a
308 // target-specific node if it hasn't already been changed.
309 SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
311 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
312 N->getOpcode() < IA64ISD::FIRST_NUMBER)
313 return NULL; // Already selected.
315 switch (N->getOpcode()) {
318 case IA64ISD::BRCALL: { // XXX: this is also a hack!
319 SDOperand Chain = N->getOperand(0);
320 SDOperand InFlag; // Null incoming flag value.
322 AddToISelQueue(Chain);
323 if(N->getNumOperands()==3) { // we have an incoming chain, callee and flag
324 InFlag = N->getOperand(2);
325 AddToISelQueue(InFlag);
329 SDOperand CallOperand;
331 // if we can call directly, do so
332 if (GlobalAddressSDNode *GASD =
333 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
334 CallOpcode = IA64::BRCALL_IPREL_GA;
335 CallOperand = CurDAG->getTargetGlobalAddress(GASD->getGlobal(), MVT::i64);
336 } else if (isa<ExternalSymbolSDNode>(N->getOperand(1))) {
337 // FIXME: we currently NEED this case for correctness, to avoid
338 // "non-pic code with imm reloc.n against dynamic symbol" errors
339 CallOpcode = IA64::BRCALL_IPREL_ES;
340 CallOperand = N->getOperand(1);
342 // otherwise we need to load the function descriptor,
343 // load the branch target (function)'s entry point and GP,
344 // branch (call) then restore the GP
345 SDOperand FnDescriptor = N->getOperand(1);
346 AddToISelQueue(FnDescriptor);
348 // load the branch target's entry point [mem] and
350 SDOperand targetEntryPoint=
351 SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, FnDescriptor), 0);
352 Chain = targetEntryPoint.getValue(1);
353 SDOperand targetGPAddr=
354 SDOperand(CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
356 CurDAG->getConstant(8, MVT::i64)), 0);
357 Chain = targetGPAddr.getValue(1);
359 SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, targetGPAddr), 0);
360 Chain = targetGP.getValue(1);
362 Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag);
363 InFlag = Chain.getValue(1);
364 Chain = CurDAG->getCopyToReg(Chain, IA64::B6, targetEntryPoint, InFlag); // FLAG these?
365 InFlag = Chain.getValue(1);
367 CallOperand = CurDAG->getRegister(IA64::B6, MVT::i64);
368 CallOpcode = IA64::BRCALL_INDIRECT;
371 // Finally, once everything is setup, emit the call itself
373 Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
374 CallOperand, InFlag), 0);
375 else // there might be no arguments
376 Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
377 CallOperand, Chain), 0);
378 InFlag = Chain.getValue(1);
380 std::vector<SDOperand> CallResults;
382 CallResults.push_back(Chain);
383 CallResults.push_back(InFlag);
385 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
386 ReplaceUses(Op.getValue(i), CallResults[i]);
390 case IA64ISD::GETFD: {
391 SDOperand Input = N->getOperand(0);
392 AddToISelQueue(Input);
393 return CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input);
401 return SelectDIV(Op);
403 case ISD::TargetConstantFP: {
404 SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
407 if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0)) {
408 V = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
409 } else if (cast<ConstantFPSDNode>(N)->isExactlyValue(+1.0)) {
410 V = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
412 assert(0 && "Unexpected FP constant!");
414 ReplaceUses(SDOperand(N, 0), V);
418 case ISD::FrameIndex: { // TODO: reduce creepyness
419 int FI = cast<FrameIndexSDNode>(N)->getIndex();
421 return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
422 CurDAG->getTargetFrameIndex(FI, MVT::i64));
424 return CurDAG->getTargetNode(IA64::MOV, MVT::i64,
425 CurDAG->getTargetFrameIndex(FI, MVT::i64));
428 case ISD::ConstantPool: { // TODO: nuke the constant pool
429 // (ia64 doesn't need one)
430 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
431 Constant *C = CP->getConstVal();
432 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
434 return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
435 CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
438 case ISD::GlobalAddress: {
439 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
440 SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
442 SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
443 CurDAG->getRegister(IA64::r1,
445 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
449 case ISD::ExternalSymbol: {
450 SDOperand EA = CurDAG->getTargetExternalSymbol(
451 cast<ExternalSymbolSDNode>(N)->getSymbol(),
453 SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
454 CurDAG->getRegister(IA64::r1,
457 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
461 case ISD::LOAD: { // FIXME: load -1, not 1, for bools?
462 LoadSDNode *LD = cast<LoadSDNode>(N);
463 SDOperand Chain = LD->getChain();
464 SDOperand Address = LD->getBasePtr();
465 AddToISelQueue(Chain);
466 AddToISelQueue(Address);
468 MVT::ValueType TypeBeingLoaded = LD->getLoadedVT();
470 switch (TypeBeingLoaded) {
475 assert(0 && "Cannot load this type!");
476 case MVT::i1: { // this is a bool
477 Opc = IA64::LD1; // first we load a byte, then compare for != 0
478 if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
479 return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
480 SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0),
481 CurDAG->getRegister(IA64::r0, MVT::i64),
484 /* otherwise, we want to load a bool into something bigger: LD1
485 will do that for us, so we just fall through */
487 case MVT::i8: Opc = IA64::LD1; break;
488 case MVT::i16: Opc = IA64::LD2; break;
489 case MVT::i32: Opc = IA64::LD4; break;
490 case MVT::i64: Opc = IA64::LD8; break;
492 case MVT::f32: Opc = IA64::LDF4; break;
493 case MVT::f64: Opc = IA64::LDF8; break;
496 // TODO: comment this
497 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
502 StoreSDNode *ST = cast<StoreSDNode>(N);
503 SDOperand Address = ST->getBasePtr();
504 SDOperand Chain = ST->getChain();
505 AddToISelQueue(Address);
506 AddToISelQueue(Chain);
509 if (ISD::isNON_TRUNCStore(N)) {
510 switch (N->getOperand(1).getValueType()) {
511 default: assert(0 && "unknown type in store");
512 case MVT::i1: { // this is a bool
513 Opc = IA64::ST1; // we store either 0 or 1 as a byte
515 SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
516 Chain = Initial.getValue(1);
517 // then load 1 into the same reg iff the predicate to store is 1
518 SDOperand Tmp = ST->getValue();
521 SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
522 CurDAG->getTargetConstant(1, MVT::i64),
524 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
526 case MVT::i64: Opc = IA64::ST8; break;
527 case MVT::f64: Opc = IA64::STF8; break;
529 } else { // Truncating store
530 switch(ST->getStoredVT()) {
531 default: assert(0 && "unknown type in truncstore");
532 case MVT::i8: Opc = IA64::ST1; break;
533 case MVT::i16: Opc = IA64::ST2; break;
534 case MVT::i32: Opc = IA64::ST4; break;
535 case MVT::f32: Opc = IA64::STF4; break;
539 SDOperand N1 = N->getOperand(1);
540 SDOperand N2 = N->getOperand(2);
543 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
547 SDOperand Chain = N->getOperand(0);
548 SDOperand CC = N->getOperand(1);
549 AddToISelQueue(Chain);
551 MachineBasicBlock *Dest =
552 cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
553 //FIXME - we do NOT need long branches all the time
554 return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
555 CurDAG->getBasicBlock(Dest), Chain);
558 case ISD::CALLSEQ_START:
559 case ISD::CALLSEQ_END: {
560 int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
561 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
562 IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
563 SDOperand N0 = N->getOperand(0);
565 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
569 // FIXME: we don't need long branches all the time!
570 SDOperand N0 = N->getOperand(0);
572 return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
573 N->getOperand(1), N0);
576 return SelectCode(Op);
580 /// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG
581 /// into an IA64-specific DAG, ready for instruction scheduling.
584 *llvm::createIA64DAGToDAGInstructionSelector(IA64TargetMachine &TM) {
585 return new IA64DAGToDAGISel(TM);