1 //===---- IA64ISelDAGToDAG.cpp - IA64 pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for IA64,
11 // converting a legalized dag to an IA64 dag.
13 //===----------------------------------------------------------------------===//
16 #include "IA64TargetMachine.h"
17 #include "IA64ISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Constants.h"
26 #include "llvm/GlobalValue.h"
27 #include "llvm/Intrinsics.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
36 Statistic<> FusedFP ("ia64-codegen", "Number of fused fp operations");
37 Statistic<> FrameOff("ia64-codegen", "Number of frame idx offsets collapsed");
39 //===--------------------------------------------------------------------===//
40 /// IA64DAGToDAGISel - IA64 specific code to select IA64 machine
41 /// instructions for SelectionDAG operations.
43 class IA64DAGToDAGISel : public SelectionDAGISel {
44 IA64TargetLowering IA64Lowering;
45 unsigned GlobalBaseReg;
47 IA64DAGToDAGISel(IA64TargetMachine &TM)
48 : SelectionDAGISel(IA64Lowering), IA64Lowering(*TM.getTargetLowering()) {}
50 virtual bool runOnFunction(Function &Fn) {
51 // Make sure we re-emit a set of the global base reg if necessary
53 return SelectionDAGISel::runOnFunction(Fn);
56 /// getI64Imm - Return a target constant with the specified value, of type
58 inline SDOperand getI64Imm(uint64_t Imm) {
59 return CurDAG->getTargetConstant(Imm, MVT::i64);
62 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
63 /// base register. Return the virtual register that holds this value.
64 // SDOperand getGlobalBaseReg(); TODO: hmm
66 // Select - Convert the specified operand from a target-independent to a
67 // target-specific node if it hasn't already been changed.
68 SDNode *Select(SDOperand N);
70 SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
71 unsigned OCHi, unsigned OCLo,
72 bool IsArithmetic = false,
74 SDNode *SelectBitfieldInsert(SDNode *N);
76 /// SelectCC - Select a comparison of the specified values with the
77 /// specified condition code, returning the CR# of the expression.
78 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
80 /// SelectAddr - Given the specified address, return the two operands for a
81 /// load/store instruction, and return true if it should be an indexed [r+r]
83 bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
85 /// InstructionSelectBasicBlock - This callback is invoked by
86 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
87 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
89 virtual const char *getPassName() const {
90 return "IA64 (Itanium) DAG->DAG Instruction Selector";
93 // Include the pieces autogenerated from the target description.
94 #include "IA64GenDAGISel.inc"
97 SDNode *SelectDIV(SDOperand Op);
101 /// InstructionSelectBasicBlock - This callback is invoked by
102 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
103 void IA64DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
106 // Select target instructions for the DAG.
107 DAG.setRoot(SelectRoot(DAG.getRoot()));
108 DAG.RemoveDeadNodes();
110 // Emit machine code to BB.
111 ScheduleAndEmitDAG(DAG);
114 SDNode *IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
116 SDOperand Chain = N->getOperand(0);
117 SDOperand Tmp1 = N->getOperand(0);
118 SDOperand Tmp2 = N->getOperand(1);
119 AddToISelQueue(Chain);
121 AddToISelQueue(Tmp1);
122 AddToISelQueue(Tmp2);
126 if(MVT::isFloatingPoint(Tmp1.getValueType()))
129 bool isModulus=false; // is it a division or a modulus?
132 switch(N->getOpcode()) {
134 case ISD::SDIV: isModulus=false; isSigned=true; break;
135 case ISD::UDIV: isModulus=false; isSigned=false; break;
137 case ISD::SREM: isModulus=true; isSigned=true; break;
138 case ISD::UREM: isModulus=true; isSigned=false; break;
141 // TODO: check for integer divides by powers of 2 (or other simple patterns?)
143 SDOperand TmpPR, TmpPR2;
144 SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
145 SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
148 // we'll need copies of F0 and F1
149 SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
150 SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
152 // OK, emit some code:
155 // first, load the inputs into FP regs.
157 SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1), 0);
158 Chain = TmpF1.getValue(1);
160 SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2), 0);
161 Chain = TmpF2.getValue(1);
163 // next, convert the inputs to FP
166 SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1), 0);
167 Chain = TmpF3.getValue(1);
169 SDOperand(CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2), 0);
170 Chain = TmpF4.getValue(1);
171 } else { // is unsigned
173 SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1), 0);
174 Chain = TmpF3.getValue(1);
176 SDOperand(CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2), 0);
177 Chain = TmpF4.getValue(1);
180 } else { // this is an FP divide/remainder, so we 'leak' some temp
181 // regs and assign TmpF3=Tmp1, TmpF4=Tmp2
186 // we start by computing an approximate reciprocal (good to 9 bits?)
187 // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
189 TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS0, MVT::f64, MVT::i1,
192 TmpF5 = SDOperand(CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
195 TmpPR = TmpF5.getValue(1);
196 Chain = TmpF5.getValue(2);
199 if(isModulus) { // for remainders, it'll be handy to have
200 // copies of -input_b
201 minusB = SDOperand(CurDAG->getTargetNode(IA64::SUB, MVT::i64,
202 CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2), 0);
203 Chain = minusB.getValue(1);
206 SDOperand TmpE0, TmpY1, TmpE1, TmpY2;
208 SDOperand OpsE0[] = { TmpF4, TmpF5, F1, TmpPR };
209 TmpE0 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
211 Chain = TmpE0.getValue(1);
212 SDOperand OpsY1[] = { TmpF5, TmpE0, TmpF5, TmpPR };
213 TmpY1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
215 Chain = TmpY1.getValue(1);
216 SDOperand OpsE1[] = { TmpE0, TmpE0, F0, TmpPR };
217 TmpE1 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
219 Chain = TmpE1.getValue(1);
220 SDOperand OpsY2[] = { TmpY1, TmpE1, TmpY1, TmpPR };
221 TmpY2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
223 Chain = TmpY2.getValue(1);
225 if(isFP) { // if this is an FP divide, we finish up here and exit early
227 assert(0 && "Sorry, try another FORTRAN compiler.");
229 SDOperand TmpE2, TmpY3, TmpQ0, TmpR0;
231 SDOperand OpsE2[] = { TmpE1, TmpE1, F0, TmpPR };
232 TmpE2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
234 Chain = TmpE2.getValue(1);
235 SDOperand OpsY3[] = { TmpY2, TmpE2, TmpY2, TmpPR };
236 TmpY3 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
238 Chain = TmpY3.getValue(1);
239 SDOperand OpsQ0[] = { Tmp1, TmpY3, F0, TmpPR };
241 SDOperand(CurDAG->getTargetNode(IA64::CFMADS1, MVT::f64, // double prec!
243 Chain = TmpQ0.getValue(1);
244 SDOperand OpsR0[] = { Tmp2, TmpQ0, Tmp1, TmpPR };
246 SDOperand(CurDAG->getTargetNode(IA64::CFNMADS1, MVT::f64, // double prec!
248 Chain = TmpR0.getValue(1);
250 // we want Result to have the same target register as the frcpa, so
251 // we two-address hack it. See the comment "for this to work..." on
252 // page 48 of Intel application note #245415
253 SDOperand Ops[] = { TmpF5, TmpY3, TmpR0, TmpQ0, TmpPR };
254 Result = CurDAG->getTargetNode(IA64::TCFMADS0, MVT::f64, // d.p. s0 rndg!
256 Chain = SDOperand(Result, 1);
257 return Result; // XXX: early exit!
258 } else { // this is *not* an FP divide, so there's a bit left to do:
260 SDOperand TmpQ2, TmpR2, TmpQ3, TmpQ;
262 SDOperand OpsQ2[] = { TmpF3, TmpY2, F0, TmpPR };
263 TmpQ2 = SDOperand(CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
265 Chain = TmpQ2.getValue(1);
266 SDOperand OpsR2[] = { TmpF4, TmpQ2, TmpF3, TmpPR };
267 TmpR2 = SDOperand(CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
269 Chain = TmpR2.getValue(1);
271 // we want TmpQ3 to have the same target register as the frcpa? maybe we
272 // should two-address hack it. See the comment "for this to work..." on page
273 // 48 of Intel application note #245415
274 SDOperand OpsQ3[] = { TmpF5, TmpR2, TmpY2, TmpQ2, TmpPR };
275 TmpQ3 = SDOperand(CurDAG->getTargetNode(IA64::TCFMAS1, MVT::f64,
277 Chain = TmpQ3.getValue(1);
279 // STORY: without these two-address instructions (TCFMAS1 and TCFMADS0)
280 // the FPSWA won't be able to help out in the case of large/tiny
281 // arguments. Other fun bugs may also appear, e.g. 0/x = x, not 0.
284 TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1,
285 MVT::f64, TmpQ3), 0);
287 TmpQ = SDOperand(CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1,
288 MVT::f64, TmpQ3), 0);
290 Chain = TmpQ.getValue(1);
294 SDOperand(CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, minusB), 0);
295 Chain = FPminusB.getValue(1);
296 SDOperand Remainder =
297 SDOperand(CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
298 TmpQ, FPminusB, TmpF1), 0);
299 Chain = Remainder.getValue(1);
300 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, Remainder);
301 Chain = SDOperand(Result, 1);
302 } else { // just an integer divide
303 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpQ);
304 Chain = SDOperand(Result, 1);
308 } // wasn't an FP divide
311 // Select - Convert the specified operand from a target-independent to a
312 // target-specific node if it hasn't already been changed.
313 SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
315 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
316 N->getOpcode() < IA64ISD::FIRST_NUMBER)
317 return NULL; // Already selected.
319 switch (N->getOpcode()) {
322 case IA64ISD::BRCALL: { // XXX: this is also a hack!
323 SDOperand Chain = N->getOperand(0);
324 SDOperand InFlag; // Null incoming flag value.
326 AddToISelQueue(Chain);
327 if(N->getNumOperands()==3) { // we have an incoming chain, callee and flag
328 InFlag = N->getOperand(2);
329 AddToISelQueue(InFlag);
333 SDOperand CallOperand;
335 // if we can call directly, do so
336 if (GlobalAddressSDNode *GASD =
337 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) {
338 CallOpcode = IA64::BRCALL_IPREL_GA;
339 CallOperand = CurDAG->getTargetGlobalAddress(GASD->getGlobal(), MVT::i64);
340 } else if (ExternalSymbolSDNode *ESSDN = // FIXME: we currently NEED this
341 // case for correctness, to avoid
342 // "non-pic code with imm reloc.n
343 // against dynamic symbol" errors
344 dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) {
345 CallOpcode = IA64::BRCALL_IPREL_ES;
346 CallOperand = N->getOperand(1);
348 // otherwise we need to load the function descriptor,
349 // load the branch target (function)'s entry point and GP,
350 // branch (call) then restore the GP
351 SDOperand FnDescriptor = N->getOperand(1);
352 AddToISelQueue(FnDescriptor);
354 // load the branch target's entry point [mem] and
356 SDOperand targetEntryPoint=
357 SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, FnDescriptor), 0);
358 Chain = targetEntryPoint.getValue(1);
359 SDOperand targetGPAddr=
360 SDOperand(CurDAG->getTargetNode(IA64::ADDS, MVT::i64,
361 FnDescriptor, CurDAG->getConstant(8, MVT::i64)), 0);
362 Chain = targetGPAddr.getValue(1);
364 SDOperand(CurDAG->getTargetNode(IA64::LD8, MVT::i64, targetGPAddr), 0);
365 Chain = targetGP.getValue(1);
367 Chain = CurDAG->getCopyToReg(Chain, IA64::r1, targetGP, InFlag);
368 InFlag = Chain.getValue(1);
369 Chain = CurDAG->getCopyToReg(Chain, IA64::B6, targetEntryPoint, InFlag); // FLAG these?
370 InFlag = Chain.getValue(1);
372 CallOperand = CurDAG->getRegister(IA64::B6, MVT::i64);
373 CallOpcode = IA64::BRCALL_INDIRECT;
376 // Finally, once everything is setup, emit the call itself
378 Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
379 CallOperand, InFlag), 0);
380 else // there might be no arguments
381 Chain = SDOperand(CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag,
382 CallOperand, Chain), 0);
383 InFlag = Chain.getValue(1);
385 std::vector<SDOperand> CallResults;
387 CallResults.push_back(Chain);
388 CallResults.push_back(InFlag);
390 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
391 ReplaceUses(Op.getValue(i), CallResults[i]);
395 case IA64ISD::GETFD: {
396 SDOperand Input = N->getOperand(0);
397 AddToISelQueue(Input);
398 return CurDAG->getTargetNode(IA64::GETFD, MVT::i64, Input);
406 return SelectDIV(Op);
408 case ISD::TargetConstantFP: {
409 SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
412 if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0)) {
413 V = CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
414 } else if (cast<ConstantFPSDNode>(N)->isExactlyValue(+1.0)) {
415 V = CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
417 assert(0 && "Unexpected FP constant!");
419 ReplaceUses(SDOperand(N, 0), V);
423 case ISD::FrameIndex: { // TODO: reduce creepyness
424 int FI = cast<FrameIndexSDNode>(N)->getIndex();
426 return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
427 CurDAG->getTargetFrameIndex(FI, MVT::i64));
429 return CurDAG->getTargetNode(IA64::MOV, MVT::i64,
430 CurDAG->getTargetFrameIndex(FI, MVT::i64));
433 case ISD::ConstantPool: { // TODO: nuke the constant pool
434 // (ia64 doesn't need one)
435 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(N);
436 Constant *C = CP->getConstVal();
437 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64,
439 return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
440 CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
443 case ISD::GlobalAddress: {
444 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
445 SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
446 SDOperand Tmp = SDOperand(CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
447 CurDAG->getRegister(IA64::r1, MVT::i64), GA), 0);
448 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
451 /* XXX case ISD::ExternalSymbol: {
452 SDOperand EA = CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(),
454 SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
455 CurDAG->getRegister(IA64::r1, MVT::i64), EA);
456 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
460 case ISD::LOAD: { // FIXME: load -1, not 1, for bools?
461 LoadSDNode *LD = cast<LoadSDNode>(N);
462 SDOperand Chain = LD->getChain();
463 SDOperand Address = LD->getBasePtr();
464 AddToISelQueue(Chain);
465 AddToISelQueue(Address);
467 MVT::ValueType TypeBeingLoaded = LD->getLoadedVT();
469 switch (TypeBeingLoaded) {
474 assert(0 && "Cannot load this type!");
475 case MVT::i1: { // this is a bool
476 Opc = IA64::LD1; // first we load a byte, then compare for != 0
477 if(N->getValueType(0) == MVT::i1) { // XXX: early exit!
478 return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
479 SDOperand(CurDAG->getTargetNode(Opc, MVT::i64, Address), 0),
480 CurDAG->getRegister(IA64::r0, MVT::i64),
483 /* otherwise, we want to load a bool into something bigger: LD1
484 will do that for us, so we just fall through */
486 case MVT::i8: Opc = IA64::LD1; break;
487 case MVT::i16: Opc = IA64::LD2; break;
488 case MVT::i32: Opc = IA64::LD4; break;
489 case MVT::i64: Opc = IA64::LD8; break;
491 case MVT::f32: Opc = IA64::LDF4; break;
492 case MVT::f64: Opc = IA64::LDF8; break;
495 // TODO: comment this
496 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
501 StoreSDNode *ST = cast<StoreSDNode>(N);
502 SDOperand Address = ST->getBasePtr();
503 SDOperand Chain = ST->getChain();
504 AddToISelQueue(Address);
505 AddToISelQueue(Chain);
508 if (ISD::isNON_TRUNCStore(N)) {
509 switch (N->getOperand(1).getValueType()) {
510 default: assert(0 && "unknown type in store");
511 case MVT::i1: { // this is a bool
512 Opc = IA64::ST1; // we store either 0 or 1 as a byte
514 SDOperand Initial = CurDAG->getCopyFromReg(Chain, IA64::r0, MVT::i64);
515 Chain = Initial.getValue(1);
516 // then load 1 into the same reg iff the predicate to store is 1
517 SDOperand Tmp = ST->getValue();
519 Tmp = SDOperand(CurDAG->getTargetNode(IA64::TPCADDS, MVT::i64, Initial,
520 CurDAG->getConstant(1, MVT::i64),
522 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
524 case MVT::i64: Opc = IA64::ST8; break;
525 case MVT::f64: Opc = IA64::STF8; break;
527 } else { // Truncating store
528 switch(ST->getStoredVT()) {
529 default: assert(0 && "unknown type in truncstore");
530 case MVT::i8: Opc = IA64::ST1; break;
531 case MVT::i16: Opc = IA64::ST2; break;
532 case MVT::i32: Opc = IA64::ST4; break;
533 case MVT::f32: Opc = IA64::STF4; break;
537 SDOperand N1 = N->getOperand(1);
538 SDOperand N2 = N->getOperand(2);
541 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, N2, N1, Chain);
545 SDOperand Chain = N->getOperand(0);
546 SDOperand CC = N->getOperand(1);
547 AddToISelQueue(Chain);
549 MachineBasicBlock *Dest =
550 cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
551 //FIXME - we do NOT need long branches all the time
552 return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
553 CurDAG->getBasicBlock(Dest), Chain);
556 case ISD::CALLSEQ_START:
557 case ISD::CALLSEQ_END: {
558 int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
559 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
560 IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
561 SDOperand N0 = N->getOperand(0);
563 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, getI64Imm(Amt), N0);
567 // FIXME: we don't need long branches all the time!
568 SDOperand N0 = N->getOperand(0);
570 return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
571 N->getOperand(1), N0);
574 return SelectCode(Op);
578 /// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG
579 /// into an IA64-specific DAG, ready for instruction scheduling.
582 *llvm::createIA64DAGToDAGInstructionSelector(IA64TargetMachine &TM) {
583 return new IA64DAGToDAGISel(TM);