1 //===---- IA64ISelDAGToDAG.cpp - IA64 pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for IA64,
11 // converting a legalized dag to an IA64 dag.
13 //===----------------------------------------------------------------------===//
16 #include "IA64TargetMachine.h"
17 #include "IA64ISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/Target/TargetOptions.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/Constants.h"
26 #include "llvm/GlobalValue.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/MathExtras.h"
32 Statistic<> FusedFP ("ia64-codegen", "Number of fused fp operations");
33 Statistic<> FrameOff("ia64-codegen", "Number of frame idx offsets collapsed");
35 //===--------------------------------------------------------------------===//
36 /// IA64DAGToDAGISel - IA64 specific code to select IA64 machine
37 /// instructions for SelectionDAG operations.
39 class IA64DAGToDAGISel : public SelectionDAGISel {
40 IA64TargetLowering IA64Lowering;
41 unsigned GlobalBaseReg;
43 IA64DAGToDAGISel(TargetMachine &TM)
44 : SelectionDAGISel(IA64Lowering), IA64Lowering(TM) {}
46 virtual bool runOnFunction(Function &Fn) {
47 // Make sure we re-emit a set of the global base reg if necessary
49 return SelectionDAGISel::runOnFunction(Fn);
52 /// getI64Imm - Return a target constant with the specified value, of type
54 inline SDOperand getI64Imm(uint64_t Imm) {
55 return CurDAG->getTargetConstant(Imm, MVT::i64);
58 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
59 /// base register. Return the virtual register that holds this value.
60 // SDOperand getGlobalBaseReg(); TODO: hmm
62 // Select - Convert the specified operand from a target-independent to a
63 // target-specific node if it hasn't already been changed.
64 SDOperand Select(SDOperand Op);
66 SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
67 unsigned OCHi, unsigned OCLo,
68 bool IsArithmetic = false,
70 SDNode *SelectBitfieldInsert(SDNode *N);
72 /// SelectCC - Select a comparison of the specified values with the
73 /// specified condition code, returning the CR# of the expression.
74 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
76 /// SelectAddr - Given the specified address, return the two operands for a
77 /// load/store instruction, and return true if it should be an indexed [r+r]
79 bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2);
81 SDOperand BuildSDIVSequence(SDNode *N);
82 SDOperand BuildUDIVSequence(SDNode *N);
84 /// InstructionSelectBasicBlock - This callback is invoked by
85 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
86 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
88 virtual const char *getPassName() const {
89 return "IA64 (Itanium) DAG->DAG Instruction Selector";
92 // Include the pieces autogenerated from the target description.
93 #include "IA64GenDAGISel.inc"
96 SDOperand SelectDIV(SDOperand Op);
100 /// InstructionSelectBasicBlock - This callback is invoked by
101 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
102 void IA64DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
105 // The selection process is inherently a bottom-up recursive process (users
106 // select their uses before themselves). Given infinite stack space, we
107 // could just start selecting on the root and traverse the whole graph. In
108 // practice however, this causes us to run out of stack space on large basic
109 // blocks. To avoid this problem, select the entry node, then all its uses,
110 // iteratively instead of recursively.
111 std::vector<SDOperand> Worklist;
112 Worklist.push_back(DAG.getEntryNode());
114 // Note that we can do this in the IA64 target (scanning forward across token
115 // chain edges) because no nodes ever get folded across these edges. On a
116 // target like X86 which supports load/modify/store operations, this would
117 // have to be more careful.
118 while (!Worklist.empty()) {
119 SDOperand Node = Worklist.back();
122 // Chose from the least deep of the top two nodes.
123 if (!Worklist.empty() &&
124 Worklist.back().Val->getNodeDepth() < Node.Val->getNodeDepth())
125 std::swap(Worklist.back(), Node);
127 if ((Node.Val->getOpcode() >= ISD::BUILTIN_OP_END &&
128 Node.Val->getOpcode() < IA64ISD::FIRST_NUMBER) ||
129 CodeGenMap.count(Node)) continue;
131 for (SDNode::use_iterator UI = Node.Val->use_begin(),
132 E = Node.Val->use_end(); UI != E; ++UI) {
133 // Scan the values. If this use has a value that is a token chain, add it
136 for (unsigned i = 0, e = User->getNumValues(); i != e; ++i)
137 if (User->getValueType(i) == MVT::Other) {
138 Worklist.push_back(SDOperand(User, i));
143 // Finally, legalize this node.
147 // Select target instructions for the DAG.
148 DAG.setRoot(Select(DAG.getRoot()));
150 DAG.RemoveDeadNodes();
152 // Emit machine code to BB.
153 ScheduleAndEmitDAG(DAG);
156 SDOperand IA64DAGToDAGISel::SelectDIV(SDOperand Op) {
158 SDOperand Chain = Select(N->getOperand(0));
160 SDOperand Tmp1 = Select(N->getOperand(0));
161 SDOperand Tmp2 = Select(N->getOperand(1));
165 if(MVT::isFloatingPoint(Tmp1.getValueType()))
168 bool isModulus=false; // is it a division or a modulus?
171 switch(N->getOpcode()) {
173 case ISD::SDIV: isModulus=false; isSigned=true; break;
174 case ISD::UDIV: isModulus=false; isSigned=false; break;
176 case ISD::SREM: isModulus=true; isSigned=true; break;
177 case ISD::UREM: isModulus=true; isSigned=false; break;
180 // TODO: check for integer divides by powers of 2 (or other simple patterns?)
182 SDOperand TmpPR, TmpPR2;
183 SDOperand TmpF1, TmpF2, TmpF3, TmpF4, TmpF5, TmpF6, TmpF7, TmpF8;
184 SDOperand TmpF9, TmpF10,TmpF11,TmpF12,TmpF13,TmpF14,TmpF15;
187 // OK, emit some code:
190 // first, load the inputs into FP regs.
191 TmpF1 = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp1);
192 Chain = TmpF1.getValue(1);
193 TmpF2 = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, Tmp2);
194 Chain = TmpF2.getValue(1);
196 // next, convert the inputs to FP
198 TmpF3 = CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF1);
199 Chain = TmpF3.getValue(1);
200 TmpF4 = CurDAG->getTargetNode(IA64::FCVTXF, MVT::f64, TmpF2);
201 Chain = TmpF4.getValue(1);
203 TmpF3 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF1);
204 Chain = TmpF3.getValue(1);
205 TmpF4 = CurDAG->getTargetNode(IA64::FCVTXUFS1, MVT::f64, TmpF2);
206 Chain = TmpF4.getValue(1);
209 } else { // this is an FP divide/remainder, so we 'leak' some temp
210 // regs and assign TmpF3=Tmp1, TmpF4=Tmp2
215 // we start by computing an approximate reciprocal (good to 9 bits?)
216 // note, this instruction writes _both_ TmpF5 (answer) and TmpPR (predicate)
217 TmpF5 = CurDAG->getTargetNode(IA64::FRCPAS1, MVT::f64, MVT::i1,
219 TmpPR = TmpF5.getValue(1);
220 Chain = TmpF5.getValue(2);
222 if(!isModulus) { // if this is a divide, we worry about div-by-zero
223 SDOperand bogusPR = CurDAG->getTargetNode(IA64::CMPEQ, MVT::i1,
224 CurDAG->getRegister(IA64::r0, MVT::i64),
225 CurDAG->getRegister(IA64::r0, MVT::i64));
226 Chain = bogusPR.getValue(1);
227 TmpPR2 = CurDAG->getTargetNode(IA64::TPCMPNE, MVT::i1, bogusPR,
228 CurDAG->getRegister(IA64::r0, MVT::i64),
229 CurDAG->getRegister(IA64::r0, MVT::i64), TmpPR);
230 Chain = TmpPR2.getValue(1);
233 SDOperand F0 = CurDAG->getRegister(IA64::F0, MVT::f64);
234 SDOperand F1 = CurDAG->getRegister(IA64::F1, MVT::f64);
236 // now we apply newton's method, thrice! (FIXME: this is ~72 bits of
237 // precision, don't need this much for f32/i32)
238 TmpF6 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
239 TmpF4, TmpF5, F1, TmpPR);
240 Chain = TmpF6.getValue(1);
241 TmpF7 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
242 TmpF3, TmpF5, F0, TmpPR);
243 Chain = TmpF7.getValue(1);
244 TmpF8 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
245 TmpF6, TmpF6, F0, TmpPR);
246 Chain = TmpF8.getValue(1);
247 TmpF9 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
248 TmpF6, TmpF7, TmpF7, TmpPR);
249 Chain = TmpF9.getValue(1);
250 TmpF10 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
251 TmpF6, TmpF5, TmpF5, TmpPR);
252 Chain = TmpF10.getValue(1);
253 TmpF11 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
254 TmpF8, TmpF9, TmpF9, TmpPR);
255 Chain = TmpF11.getValue(1);
256 TmpF12 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
257 TmpF8, TmpF10, TmpF10, TmpPR);
258 Chain = TmpF12.getValue(1);
259 TmpF13 = CurDAG->getTargetNode(IA64::CFNMAS1, MVT::f64,
260 TmpF4, TmpF11, TmpF3, TmpPR);
261 Chain = TmpF13.getValue(1);
263 // FIXME: this is unfortunate :(
264 // the story is that the dest reg of the fnma above and the fma below
265 // (and therefore possibly the src of the fcvt.fx[u] as well) cannot
266 // be the same register, or this code breaks if the first argument is
267 // zero. (e.g. without this hack, 0%8 yields -64, not 0.)
268 TmpF14 = CurDAG->getTargetNode(IA64::CFMAS1, MVT::f64,
269 TmpF13, TmpF12, TmpF11, TmpPR);
270 Chain = TmpF14.getValue(1);
272 if(isModulus) { // XXX: fragile! fixes _only_ mod, *breaks* div! !
273 SDOperand bogus = CurDAG->getTargetNode(IA64::IUSE, MVT::Other, TmpF13); // hack :(
274 Chain = bogus.getValue(0); // hmmm
278 // round to an integer
280 TmpF15 = CurDAG->getTargetNode(IA64::FCVTFXTRUNCS1, MVT::i64, TmpF14);
281 Chain = TmpF15.getValue(1);
284 TmpF15 = CurDAG->getTargetNode(IA64::FCVTFXUTRUNCS1, MVT::i64, TmpF14);
285 Chain = TmpF15.getValue(1);
289 // EXERCISE: can you see why TmpF15=TmpF14 does not work here, and
290 // we really do need the above FMOV? ;)
294 if(isFP) { // extra worrying about div-by-zero
295 // we do a 'conditional fmov' (of the correct result, depending
296 // on how the frcpa predicate turned out)
297 SDOperand bogoResult = CurDAG->getTargetNode(IA64::PFMOV, MVT::f64,
299 Chain = bogoResult.getValue(1);
300 Result = CurDAG->getTargetNode(IA64::CFMOV, MVT::f64, bogoResult,
302 Chain = Result.getValue(1);
305 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, TmpF15);
306 Chain = Result.getValue(1);
308 } else { // this is a modulus
310 // answer = q * (-b) + a
311 SDOperand TmpI = CurDAG->getTargetNode(IA64::SUB, MVT::i64,
312 CurDAG->getRegister(IA64::r0, MVT::i64), Tmp2);
313 Chain = TmpI.getValue(1);
314 SDOperand TmpF = CurDAG->getTargetNode(IA64::SETFSIG, MVT::f64, TmpI);
315 Chain = TmpF.getValue(1);
316 SDOperand ModulusResult = CurDAG->getTargetNode(IA64::XMAL, MVT::f64,
317 TmpF15, TmpF, TmpF1);
318 Chain = ModulusResult.getValue(1);
319 Result = CurDAG->getTargetNode(IA64::GETFSIG, MVT::i64, ModulusResult);
320 Chain = Result.getValue(1);
321 } else { // FP modulus! The horror... the horror....
322 assert(0 && "sorry, no FP modulus just yet!\n!\n");
329 // Select - Convert the specified operand from a target-independent to a
330 // target-specific node if it hasn't already been changed.
331 SDOperand IA64DAGToDAGISel::Select(SDOperand Op) {
333 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
334 N->getOpcode() < IA64ISD::FIRST_NUMBER)
335 return Op; // Already selected.
337 // If this has already been converted, use it.
338 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
339 if (CGMI != CodeGenMap.end()) return CGMI->second;
341 switch (N->getOpcode()) {
344 case ISD::Register: return Op; // XXX: this is a hack, tblgen one day?
346 case IA64ISD::GETFD: {
347 SDOperand Input = Select(N->getOperand(0));
348 SDOperand Result = CurDAG->getTargetNode(IA64::GETFD, MVT::i64, MVT::Flag, Input);
349 CodeGenMap[Op.getValue(0)] = Result;
350 CodeGenMap[Op.getValue(1)] = Result.getValue(1);
351 return Result.getValue(Op.ResNo);
355 case ISD::TAILCALL: { {
356 // FIXME: This is a workaround for a bug in tblgen.
357 // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag)
358 // Emits: (CALL:void (tglobaladdr:i32):$dst)
359 // Pattern complexity = 2 cost = 1
360 SDOperand N1 = N->getOperand(1);
361 if (N1.getOpcode() != ISD::TargetGlobalAddress &&
362 N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail;
363 SDOperand InFlag = SDOperand(0, 0);
364 SDOperand Chain = N->getOperand(0);
366 Chain = Select(Chain);
368 if (N->getNumOperands() == 3) {
369 InFlag = Select(N->getOperand(2));
370 Result = CurDAG->getTargetNode(IA64::BRCALL, MVT::Other, MVT::Flag, Tmp0,
373 Result = CurDAG->getTargetNode(IA64::BRCALL, MVT::Other, MVT::Flag, Tmp0,
376 Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0);
377 CodeGenMap[SDOperand(N, 1)] = Result.getValue(1);
378 return Result.getValue(Op.ResNo);
388 case ISD::UREM: return SelectDIV(Op);
390 case ISD::DYNAMIC_STACKALLOC: {
391 if (!isa<ConstantSDNode>(N->getOperand(2)) ||
392 cast<ConstantSDNode>(N->getOperand(2))->getValue() != 0) {
393 std::cerr << "Cannot allocate stack object with greater alignment than"
394 << " the stack alignment yet!";
398 SDOperand Chain = Select(N->getOperand(0));
399 SDOperand Amt = Select(N->getOperand(1));
400 SDOperand Reg = CurDAG->getRegister(IA64::r12, MVT::i64);
401 SDOperand Val = CurDAG->getCopyFromReg(Chain, IA64::r12, MVT::i64);
402 Chain = Val.getValue(1);
404 // Subtract the amount (guaranteed to be a multiple of the stack alignment)
405 // from the stack pointer, giving us the result pointer.
406 SDOperand Result = Select(CurDAG->getNode(ISD::SUB, MVT::i64, Val, Amt));
408 // Copy this result back into r12.
409 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, Reg, Result);
411 // Copy this result back out of r12 to make sure we're not using the stack
412 // space without decrementing the stack pointer.
413 Result = CurDAG->getCopyFromReg(Chain, IA64::r12, MVT::i64);
415 // Finally, replace the DYNAMIC_STACKALLOC with the copyfromreg.
416 CodeGenMap[Op.getValue(0)] = Result;
417 CodeGenMap[Op.getValue(1)] = Result.getValue(1);
418 return SDOperand(Result.Val, Op.ResNo);
421 case ISD::ConstantFP: {
422 SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
424 if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0))
425 return CurDAG->getCopyFromReg(Chain, IA64::F0, MVT::f64);
426 else if (cast<ConstantFPSDNode>(N)->isExactlyValue(+1.0))
427 return CurDAG->getCopyFromReg(Chain, IA64::F1, MVT::f64);
429 assert(0 && "Unexpected FP constant!");
432 case ISD::FrameIndex: { // TODO: reduce creepyness
433 int FI = cast<FrameIndexSDNode>(N)->getIndex();
435 return CurDAG->SelectNodeTo(N, IA64::MOV, MVT::i64,
436 CurDAG->getTargetFrameIndex(FI, MVT::i64));
437 return CurDAG->getTargetNode(IA64::MOV, MVT::i64,
438 CurDAG->getTargetFrameIndex(FI, MVT::i64));
441 case ISD::ConstantPool: {
442 Constant *C = cast<ConstantPoolSDNode>(N)->get();
443 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
444 return CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64, // ?
445 CurDAG->getRegister(IA64::r1, MVT::i64), CPI);
448 case ISD::GlobalAddress: {
449 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
450 SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i64);
451 SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_GA, MVT::i64,
452 CurDAG->getRegister(IA64::r1, MVT::i64), GA);
453 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
456 /* XXX case ISD::ExternalSymbol: {
457 SDOperand EA = CurDAG->getTargetExternalSymbol(cast<ExternalSymbolSDNode>(N)->getSymbol(),
459 SDOperand Tmp = CurDAG->getTargetNode(IA64::ADDL_EA, MVT::i64,
460 CurDAG->getRegister(IA64::r1, MVT::i64), EA);
461 return CurDAG->getTargetNode(IA64::LD8, MVT::i64, Tmp);
467 case ISD::ZEXTLOAD: {
468 SDOperand Chain = Select(N->getOperand(0));
469 SDOperand Address = Select(N->getOperand(1));
471 MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ?
472 N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT();
474 switch (TypeBeingLoaded) {
475 default: N->dump(); assert(0 && "Cannot load this type!");
476 case MVT::i1: { // this is a bool
477 Opc = IA64::LD1; // first we load a byte, then compare for != 0
478 if(N->getValueType(0) == MVT::i1) // XXX: early exit!
479 return CurDAG->SelectNodeTo(N, IA64::CMPNE, MVT::i1, MVT::Other,
480 CurDAG->getTargetNode(Opc, MVT::i64, Address),
481 CurDAG->getRegister(IA64::r0, MVT::i64),
482 Chain).getValue(Op.ResNo);
483 /* otherwise, we want to load a bool into something bigger: LD1
484 will do that for us, so we just fall through */
486 case MVT::i8: Opc = IA64::LD1; break;
487 case MVT::i16: Opc = IA64::LD2; break;
488 case MVT::i32: Opc = IA64::LD4; break;
489 case MVT::i64: Opc = IA64::LD8; break;
491 case MVT::f32: Opc = IA64::LDF4; break;
492 case MVT::f64: Opc = IA64::LDF8; break;
495 // TODO: comment this
496 return CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other,
497 Address, Chain).getValue(Op.ResNo);
500 case ISD::TRUNCSTORE:
502 SDOperand Address = Select(N->getOperand(2));
503 SDOperand Chain = Select(N->getOperand(0));
506 if (N->getOpcode() == ISD::STORE) {
507 switch (N->getOperand(1).getValueType()) {
508 default: assert(0 && "unknown type in store");
509 case MVT::i1: { // this is a bool
510 Opc = IA64::ST1; // we store either 0 or 1 as a byte
512 CurDAG->getTargetNode(IA64::PADDS, MVT::i64,
513 CurDAG->getRegister(IA64::r0, MVT::i64),
514 CurDAG->getConstant(1, MVT::i64),
515 Select(N->getOperand(1)));
516 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Address, Tmp, Chain);
518 case MVT::i64: Opc = IA64::ST8; break;
519 case MVT::f64: Opc = IA64::STF8; break;
521 } else { //ISD::TRUNCSTORE
522 switch(cast<VTSDNode>(N->getOperand(4))->getVT()) {
523 default: assert(0 && "unknown type in truncstore");
524 case MVT::i8: Opc = IA64::ST1; break;
525 case MVT::i16: Opc = IA64::ST2; break;
526 case MVT::i32: Opc = IA64::ST4; break;
527 case MVT::f32: Opc = IA64::STF4; break;
531 return CurDAG->SelectNodeTo(N, Opc, MVT::Other, Select(N->getOperand(2)),
532 Select(N->getOperand(1)), Chain);
536 SDOperand Chain = Select(N->getOperand(0));
537 SDOperand CC = Select(N->getOperand(1));
538 MachineBasicBlock *Dest =
539 cast<BasicBlockSDNode>(N->getOperand(2))->getBasicBlock();
540 //FIXME - we do NOT need long branches all the time
541 return CurDAG->SelectNodeTo(N, IA64::BRLCOND_NOTCALL, MVT::Other, CC,
542 CurDAG->getBasicBlock(Dest), Chain);
545 case ISD::CALLSEQ_START:
546 case ISD::CALLSEQ_END: {
547 int64_t Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
548 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
549 IA64::ADJUSTCALLSTACKDOWN : IA64::ADJUSTCALLSTACKUP;
550 return CurDAG->SelectNodeTo(N, Opc, MVT::Other,
551 getI64Imm(Amt), Select(N->getOperand(0)));
555 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
558 switch (N->getNumOperands()) {
560 assert(0 && "Unknown return instruction!");
562 SDOperand RetVal = Select(N->getOperand(1));
563 switch (RetVal.getValueType()) {
564 default: assert(0 && "I don't know how to return this type! (promote?)");
565 // FIXME: do I need to add support for bools here?
566 // (return '0' or '1' in r8, basically...)
568 // FIXME: need to round floats - 80 bits is bad, the tester
571 // we mark r8 as live on exit up above in LowerArguments()
572 // BuildMI(BB, IA64::MOV, 1, IA64::r8).addReg(Tmp1);
573 Chain = CurDAG->getCopyToReg(Chain, IA64::r8, RetVal);
574 InFlag = Chain.getValue(1);
577 // we mark F8 as live on exit up above in LowerArguments()
578 // BuildMI(BB, IA64::FMOV, 1, IA64::F8).addReg(Tmp1);
579 Chain = CurDAG->getCopyToReg(Chain, IA64::F8, RetVal);
580 InFlag = Chain.getValue(1);
589 // we need to copy VirtGPR (the vreg (to become a real reg)) that holds
590 // the output of this function's alloc instruction back into ar.pfs
591 // before we return. this copy must not float up above the last
592 // outgoing call in this function!!!
593 SDOperand AR_PFSVal = CurDAG->getCopyFromReg(Chain, IA64Lowering.VirtGPR,
595 Chain = AR_PFSVal.getValue(1);
596 Chain = CurDAG->getCopyToReg(Chain, IA64::AR_PFS, AR_PFSVal);
598 // and then just emit a 'ret' instruction
599 // before returning, restore the ar.pfs register (set by the 'alloc' up top)
600 // BuildMI(BB, IA64::MOV, 1).addReg(IA64::AR_PFS).addReg(IA64Lowering.VirtGPR);
602 return CurDAG->SelectNodeTo(N, IA64::RET, MVT::Other, Chain);
606 // FIXME: we don't need long branches all the time!
607 return CurDAG->SelectNodeTo(N, IA64::BRL_NOTCALL, MVT::Other,
608 N->getOperand(1), Select(N->getOperand(0)));
611 return SelectCode(Op);
615 /// createIA64DAGToDAGInstructionSelector - This pass converts a legalized DAG
616 /// into an IA64-specific DAG, ready for instruction scheduling.
618 FunctionPass *llvm::createIA64DAGToDAGInstructionSelector(TargetMachine &TM) {
619 return new IA64DAGToDAGISel(TM);