1 //===-- IA64ISelLowering.cpp - IA64 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the IA64ISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "IA64ISelLowering.h"
15 #include "IA64MachineFunctionInfo.h"
16 #include "IA64TargetMachine.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
26 IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
27 : TargetLowering(TM) {
29 // register class for general registers
30 addRegisterClass(MVT::i64, IA64::GRRegisterClass);
32 // register class for FP registers
33 addRegisterClass(MVT::f64, IA64::FPRegisterClass);
35 // register class for predicate registers
36 addRegisterClass(MVT::i1, IA64::PRRegisterClass);
38 setLoadXAction(ISD::EXTLOAD , MVT::i1 , Promote);
40 setLoadXAction(ISD::ZEXTLOAD , MVT::i1 , Promote);
42 setLoadXAction(ISD::SEXTLOAD , MVT::i1 , Promote);
43 setLoadXAction(ISD::SEXTLOAD , MVT::i8 , Expand);
44 setLoadXAction(ISD::SEXTLOAD , MVT::i16 , Expand);
45 setLoadXAction(ISD::SEXTLOAD , MVT::i32 , Expand);
47 setOperationAction(ISD::BRIND , MVT::Other, Expand);
48 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
49 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
50 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
52 // ia64 uses SELECT not SELECT_CC
53 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
55 // We need to handle ISD::RET for void functions ourselves,
56 // so we get a chance to restore ar.pfs before adding a
58 setOperationAction(ISD::RET, MVT::Other, Custom);
60 setShiftAmountType(MVT::i64);
62 setOperationAction(ISD::FREM , MVT::f32 , Expand);
63 setOperationAction(ISD::FREM , MVT::f64 , Expand);
65 setOperationAction(ISD::UREM , MVT::f32 , Expand);
66 setOperationAction(ISD::UREM , MVT::f64 , Expand);
68 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
70 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
71 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
73 // We don't support sin/cos/sqrt/pow
74 setOperationAction(ISD::FSIN , MVT::f64, Expand);
75 setOperationAction(ISD::FCOS , MVT::f64, Expand);
76 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
77 setOperationAction(ISD::FPOW , MVT::f64, Expand);
78 setOperationAction(ISD::FSIN , MVT::f32, Expand);
79 setOperationAction(ISD::FCOS , MVT::f32, Expand);
80 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
81 setOperationAction(ISD::FPOW , MVT::f32, Expand);
83 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
85 // FIXME: IA64 supports fcopysign natively!
86 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
87 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
89 // We don't have line number support yet.
90 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
91 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
92 setOperationAction(ISD::LABEL, MVT::Other, Expand);
94 // IA64 has ctlz in the form of the 'fnorm' instruction. The Legalizer
95 // expansion for ctlz/cttz in terms of ctpop is much larger, but lower
97 // FIXME: Custom lower CTLZ when compiling for size?
98 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
99 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
100 setOperationAction(ISD::ROTL , MVT::i64 , Expand);
101 setOperationAction(ISD::ROTR , MVT::i64 , Expand);
103 // FIXME: IA64 has this, but is not implemented. should be mux @rev
104 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
106 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
107 setOperationAction(ISD::VAARG , MVT::Other, Custom);
108 setOperationAction(ISD::VASTART , MVT::Other, Custom);
110 // Use the default implementation.
111 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
112 setOperationAction(ISD::VAEND , MVT::Other, Expand);
113 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
114 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
115 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
117 // Thread Local Storage
118 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
120 setStackPointerRegisterToSaveRestore(IA64::r12);
122 setJumpBufSize(704); // on ia64-linux, jmp_bufs are 704 bytes..
123 setJumpBufAlignment(16); // ...and must be 16-byte aligned
125 computeRegisterProperties();
127 addLegalFPImmediate(APFloat(+0.0));
128 addLegalFPImmediate(APFloat(-0.0));
129 addLegalFPImmediate(APFloat(+1.0));
130 addLegalFPImmediate(APFloat(-1.0));
133 const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const {
136 case IA64ISD::GETFD: return "IA64ISD::GETFD";
137 case IA64ISD::BRCALL: return "IA64ISD::BRCALL";
138 case IA64ISD::RET_FLAG: return "IA64ISD::RET_FLAG";
142 MVT IA64TargetLowering::getSetCCResultType(const SDOperand &) const {
146 std::vector<SDOperand>
147 IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
148 std::vector<SDOperand> ArgValues;
150 // add beautiful description of IA64 stack frame format
151 // here (from intel 24535803.pdf most likely)
153 MachineFunction &MF = DAG.getMachineFunction();
154 MachineFrameInfo *MFI = MF.getFrameInfo();
155 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
157 GP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
158 SP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
159 RP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
161 MachineBasicBlock& BB = MF.front();
163 unsigned args_int[] = {IA64::r32, IA64::r33, IA64::r34, IA64::r35,
164 IA64::r36, IA64::r37, IA64::r38, IA64::r39};
166 unsigned args_FP[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11,
167 IA64::F12,IA64::F13,IA64::F14, IA64::F15};
173 unsigned used_FPArgs = 0; // how many FP args have been used so far?
175 unsigned ArgOffset = 0;
178 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
180 SDOperand newroot, argt;
181 if(count < 8) { // need to fix this logic? maybe.
183 switch (getValueType(I->getType()).getSimpleVT()) {
185 assert(0 && "ERROR in LowerArgs: can't lower this type of arg.\n");
187 // fixme? (well, will need to for weird FP structy stuff,
188 // see intel ABI docs)
190 //XXX BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]);
191 MF.getRegInfo().addLiveIn(args_FP[used_FPArgs]);
192 // mark this reg as liveIn
193 // floating point args go into f8..f15 as-needed, the increment
194 argVreg[count] = // is below..:
195 MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::f64));
196 // FP args go into f8..f15 as needed: (hence the ++)
197 argPreg[count] = args_FP[used_FPArgs++];
198 argOpc[count] = IA64::FMOV;
199 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count],
201 if (I->getType() == Type::FloatTy)
202 argt = DAG.getNode(ISD::FP_ROUND, MVT::f32, argt,
203 DAG.getIntPtrConstant(0));
205 case MVT::i1: // NOTE: as far as C abi stuff goes,
206 // bools are just boring old ints
211 //XXX BuildMI(&BB, IA64::IDEF, 0, args_int[count]);
212 MF.getRegInfo().addLiveIn(args_int[count]);
213 // mark this register as liveIn
215 MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
216 argPreg[count] = args_int[count];
217 argOpc[count] = IA64::MOV;
219 DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], MVT::i64);
220 if ( getValueType(I->getType()) != MVT::i64)
221 argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()),
225 } else { // more than 8 args go into the frame
226 // Create the frame index object for this incoming parameter...
227 ArgOffset = 16 + 8 * (count - 8);
228 int FI = MFI->CreateFixedObject(8, ArgOffset);
230 // Create the SelectionDAG nodes corresponding to a load
231 //from this parameter
232 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
233 argt = newroot = DAG.getLoad(getValueType(I->getType()),
234 DAG.getEntryNode(), FIN, NULL, 0);
237 DAG.setRoot(newroot.getValue(1));
238 ArgValues.push_back(argt);
242 // Create a vreg to hold the output of (what will become)
243 // the "alloc" instruction
244 VirtGPR = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
245 BuildMI(&BB, TII->get(IA64::PSEUDO_ALLOC), VirtGPR);
246 // we create a PSEUDO_ALLOC (pseudo)instruction for now
248 BuildMI(&BB, IA64::IDEF, 0, IA64::r1);
251 BuildMI(&BB, IA64::IDEF, 0, IA64::r12);
252 BuildMI(&BB, IA64::IDEF, 0, IA64::rp);
255 BuildMI(&BB, IA64::MOV, 1, GP).addReg(IA64::r1);
258 BuildMI(&BB, IA64::MOV, 1, SP).addReg(IA64::r12);
259 BuildMI(&BB, IA64::MOV, 1, RP).addReg(IA64::rp);
263 unsigned tempOffset=0;
265 // if this is a varargs function, we simply lower llvm.va_start by
266 // pointing to the first entry
269 VarArgsFrameIndex = MFI->CreateFixedObject(8, tempOffset);
272 // here we actually do the moving of args, and store them to the stack
273 // too if this is a varargs function:
274 for (int i = 0; i < count && i < 8; ++i) {
275 BuildMI(&BB, TII->get(argOpc[i]), argVreg[i]).addReg(argPreg[i]);
277 // if this is a varargs function, we copy the input registers to the stack
278 int FI = MFI->CreateFixedObject(8, tempOffset);
279 tempOffset+=8; //XXX: is it safe to use r22 like this?
280 BuildMI(&BB, TII->get(IA64::MOV), IA64::r22).addFrameIndex(FI);
281 // FIXME: we should use st8.spill here, one day
282 BuildMI(&BB, TII->get(IA64::ST8), IA64::r22).addReg(argPreg[i]);
286 // Finally, inform the code generator which regs we return values in.
287 // (see the ISD::RET: case in the instruction selector)
288 switch (getValueType(F.getReturnType()).getSimpleVT()) {
289 default: assert(0 && "i have no idea where to return this type!");
290 case MVT::isVoid: break;
296 MF.getRegInfo().addLiveOut(IA64::r8);
300 MF.getRegInfo().addLiveOut(IA64::F8);
307 std::pair<SDOperand, SDOperand>
308 IA64TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
309 bool RetSExt, bool RetZExt,
310 bool isVarArg, unsigned CallingConv,
311 bool isTailCall, SDOperand Callee,
312 ArgListTy &Args, SelectionDAG &DAG) {
314 MachineFunction &MF = DAG.getMachineFunction();
316 unsigned NumBytes = 16;
317 unsigned outRegsUsed = 0;
319 if (Args.size() > 8) {
320 NumBytes += (Args.size() - 8) * 8;
323 outRegsUsed = Args.size();
326 // FIXME? this WILL fail if we ever try to pass around an arg that
327 // consumes more than a single output slot (a 'real' double, int128
328 // some sort of aggregate etc.), as we'll underestimate how many 'outX'
329 // registers we use. Hopefully, the assembler will notice.
330 MF.getInfo<IA64FunctionInfo>()->outRegsUsed=
331 std::max(outRegsUsed, MF.getInfo<IA64FunctionInfo>()->outRegsUsed);
333 // keep stack frame 16-byte aligned
334 // assert(NumBytes==((NumBytes+15) & ~15) &&
335 // "stack frame not 16-byte aligned!");
336 NumBytes = (NumBytes+15) & ~15;
338 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
341 std::vector<SDOperand> Stores;
342 std::vector<SDOperand> Converts;
343 std::vector<SDOperand> RegValuesToPass;
344 unsigned ArgOffset = 16;
346 for (unsigned i = 0, e = Args.size(); i != e; ++i)
348 SDOperand Val = Args[i].Node;
349 MVT ObjectVT = Val.getValueType();
350 SDOperand ValToStore(0, 0), ValToConvert(0, 0);
352 switch (ObjectVT.getSimpleVT()) {
353 default: assert(0 && "unexpected argument type!");
358 //promote to 64-bits, sign/zero extending based on type
360 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
362 ExtendKind = ISD::SIGN_EXTEND;
363 else if (Args[i].isZExt)
364 ExtendKind = ISD::ZERO_EXTEND;
365 Val = DAG.getNode(ExtendKind, MVT::i64, Val);
370 if(RegValuesToPass.size() >= 8) {
373 RegValuesToPass.push_back(Val);
378 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
381 if(RegValuesToPass.size() >= 8) {
384 RegValuesToPass.push_back(Val);
385 if(1 /* TODO: if(calling external or varadic function)*/ ) {
386 ValToConvert = Val; // additionally pass this FP value as an int
394 StackPtr = DAG.getRegister(IA64::r12, MVT::i64);
396 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
397 PtrOff = DAG.getNode(ISD::ADD, MVT::i64, StackPtr, PtrOff);
398 Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
399 ArgOffset += ObjSize;
402 if(ValToConvert.Val) {
403 Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert));
407 // Emit all stores, make sure they occur before any copies into physregs.
409 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size());
411 static const unsigned IntArgRegs[] = {
412 IA64::out0, IA64::out1, IA64::out2, IA64::out3,
413 IA64::out4, IA64::out5, IA64::out6, IA64::out7
416 static const unsigned FPArgRegs[] = {
417 IA64::F8, IA64::F9, IA64::F10, IA64::F11,
418 IA64::F12, IA64::F13, IA64::F14, IA64::F15
423 // save the current GP, SP and RP : FIXME: do we need to do all 3 always?
424 SDOperand GPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r1, MVT::i64, InFlag);
425 Chain = GPBeforeCall.getValue(1);
426 InFlag = Chain.getValue(2);
427 SDOperand SPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r12, MVT::i64, InFlag);
428 Chain = SPBeforeCall.getValue(1);
429 InFlag = Chain.getValue(2);
430 SDOperand RPBeforeCall = DAG.getCopyFromReg(Chain, IA64::rp, MVT::i64, InFlag);
431 Chain = RPBeforeCall.getValue(1);
432 InFlag = Chain.getValue(2);
434 // Build a sequence of copy-to-reg nodes chained together with token chain
435 // and flag operands which copy the outgoing integer args into regs out[0-7]
436 // mapped 1:1 and the FP args into regs F8-F15 "lazily"
437 // TODO: for performance, we should only copy FP args into int regs when we
438 // know this is required (i.e. for varardic or external (unknown) functions)
440 // first to the FP->(integer representation) conversions, these are
441 // flagged for now, but shouldn't have to be (TODO)
442 unsigned seenConverts = 0;
443 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
444 if(RegValuesToPass[i].getValueType().isFloatingPoint()) {
445 Chain = DAG.getCopyToReg(Chain, IntArgRegs[i], Converts[seenConverts++],
447 InFlag = Chain.getValue(1);
451 // next copy args into the usual places, these are flagged
452 unsigned usedFPArgs = 0;
453 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
454 Chain = DAG.getCopyToReg(Chain,
455 RegValuesToPass[i].getValueType().isInteger() ?
456 IntArgRegs[i] : FPArgRegs[usedFPArgs++], RegValuesToPass[i], InFlag);
457 InFlag = Chain.getValue(1);
460 // If the callee is a GlobalAddress node (quite common, every direct call is)
461 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
463 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
464 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i64);
468 std::vector<MVT> NodeTys;
469 std::vector<SDOperand> CallOperands;
470 NodeTys.push_back(MVT::Other); // Returns a chain
471 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
472 CallOperands.push_back(Chain);
473 CallOperands.push_back(Callee);
475 // emit the call itself
477 CallOperands.push_back(InFlag);
479 assert(0 && "this should never happen!\n");
481 // to make way for a hack:
482 Chain = DAG.getNode(IA64ISD::BRCALL, NodeTys,
483 &CallOperands[0], CallOperands.size());
484 InFlag = Chain.getValue(1);
486 // restore the GP, SP and RP after the call
487 Chain = DAG.getCopyToReg(Chain, IA64::r1, GPBeforeCall, InFlag);
488 InFlag = Chain.getValue(1);
489 Chain = DAG.getCopyToReg(Chain, IA64::r12, SPBeforeCall, InFlag);
490 InFlag = Chain.getValue(1);
491 Chain = DAG.getCopyToReg(Chain, IA64::rp, RPBeforeCall, InFlag);
492 InFlag = Chain.getValue(1);
494 std::vector<MVT> RetVals;
495 RetVals.push_back(MVT::Other);
496 RetVals.push_back(MVT::Flag);
498 MVT RetTyVT = getValueType(RetTy);
500 if (RetTyVT != MVT::isVoid) {
501 switch (RetTyVT.getSimpleVT()) {
502 default: assert(0 && "Unknown value type to return!");
503 case MVT::i1: { // bools are just like other integers (returned in r8)
504 // we *could* fall through to the truncate below, but this saves a
505 // few redundant predicate ops
506 SDOperand boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64,InFlag);
507 InFlag = boolInR8.getValue(2);
508 Chain = boolInR8.getValue(1);
509 SDOperand zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag);
510 InFlag = zeroReg.getValue(2);
511 Chain = zeroReg.getValue(1);
513 RetVal = DAG.getSetCC(MVT::i1, boolInR8, zeroReg, ISD::SETNE);
519 RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
520 Chain = RetVal.getValue(1);
522 // keep track of whether it is sign or zero extended (todo: bools?)
524 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
525 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
527 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
530 RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
531 Chain = RetVal.getValue(1);
532 InFlag = RetVal.getValue(2); // XXX dead
535 RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
536 Chain = RetVal.getValue(1);
537 RetVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, RetVal,
538 DAG.getIntPtrConstant(0));
541 RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
542 Chain = RetVal.getValue(1);
543 InFlag = RetVal.getValue(2); // XXX dead
548 Chain = DAG.getCALLSEQ_END(Chain,
549 DAG.getConstant(NumBytes, getPointerTy()),
550 DAG.getConstant(0, getPointerTy()),
552 return std::make_pair(RetVal, Chain);
555 SDOperand IA64TargetLowering::
556 LowerOperation(SDOperand Op, SelectionDAG &DAG) {
557 switch (Op.getOpcode()) {
558 default: assert(0 && "Should not custom lower this!");
559 case ISD::GlobalTLSAddress:
560 assert(0 && "TLS not implemented for IA64.");
562 SDOperand AR_PFSVal, Copy;
564 switch(Op.getNumOperands()) {
566 assert(0 && "Do not know how to return this many arguments!");
569 AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64);
570 AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), IA64::AR_PFS,
572 return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, AR_PFSVal);
574 // Copy the result into the output register & restore ar.pfs
575 MVT ArgVT = Op.getOperand(1).getValueType();
576 unsigned ArgReg = ArgVT.isInteger() ? IA64::r8 : IA64::F8;
578 AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64);
579 Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), ArgReg, Op.getOperand(1),
581 AR_PFSVal = DAG.getCopyToReg(Copy.getValue(0), IA64::AR_PFS, AR_PFSVal,
583 return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other,
584 AR_PFSVal, AR_PFSVal.getValue(1));
590 MVT VT = getPointerTy();
591 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
592 SDOperand VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1),
594 // Increment the pointer, VAList, to the next vaarg
595 SDOperand VAIncr = DAG.getNode(ISD::ADD, VT, VAList,
596 DAG.getConstant(VT.getSizeInBits()/8,
598 // Store the incremented VAList to the legalized pointer
599 VAIncr = DAG.getStore(VAList.getValue(1), VAIncr,
600 Op.getOperand(1), SV, 0);
601 // Load the actual argument out of the pointer VAList
602 return DAG.getLoad(Op.getValueType(), VAIncr, VAList, NULL, 0);
605 // vastart just stores the address of the VarArgsFrameIndex slot into the
606 // memory location argument.
607 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
608 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
609 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
611 // Frame & Return address. Currently unimplemented
612 case ISD::RETURNADDR: break;
613 case ISD::FRAMEADDR: break;