1 //===-- IA64ISelLowering.cpp - IA64 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the IA64ISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "IA64ISelLowering.h"
15 #include "IA64MachineFunctionInfo.h"
16 #include "IA64TargetMachine.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
26 IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
27 : TargetLowering(TM) {
29 // register class for general registers
30 addRegisterClass(MVT::i64, IA64::GRRegisterClass);
32 // register class for FP registers
33 addRegisterClass(MVT::f64, IA64::FPRegisterClass);
35 // register class for predicate registers
36 addRegisterClass(MVT::i1, IA64::PRRegisterClass);
38 setOperationAction(ISD::BRIND , MVT::i64, Expand);
39 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
40 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
42 // ia64 uses SELECT not SELECT_CC
43 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
45 // We need to handle ISD::RET for void functions ourselves,
46 // so we get a chance to restore ar.pfs before adding a
48 setOperationAction(ISD::RET, MVT::Other, Custom);
50 setSetCCResultType(MVT::i1);
51 setShiftAmountType(MVT::i64);
53 setOperationAction(ISD::EXTLOAD , MVT::i1 , Promote);
55 setOperationAction(ISD::ZEXTLOAD , MVT::i1 , Expand);
57 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
58 setOperationAction(ISD::SEXTLOAD , MVT::i8 , Expand);
59 setOperationAction(ISD::SEXTLOAD , MVT::i16 , Expand);
60 setOperationAction(ISD::SEXTLOAD , MVT::i32 , Expand);
62 setOperationAction(ISD::FREM , MVT::f32 , Expand);
63 setOperationAction(ISD::FREM , MVT::f64 , Expand);
65 setOperationAction(ISD::UREM , MVT::f32 , Expand);
66 setOperationAction(ISD::UREM , MVT::f64 , Expand);
68 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
69 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
70 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
72 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
73 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
75 // We don't support sin/cos/sqrt
76 setOperationAction(ISD::FSIN , MVT::f64, Expand);
77 setOperationAction(ISD::FCOS , MVT::f64, Expand);
78 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
79 setOperationAction(ISD::FSIN , MVT::f32, Expand);
80 setOperationAction(ISD::FCOS , MVT::f32, Expand);
81 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
83 // FIXME: IA64 supports fcopysign natively!
84 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
85 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
87 // We don't have line number support yet.
88 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
89 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
90 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
92 //IA64 has these, but they are not implemented
93 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
94 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
95 setOperationAction(ISD::ROTL , MVT::i64 , Expand);
96 setOperationAction(ISD::ROTR , MVT::i64 , Expand);
97 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); // mux @rev
99 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
100 setOperationAction(ISD::VAARG , MVT::Other, Custom);
101 setOperationAction(ISD::VASTART , MVT::Other, Custom);
103 // Use the default implementation.
104 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
105 setOperationAction(ISD::VAEND , MVT::Other, Expand);
106 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
107 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
108 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
110 setStackPointerRegisterToSaveRestore(IA64::r12);
112 computeRegisterProperties();
114 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
115 addLegalFPImmediate(+0.0);
116 addLegalFPImmediate(+1.0);
119 const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const {
122 case IA64ISD::GETFD: return "IA64ISD::GETFD";
123 case IA64ISD::BRCALL: return "IA64ISD::BRCALL";
124 case IA64ISD::RET_FLAG: return "IA64ISD::RET_FLAG";
129 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
130 static bool isFloatingPointZero(SDOperand Op) {
131 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
132 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
133 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
134 // Maybe this has already been legalized into the constant pool?
135 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
136 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
137 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
142 std::vector<SDOperand>
143 IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
144 std::vector<SDOperand> ArgValues;
146 // add beautiful description of IA64 stack frame format
147 // here (from intel 24535803.pdf most likely)
149 MachineFunction &MF = DAG.getMachineFunction();
150 MachineFrameInfo *MFI = MF.getFrameInfo();
152 GP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
153 SP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
154 RP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
156 MachineBasicBlock& BB = MF.front();
158 unsigned args_int[] = {IA64::r32, IA64::r33, IA64::r34, IA64::r35,
159 IA64::r36, IA64::r37, IA64::r38, IA64::r39};
161 unsigned args_FP[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11,
162 IA64::F12,IA64::F13,IA64::F14, IA64::F15};
168 unsigned used_FPArgs = 0; // how many FP args have been used so far?
170 unsigned ArgOffset = 0;
173 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
175 SDOperand newroot, argt;
176 if(count < 8) { // need to fix this logic? maybe.
178 switch (getValueType(I->getType())) {
180 assert(0 && "ERROR in LowerArgs: can't lower this type of arg.\n");
182 // fixme? (well, will need to for weird FP structy stuff,
183 // see intel ABI docs)
185 //XXX BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]);
186 MF.addLiveIn(args_FP[used_FPArgs]); // mark this reg as liveIn
187 // floating point args go into f8..f15 as-needed, the increment
188 argVreg[count] = // is below..:
189 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::f64));
190 // FP args go into f8..f15 as needed: (hence the ++)
191 argPreg[count] = args_FP[used_FPArgs++];
192 argOpc[count] = IA64::FMOV;
193 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count],
195 if (I->getType() == Type::FloatTy)
196 argt = DAG.getNode(ISD::FP_ROUND, MVT::f32, argt);
198 case MVT::i1: // NOTE: as far as C abi stuff goes,
199 // bools are just boring old ints
204 //XXX BuildMI(&BB, IA64::IDEF, 0, args_int[count]);
205 MF.addLiveIn(args_int[count]); // mark this register as liveIn
207 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
208 argPreg[count] = args_int[count];
209 argOpc[count] = IA64::MOV;
211 DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], MVT::i64);
212 if ( getValueType(I->getType()) != MVT::i64)
213 argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()),
217 } else { // more than 8 args go into the frame
218 // Create the frame index object for this incoming parameter...
219 ArgOffset = 16 + 8 * (count - 8);
220 int FI = MFI->CreateFixedObject(8, ArgOffset);
222 // Create the SelectionDAG nodes corresponding to a load
223 //from this parameter
224 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
225 argt = newroot = DAG.getLoad(getValueType(I->getType()),
226 DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
229 DAG.setRoot(newroot.getValue(1));
230 ArgValues.push_back(argt);
234 // Create a vreg to hold the output of (what will become)
235 // the "alloc" instruction
236 VirtGPR = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
237 BuildMI(&BB, IA64::PSEUDO_ALLOC, 0, VirtGPR);
238 // we create a PSEUDO_ALLOC (pseudo)instruction for now
240 BuildMI(&BB, IA64::IDEF, 0, IA64::r1);
243 BuildMI(&BB, IA64::IDEF, 0, IA64::r12);
244 BuildMI(&BB, IA64::IDEF, 0, IA64::rp);
247 BuildMI(&BB, IA64::MOV, 1, GP).addReg(IA64::r1);
250 BuildMI(&BB, IA64::MOV, 1, SP).addReg(IA64::r12);
251 BuildMI(&BB, IA64::MOV, 1, RP).addReg(IA64::rp);
255 unsigned tempOffset=0;
257 // if this is a varargs function, we simply lower llvm.va_start by
258 // pointing to the first entry
261 VarArgsFrameIndex = MFI->CreateFixedObject(8, tempOffset);
264 // here we actually do the moving of args, and store them to the stack
265 // too if this is a varargs function:
266 for (int i = 0; i < count && i < 8; ++i) {
267 BuildMI(&BB, argOpc[i], 1, argVreg[i]).addReg(argPreg[i]);
269 // if this is a varargs function, we copy the input registers to the stack
270 int FI = MFI->CreateFixedObject(8, tempOffset);
271 tempOffset+=8; //XXX: is it safe to use r22 like this?
272 BuildMI(&BB, IA64::MOV, 1, IA64::r22).addFrameIndex(FI);
273 // FIXME: we should use st8.spill here, one day
274 BuildMI(&BB, IA64::ST8, 1, IA64::r22).addReg(argPreg[i]);
278 // Finally, inform the code generator which regs we return values in.
279 // (see the ISD::RET: case in the instruction selector)
280 switch (getValueType(F.getReturnType())) {
281 default: assert(0 && "i have no idea where to return this type!");
282 case MVT::isVoid: break;
288 MF.addLiveOut(IA64::r8);
292 MF.addLiveOut(IA64::F8);
299 std::pair<SDOperand, SDOperand>
300 IA64TargetLowering::LowerCallTo(SDOperand Chain,
301 const Type *RetTy, bool isVarArg,
302 unsigned CallingConv, bool isTailCall,
303 SDOperand Callee, ArgListTy &Args,
306 MachineFunction &MF = DAG.getMachineFunction();
308 unsigned NumBytes = 16;
309 unsigned outRegsUsed = 0;
311 if (Args.size() > 8) {
312 NumBytes += (Args.size() - 8) * 8;
315 outRegsUsed = Args.size();
318 // FIXME? this WILL fail if we ever try to pass around an arg that
319 // consumes more than a single output slot (a 'real' double, int128
320 // some sort of aggregate etc.), as we'll underestimate how many 'outX'
321 // registers we use. Hopefully, the assembler will notice.
322 MF.getInfo<IA64FunctionInfo>()->outRegsUsed=
323 std::max(outRegsUsed, MF.getInfo<IA64FunctionInfo>()->outRegsUsed);
325 // keep stack frame 16-byte aligned
326 //assert(NumBytes==((NumBytes+15) & ~15) && "stack frame not 16-byte aligned!");
327 NumBytes = (NumBytes+15) & ~15;
329 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
331 SDOperand StackPtr, NullSV;
332 std::vector<SDOperand> Stores;
333 std::vector<SDOperand> Converts;
334 std::vector<SDOperand> RegValuesToPass;
335 unsigned ArgOffset = 16;
337 for (unsigned i = 0, e = Args.size(); i != e; ++i)
339 SDOperand Val = Args[i].first;
340 MVT::ValueType ObjectVT = Val.getValueType();
341 SDOperand ValToStore(0, 0), ValToConvert(0, 0);
344 default: assert(0 && "unexpected argument type!");
349 //promote to 64-bits, sign/zero extending based on type
351 if(Args[i].second->isSigned())
352 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Val);
354 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Val);
358 if(RegValuesToPass.size() >= 8) {
361 RegValuesToPass.push_back(Val);
366 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
369 if(RegValuesToPass.size() >= 8) {
372 RegValuesToPass.push_back(Val);
373 if(1 /* TODO: if(calling external or varadic function)*/ ) {
374 ValToConvert = Val; // additionally pass this FP value as an int
382 StackPtr = DAG.getRegister(IA64::r12, MVT::i64);
383 NullSV = DAG.getSrcValue(NULL);
385 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
386 PtrOff = DAG.getNode(ISD::ADD, MVT::i64, StackPtr, PtrOff);
387 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
388 ValToStore, PtrOff, NullSV));
389 ArgOffset += ObjSize;
392 if(ValToConvert.Val) {
393 Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert));
397 // Emit all stores, make sure they occur before any copies into physregs.
399 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size());
401 static const unsigned IntArgRegs[] = {
402 IA64::out0, IA64::out1, IA64::out2, IA64::out3,
403 IA64::out4, IA64::out5, IA64::out6, IA64::out7
406 static const unsigned FPArgRegs[] = {
407 IA64::F8, IA64::F9, IA64::F10, IA64::F11,
408 IA64::F12, IA64::F13, IA64::F14, IA64::F15
413 // save the current GP, SP and RP : FIXME: do we need to do all 3 always?
414 SDOperand GPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r1, MVT::i64, InFlag);
415 Chain = GPBeforeCall.getValue(1);
416 InFlag = Chain.getValue(2);
417 SDOperand SPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r12, MVT::i64, InFlag);
418 Chain = SPBeforeCall.getValue(1);
419 InFlag = Chain.getValue(2);
420 SDOperand RPBeforeCall = DAG.getCopyFromReg(Chain, IA64::rp, MVT::i64, InFlag);
421 Chain = RPBeforeCall.getValue(1);
422 InFlag = Chain.getValue(2);
424 // Build a sequence of copy-to-reg nodes chained together with token chain
425 // and flag operands which copy the outgoing integer args into regs out[0-7]
426 // mapped 1:1 and the FP args into regs F8-F15 "lazily"
427 // TODO: for performance, we should only copy FP args into int regs when we
428 // know this is required (i.e. for varardic or external (unknown) functions)
430 // first to the FP->(integer representation) conversions, these are
431 // flagged for now, but shouldn't have to be (TODO)
432 unsigned seenConverts = 0;
433 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
434 if(MVT::isFloatingPoint(RegValuesToPass[i].getValueType())) {
435 Chain = DAG.getCopyToReg(Chain, IntArgRegs[i], Converts[seenConverts++], InFlag);
436 InFlag = Chain.getValue(1);
440 // next copy args into the usual places, these are flagged
441 unsigned usedFPArgs = 0;
442 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
443 Chain = DAG.getCopyToReg(Chain,
444 MVT::isInteger(RegValuesToPass[i].getValueType()) ?
445 IntArgRegs[i] : FPArgRegs[usedFPArgs++],
446 RegValuesToPass[i], InFlag);
447 InFlag = Chain.getValue(1);
450 // If the callee is a GlobalAddress node (quite common, every direct call is)
451 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
453 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
454 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i64);
458 std::vector<MVT::ValueType> NodeTys;
459 std::vector<SDOperand> CallOperands;
460 NodeTys.push_back(MVT::Other); // Returns a chain
461 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
462 CallOperands.push_back(Chain);
463 CallOperands.push_back(Callee);
465 // emit the call itself
467 CallOperands.push_back(InFlag);
469 assert(0 && "this should never happen!\n");
471 // to make way for a hack:
472 Chain = DAG.getNode(IA64ISD::BRCALL, NodeTys,
473 &CallOperands[0], CallOperands.size());
474 InFlag = Chain.getValue(1);
476 // restore the GP, SP and RP after the call
477 Chain = DAG.getCopyToReg(Chain, IA64::r1, GPBeforeCall, InFlag);
478 InFlag = Chain.getValue(1);
479 Chain = DAG.getCopyToReg(Chain, IA64::r12, SPBeforeCall, InFlag);
480 InFlag = Chain.getValue(1);
481 Chain = DAG.getCopyToReg(Chain, IA64::rp, RPBeforeCall, InFlag);
482 InFlag = Chain.getValue(1);
484 std::vector<MVT::ValueType> RetVals;
485 RetVals.push_back(MVT::Other);
486 RetVals.push_back(MVT::Flag);
488 MVT::ValueType RetTyVT = getValueType(RetTy);
490 if (RetTyVT != MVT::isVoid) {
492 default: assert(0 && "Unknown value type to return!");
493 case MVT::i1: { // bools are just like other integers (returned in r8)
494 // we *could* fall through to the truncate below, but this saves a
495 // few redundant predicate ops
496 SDOperand boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
497 InFlag = boolInR8.getValue(2);
498 Chain = boolInR8.getValue(1);
499 SDOperand zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag);
500 InFlag = zeroReg.getValue(2);
501 Chain = zeroReg.getValue(1);
503 RetVal = DAG.getSetCC(MVT::i1, boolInR8, zeroReg, ISD::SETNE);
509 RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
510 Chain = RetVal.getValue(1);
512 // keep track of whether it is sign or zero extended (todo: bools?)
514 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
515 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
517 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
520 RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
521 Chain = RetVal.getValue(1);
522 InFlag = RetVal.getValue(2); // XXX dead
525 RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
526 Chain = RetVal.getValue(1);
527 RetVal = DAG.getNode(ISD::TRUNCATE, MVT::f32, RetVal);
530 RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
531 Chain = RetVal.getValue(1);
532 InFlag = RetVal.getValue(2); // XXX dead
537 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
538 DAG.getConstant(NumBytes, getPointerTy()));
540 return std::make_pair(RetVal, Chain);
543 std::pair<SDOperand, SDOperand> IA64TargetLowering::
544 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
546 assert(0 && "LowerFrameReturnAddress unimplemented");
550 SDOperand IA64TargetLowering::
551 LowerOperation(SDOperand Op, SelectionDAG &DAG) {
552 switch (Op.getOpcode()) {
553 default: assert(0 && "Should not custom lower this!");
555 SDOperand AR_PFSVal, Copy;
557 switch(Op.getNumOperands()) {
559 assert(0 && "Do not know how to return this many arguments!");
562 AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64);
563 AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), IA64::AR_PFS,
565 return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, AR_PFSVal);
567 // Copy the result into the output register & restore ar.pfs
568 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
569 unsigned ArgReg = MVT::isInteger(ArgVT) ? IA64::r8 : IA64::F8;
571 AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64);
572 Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), ArgReg, Op.getOperand(1),
574 AR_PFSVal = DAG.getCopyToReg(Copy.getValue(0), IA64::AR_PFS, AR_PFSVal,
576 std::vector<MVT::ValueType> NodeTys;
577 std::vector<SDOperand> RetOperands;
578 NodeTys.push_back(MVT::Other);
579 NodeTys.push_back(MVT::Flag);
580 RetOperands.push_back(AR_PFSVal);
581 RetOperands.push_back(AR_PFSVal.getValue(1));
582 return DAG.getNode(IA64ISD::RET_FLAG, NodeTys,
583 &RetOperands[0], RetOperands.size());
589 MVT::ValueType VT = getPointerTy();
590 SDOperand VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1),
592 // Increment the pointer, VAList, to the next vaarg
593 SDOperand VAIncr = DAG.getNode(ISD::ADD, VT, VAList,
594 DAG.getConstant(MVT::getSizeInBits(VT)/8,
596 // Store the incremented VAList to the legalized pointer
597 VAIncr = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), VAIncr,
598 Op.getOperand(1), Op.getOperand(2));
599 // Load the actual argument out of the pointer VAList
600 return DAG.getLoad(Op.getValueType(), VAIncr, VAList, DAG.getSrcValue(0));
603 // vastart just stores the address of the VarArgsFrameIndex slot into the
604 // memory location argument.
605 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
606 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
607 Op.getOperand(1), Op.getOperand(2));