1 //===-- IA64ISelLowering.cpp - IA64 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the IA64ISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "IA64ISelLowering.h"
15 #include "IA64MachineFunctionInfo.h"
16 #include "IA64TargetMachine.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
26 IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
27 : TargetLowering(TM) {
29 // register class for general registers
30 addRegisterClass(MVT::i64, IA64::GRRegisterClass);
32 // register class for FP registers
33 addRegisterClass(MVT::f64, IA64::FPRegisterClass);
35 // register class for predicate registers
36 addRegisterClass(MVT::i1, IA64::PRRegisterClass);
38 setLoadXAction(ISD::EXTLOAD , MVT::i1 , Promote);
40 setLoadXAction(ISD::ZEXTLOAD , MVT::i1 , Promote);
42 setLoadXAction(ISD::SEXTLOAD , MVT::i1 , Promote);
43 setLoadXAction(ISD::SEXTLOAD , MVT::i8 , Expand);
44 setLoadXAction(ISD::SEXTLOAD , MVT::i16 , Expand);
45 setLoadXAction(ISD::SEXTLOAD , MVT::i32 , Expand);
47 setOperationAction(ISD::BRIND , MVT::Other, Expand);
48 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
49 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
50 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
52 // ia64 uses SELECT not SELECT_CC
53 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
55 // We need to handle ISD::RET for void functions ourselves,
56 // so we get a chance to restore ar.pfs before adding a
58 setOperationAction(ISD::RET, MVT::Other, Custom);
60 setSetCCResultType(MVT::i1);
61 setShiftAmountType(MVT::i64);
63 setOperationAction(ISD::FREM , MVT::f32 , Expand);
64 setOperationAction(ISD::FREM , MVT::f64 , Expand);
66 setOperationAction(ISD::UREM , MVT::f32 , Expand);
67 setOperationAction(ISD::UREM , MVT::f64 , Expand);
69 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
70 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
71 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
73 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
74 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
76 // We don't support sin/cos/sqrt/pow
77 setOperationAction(ISD::FSIN , MVT::f64, Expand);
78 setOperationAction(ISD::FCOS , MVT::f64, Expand);
79 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
80 setOperationAction(ISD::FPOW , MVT::f64, Expand);
81 setOperationAction(ISD::FSIN , MVT::f32, Expand);
82 setOperationAction(ISD::FCOS , MVT::f32, Expand);
83 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
84 setOperationAction(ISD::FPOW , MVT::f32, Expand);
86 // FIXME: IA64 supports fcopysign natively!
87 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
88 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
90 // We don't have line number support yet.
91 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
92 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
93 setOperationAction(ISD::LABEL, MVT::Other, Expand);
95 //IA64 has these, but they are not implemented
96 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
97 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
98 setOperationAction(ISD::ROTL , MVT::i64 , Expand);
99 setOperationAction(ISD::ROTR , MVT::i64 , Expand);
100 setOperationAction(ISD::BSWAP, MVT::i64 , Expand); // mux @rev
102 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
103 setOperationAction(ISD::VAARG , MVT::Other, Custom);
104 setOperationAction(ISD::VASTART , MVT::Other, Custom);
106 // Use the default implementation.
107 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
108 setOperationAction(ISD::VAEND , MVT::Other, Expand);
109 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
110 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
111 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
113 // Thread Local Storage
114 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
116 setStackPointerRegisterToSaveRestore(IA64::r12);
118 setJumpBufSize(704); // on ia64-linux, jmp_bufs are 704 bytes..
119 setJumpBufAlignment(16); // ...and must be 16-byte aligned
121 computeRegisterProperties();
123 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
124 addLegalFPImmediate(APFloat(+0.0));
125 addLegalFPImmediate(APFloat(+0.0f));
126 addLegalFPImmediate(APFloat(+1.0));
127 addLegalFPImmediate(APFloat(+1.0f));
130 const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const {
133 case IA64ISD::GETFD: return "IA64ISD::GETFD";
134 case IA64ISD::BRCALL: return "IA64ISD::BRCALL";
135 case IA64ISD::RET_FLAG: return "IA64ISD::RET_FLAG";
140 std::vector<SDOperand>
141 IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
142 std::vector<SDOperand> ArgValues;
144 // add beautiful description of IA64 stack frame format
145 // here (from intel 24535803.pdf most likely)
147 MachineFunction &MF = DAG.getMachineFunction();
148 MachineFrameInfo *MFI = MF.getFrameInfo();
149 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
151 GP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
152 SP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
153 RP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
155 MachineBasicBlock& BB = MF.front();
157 unsigned args_int[] = {IA64::r32, IA64::r33, IA64::r34, IA64::r35,
158 IA64::r36, IA64::r37, IA64::r38, IA64::r39};
160 unsigned args_FP[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11,
161 IA64::F12,IA64::F13,IA64::F14, IA64::F15};
167 unsigned used_FPArgs = 0; // how many FP args have been used so far?
169 unsigned ArgOffset = 0;
172 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
174 SDOperand newroot, argt;
175 if(count < 8) { // need to fix this logic? maybe.
177 switch (getValueType(I->getType())) {
179 assert(0 && "ERROR in LowerArgs: can't lower this type of arg.\n");
181 // fixme? (well, will need to for weird FP structy stuff,
182 // see intel ABI docs)
184 //XXX BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]);
185 MF.getRegInfo().addLiveIn(args_FP[used_FPArgs]);
186 // mark this reg as liveIn
187 // floating point args go into f8..f15 as-needed, the increment
188 argVreg[count] = // is below..:
189 MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::f64));
190 // FP args go into f8..f15 as needed: (hence the ++)
191 argPreg[count] = args_FP[used_FPArgs++];
192 argOpc[count] = IA64::FMOV;
193 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count],
195 if (I->getType() == Type::FloatTy)
196 argt = DAG.getNode(ISD::FP_ROUND, MVT::f32, argt,
197 DAG.getIntPtrConstant(0));
199 case MVT::i1: // NOTE: as far as C abi stuff goes,
200 // bools are just boring old ints
205 //XXX BuildMI(&BB, IA64::IDEF, 0, args_int[count]);
206 MF.getRegInfo().addLiveIn(args_int[count]);
207 // mark this register as liveIn
209 MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
210 argPreg[count] = args_int[count];
211 argOpc[count] = IA64::MOV;
213 DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], MVT::i64);
214 if ( getValueType(I->getType()) != MVT::i64)
215 argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()),
219 } else { // more than 8 args go into the frame
220 // Create the frame index object for this incoming parameter...
221 ArgOffset = 16 + 8 * (count - 8);
222 int FI = MFI->CreateFixedObject(8, ArgOffset);
224 // Create the SelectionDAG nodes corresponding to a load
225 //from this parameter
226 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
227 argt = newroot = DAG.getLoad(getValueType(I->getType()),
228 DAG.getEntryNode(), FIN, NULL, 0);
231 DAG.setRoot(newroot.getValue(1));
232 ArgValues.push_back(argt);
236 // Create a vreg to hold the output of (what will become)
237 // the "alloc" instruction
238 VirtGPR = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
239 BuildMI(&BB, TII->get(IA64::PSEUDO_ALLOC), VirtGPR);
240 // we create a PSEUDO_ALLOC (pseudo)instruction for now
242 BuildMI(&BB, IA64::IDEF, 0, IA64::r1);
245 BuildMI(&BB, IA64::IDEF, 0, IA64::r12);
246 BuildMI(&BB, IA64::IDEF, 0, IA64::rp);
249 BuildMI(&BB, IA64::MOV, 1, GP).addReg(IA64::r1);
252 BuildMI(&BB, IA64::MOV, 1, SP).addReg(IA64::r12);
253 BuildMI(&BB, IA64::MOV, 1, RP).addReg(IA64::rp);
257 unsigned tempOffset=0;
259 // if this is a varargs function, we simply lower llvm.va_start by
260 // pointing to the first entry
263 VarArgsFrameIndex = MFI->CreateFixedObject(8, tempOffset);
266 // here we actually do the moving of args, and store them to the stack
267 // too if this is a varargs function:
268 for (int i = 0; i < count && i < 8; ++i) {
269 BuildMI(&BB, TII->get(argOpc[i]), argVreg[i]).addReg(argPreg[i]);
271 // if this is a varargs function, we copy the input registers to the stack
272 int FI = MFI->CreateFixedObject(8, tempOffset);
273 tempOffset+=8; //XXX: is it safe to use r22 like this?
274 BuildMI(&BB, TII->get(IA64::MOV), IA64::r22).addFrameIndex(FI);
275 // FIXME: we should use st8.spill here, one day
276 BuildMI(&BB, TII->get(IA64::ST8), IA64::r22).addReg(argPreg[i]);
280 // Finally, inform the code generator which regs we return values in.
281 // (see the ISD::RET: case in the instruction selector)
282 switch (getValueType(F.getReturnType())) {
283 default: assert(0 && "i have no idea where to return this type!");
284 case MVT::isVoid: break;
290 MF.getRegInfo().addLiveOut(IA64::r8);
294 MF.getRegInfo().addLiveOut(IA64::F8);
301 std::pair<SDOperand, SDOperand>
302 IA64TargetLowering::LowerCallTo(SDOperand Chain,
303 const Type *RetTy, bool RetTyIsSigned,
304 bool isVarArg, unsigned CallingConv,
305 bool isTailCall, SDOperand Callee,
306 ArgListTy &Args, SelectionDAG &DAG) {
308 MachineFunction &MF = DAG.getMachineFunction();
310 unsigned NumBytes = 16;
311 unsigned outRegsUsed = 0;
313 if (Args.size() > 8) {
314 NumBytes += (Args.size() - 8) * 8;
317 outRegsUsed = Args.size();
320 // FIXME? this WILL fail if we ever try to pass around an arg that
321 // consumes more than a single output slot (a 'real' double, int128
322 // some sort of aggregate etc.), as we'll underestimate how many 'outX'
323 // registers we use. Hopefully, the assembler will notice.
324 MF.getInfo<IA64FunctionInfo>()->outRegsUsed=
325 std::max(outRegsUsed, MF.getInfo<IA64FunctionInfo>()->outRegsUsed);
327 // keep stack frame 16-byte aligned
328 // assert(NumBytes==((NumBytes+15) & ~15) &&
329 // "stack frame not 16-byte aligned!");
330 NumBytes = (NumBytes+15) & ~15;
332 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, getPointerTy()));
335 std::vector<SDOperand> Stores;
336 std::vector<SDOperand> Converts;
337 std::vector<SDOperand> RegValuesToPass;
338 unsigned ArgOffset = 16;
340 for (unsigned i = 0, e = Args.size(); i != e; ++i)
342 SDOperand Val = Args[i].Node;
343 MVT::ValueType ObjectVT = Val.getValueType();
344 SDOperand ValToStore(0, 0), ValToConvert(0, 0);
347 default: assert(0 && "unexpected argument type!");
352 //promote to 64-bits, sign/zero extending based on type
354 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
356 ExtendKind = ISD::SIGN_EXTEND;
357 else if (Args[i].isZExt)
358 ExtendKind = ISD::ZERO_EXTEND;
359 Val = DAG.getNode(ExtendKind, MVT::i64, Val);
364 if(RegValuesToPass.size() >= 8) {
367 RegValuesToPass.push_back(Val);
372 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
375 if(RegValuesToPass.size() >= 8) {
378 RegValuesToPass.push_back(Val);
379 if(1 /* TODO: if(calling external or varadic function)*/ ) {
380 ValToConvert = Val; // additionally pass this FP value as an int
388 StackPtr = DAG.getRegister(IA64::r12, MVT::i64);
390 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
391 PtrOff = DAG.getNode(ISD::ADD, MVT::i64, StackPtr, PtrOff);
392 Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
393 ArgOffset += ObjSize;
396 if(ValToConvert.Val) {
397 Converts.push_back(DAG.getNode(IA64ISD::GETFD, MVT::i64, ValToConvert));
401 // Emit all stores, make sure they occur before any copies into physregs.
403 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size());
405 static const unsigned IntArgRegs[] = {
406 IA64::out0, IA64::out1, IA64::out2, IA64::out3,
407 IA64::out4, IA64::out5, IA64::out6, IA64::out7
410 static const unsigned FPArgRegs[] = {
411 IA64::F8, IA64::F9, IA64::F10, IA64::F11,
412 IA64::F12, IA64::F13, IA64::F14, IA64::F15
417 // save the current GP, SP and RP : FIXME: do we need to do all 3 always?
418 SDOperand GPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r1, MVT::i64, InFlag);
419 Chain = GPBeforeCall.getValue(1);
420 InFlag = Chain.getValue(2);
421 SDOperand SPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r12, MVT::i64, InFlag);
422 Chain = SPBeforeCall.getValue(1);
423 InFlag = Chain.getValue(2);
424 SDOperand RPBeforeCall = DAG.getCopyFromReg(Chain, IA64::rp, MVT::i64, InFlag);
425 Chain = RPBeforeCall.getValue(1);
426 InFlag = Chain.getValue(2);
428 // Build a sequence of copy-to-reg nodes chained together with token chain
429 // and flag operands which copy the outgoing integer args into regs out[0-7]
430 // mapped 1:1 and the FP args into regs F8-F15 "lazily"
431 // TODO: for performance, we should only copy FP args into int regs when we
432 // know this is required (i.e. for varardic or external (unknown) functions)
434 // first to the FP->(integer representation) conversions, these are
435 // flagged for now, but shouldn't have to be (TODO)
436 unsigned seenConverts = 0;
437 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
438 if(MVT::isFloatingPoint(RegValuesToPass[i].getValueType())) {
439 Chain = DAG.getCopyToReg(Chain, IntArgRegs[i], Converts[seenConverts++],
441 InFlag = Chain.getValue(1);
445 // next copy args into the usual places, these are flagged
446 unsigned usedFPArgs = 0;
447 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
448 Chain = DAG.getCopyToReg(Chain,
449 MVT::isInteger(RegValuesToPass[i].getValueType()) ?
450 IntArgRegs[i] : FPArgRegs[usedFPArgs++], RegValuesToPass[i], InFlag);
451 InFlag = Chain.getValue(1);
454 // If the callee is a GlobalAddress node (quite common, every direct call is)
455 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
457 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
458 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i64);
462 std::vector<MVT::ValueType> NodeTys;
463 std::vector<SDOperand> CallOperands;
464 NodeTys.push_back(MVT::Other); // Returns a chain
465 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
466 CallOperands.push_back(Chain);
467 CallOperands.push_back(Callee);
469 // emit the call itself
471 CallOperands.push_back(InFlag);
473 assert(0 && "this should never happen!\n");
475 // to make way for a hack:
476 Chain = DAG.getNode(IA64ISD::BRCALL, NodeTys,
477 &CallOperands[0], CallOperands.size());
478 InFlag = Chain.getValue(1);
480 // restore the GP, SP and RP after the call
481 Chain = DAG.getCopyToReg(Chain, IA64::r1, GPBeforeCall, InFlag);
482 InFlag = Chain.getValue(1);
483 Chain = DAG.getCopyToReg(Chain, IA64::r12, SPBeforeCall, InFlag);
484 InFlag = Chain.getValue(1);
485 Chain = DAG.getCopyToReg(Chain, IA64::rp, RPBeforeCall, InFlag);
486 InFlag = Chain.getValue(1);
488 std::vector<MVT::ValueType> RetVals;
489 RetVals.push_back(MVT::Other);
490 RetVals.push_back(MVT::Flag);
492 MVT::ValueType RetTyVT = getValueType(RetTy);
494 if (RetTyVT != MVT::isVoid) {
496 default: assert(0 && "Unknown value type to return!");
497 case MVT::i1: { // bools are just like other integers (returned in r8)
498 // we *could* fall through to the truncate below, but this saves a
499 // few redundant predicate ops
500 SDOperand boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64,InFlag);
501 InFlag = boolInR8.getValue(2);
502 Chain = boolInR8.getValue(1);
503 SDOperand zeroReg = DAG.getCopyFromReg(Chain, IA64::r0, MVT::i64, InFlag);
504 InFlag = zeroReg.getValue(2);
505 Chain = zeroReg.getValue(1);
507 RetVal = DAG.getSetCC(MVT::i1, boolInR8, zeroReg, ISD::SETNE);
513 RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
514 Chain = RetVal.getValue(1);
516 // keep track of whether it is sign or zero extended (todo: bools?)
518 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
519 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
521 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
524 RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
525 Chain = RetVal.getValue(1);
526 InFlag = RetVal.getValue(2); // XXX dead
529 RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
530 Chain = RetVal.getValue(1);
531 RetVal = DAG.getNode(ISD::TRUNCATE, MVT::f32, RetVal);
534 RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
535 Chain = RetVal.getValue(1);
536 InFlag = RetVal.getValue(2); // XXX dead
541 Chain = DAG.getCALLSEQ_END(Chain,
542 DAG.getConstant(NumBytes, getPointerTy()),
543 DAG.getConstant(0, getPointerTy()),
545 return std::make_pair(RetVal, Chain);
548 SDOperand IA64TargetLowering::
549 LowerOperation(SDOperand Op, SelectionDAG &DAG) {
550 switch (Op.getOpcode()) {
551 default: assert(0 && "Should not custom lower this!");
552 case ISD::GlobalTLSAddress:
553 assert(0 && "TLS not implemented for IA64.");
555 SDOperand AR_PFSVal, Copy;
557 switch(Op.getNumOperands()) {
559 assert(0 && "Do not know how to return this many arguments!");
562 AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64);
563 AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), IA64::AR_PFS,
565 return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other, AR_PFSVal);
567 // Copy the result into the output register & restore ar.pfs
568 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
569 unsigned ArgReg = MVT::isInteger(ArgVT) ? IA64::r8 : IA64::F8;
571 AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), VirtGPR, MVT::i64);
572 Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), ArgReg, Op.getOperand(1),
574 AR_PFSVal = DAG.getCopyToReg(Copy.getValue(0), IA64::AR_PFS, AR_PFSVal,
576 return DAG.getNode(IA64ISD::RET_FLAG, MVT::Other,
577 AR_PFSVal, AR_PFSVal.getValue(1));
583 MVT::ValueType VT = getPointerTy();
584 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
585 SDOperand VAList = DAG.getLoad(VT, Op.getOperand(0), Op.getOperand(1),
587 // Increment the pointer, VAList, to the next vaarg
588 SDOperand VAIncr = DAG.getNode(ISD::ADD, VT, VAList,
589 DAG.getConstant(MVT::getSizeInBits(VT)/8,
591 // Store the incremented VAList to the legalized pointer
592 VAIncr = DAG.getStore(VAList.getValue(1), VAIncr,
593 Op.getOperand(1), SV, 0);
594 // Load the actual argument out of the pointer VAList
595 return DAG.getLoad(Op.getValueType(), VAIncr, VAList, NULL, 0);
598 // vastart just stores the address of the VarArgsFrameIndex slot into the
599 // memory location argument.
600 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
601 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
602 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
604 // Frame & Return address. Currently unimplemented
605 case ISD::RETURNADDR: break;
606 case ISD::FRAMEADDR: break;