1 //===-- IA64ISelLowering.cpp - IA64 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the IA64ISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "IA64ISelLowering.h"
15 #include "IA64MachineFunctionInfo.h"
16 #include "IA64TargetMachine.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
26 IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
27 : TargetLowering(TM) {
29 // register class for general registers
30 addRegisterClass(MVT::i64, IA64::GRRegisterClass);
32 // register class for FP registers
33 addRegisterClass(MVT::f64, IA64::FPRegisterClass);
35 // register class for predicate registers
36 addRegisterClass(MVT::i1, IA64::PRRegisterClass);
38 setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
39 setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
40 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
42 setSetCCResultType(MVT::i1);
43 setShiftAmountType(MVT::i64);
45 setOperationAction(ISD::EXTLOAD , MVT::i1 , Promote);
47 setOperationAction(ISD::ZEXTLOAD , MVT::i1 , Expand);
49 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
50 setOperationAction(ISD::SEXTLOAD , MVT::i8 , Expand);
51 setOperationAction(ISD::SEXTLOAD , MVT::i16 , Expand);
52 setOperationAction(ISD::SEXTLOAD , MVT::i32 , Expand);
54 setOperationAction(ISD::FREM , MVT::f32 , Expand);
55 setOperationAction(ISD::FREM , MVT::f64 , Expand);
57 setOperationAction(ISD::UREM , MVT::f32 , Expand);
58 setOperationAction(ISD::UREM , MVT::f64 , Expand);
60 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
61 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
62 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
64 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
65 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
67 // We don't support sin/cos/sqrt
68 setOperationAction(ISD::FSIN , MVT::f64, Expand);
69 setOperationAction(ISD::FCOS , MVT::f64, Expand);
70 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
71 setOperationAction(ISD::FSIN , MVT::f32, Expand);
72 setOperationAction(ISD::FCOS , MVT::f32, Expand);
73 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
75 //IA64 has these, but they are not implemented
76 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
77 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
79 computeRegisterProperties();
81 addLegalFPImmediate(+0.0);
82 addLegalFPImmediate(+1.0);
85 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
86 static bool isFloatingPointZero(SDOperand Op) {
87 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
88 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
89 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
90 // Maybe this has already been legalized into the constant pool?
91 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
92 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
93 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
98 std::vector<SDOperand>
99 IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
100 std::vector<SDOperand> ArgValues;
102 // add beautiful description of IA64 stack frame format
103 // here (from intel 24535803.pdf most likely)
105 MachineFunction &MF = DAG.getMachineFunction();
106 MachineFrameInfo *MFI = MF.getFrameInfo();
108 GP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
109 SP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
110 RP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
112 MachineBasicBlock& BB = MF.front();
114 unsigned args_int[] = {IA64::r32, IA64::r33, IA64::r34, IA64::r35,
115 IA64::r36, IA64::r37, IA64::r38, IA64::r39};
117 unsigned args_FP[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11,
118 IA64::F12,IA64::F13,IA64::F14, IA64::F15};
124 unsigned used_FPArgs = 0; // how many FP args have been used so far?
126 unsigned ArgOffset = 0;
129 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
131 SDOperand newroot, argt;
132 if(count < 8) { // need to fix this logic? maybe.
134 switch (getValueType(I->getType())) {
136 assert(0 && "ERROR in LowerArgs: can't lower this type of arg.\n");
138 // fixme? (well, will need to for weird FP structy stuff,
139 // see intel ABI docs)
141 //XXX BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]);
142 MF.addLiveIn(args_FP[used_FPArgs]); // mark this reg as liveIn
143 // floating point args go into f8..f15 as-needed, the increment
144 argVreg[count] = // is below..:
145 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::f64));
146 // FP args go into f8..f15 as needed: (hence the ++)
147 argPreg[count] = args_FP[used_FPArgs++];
148 argOpc[count] = IA64::FMOV;
149 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count],
151 if (I->getType() == Type::FloatTy)
152 argt = DAG.getNode(ISD::FP_ROUND, MVT::f32, argt);
154 case MVT::i1: // NOTE: as far as C abi stuff goes,
155 // bools are just boring old ints
160 //XXX BuildMI(&BB, IA64::IDEF, 0, args_int[count]);
161 MF.addLiveIn(args_int[count]); // mark this register as liveIn
163 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
164 argPreg[count] = args_int[count];
165 argOpc[count] = IA64::MOV;
167 DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], MVT::i64);
168 if ( getValueType(I->getType()) != MVT::i64)
169 argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()),
173 } else { // more than 8 args go into the frame
174 // Create the frame index object for this incoming parameter...
175 ArgOffset = 16 + 8 * (count - 8);
176 int FI = MFI->CreateFixedObject(8, ArgOffset);
178 // Create the SelectionDAG nodes corresponding to a load
179 //from this parameter
180 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
181 argt = newroot = DAG.getLoad(getValueType(I->getType()),
182 DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
185 DAG.setRoot(newroot.getValue(1));
186 ArgValues.push_back(argt);
190 // Create a vreg to hold the output of (what will become)
191 // the "alloc" instruction
192 VirtGPR = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
193 BuildMI(&BB, IA64::PSEUDO_ALLOC, 0, VirtGPR);
194 // we create a PSEUDO_ALLOC (pseudo)instruction for now
196 BuildMI(&BB, IA64::IDEF, 0, IA64::r1);
199 BuildMI(&BB, IA64::IDEF, 0, IA64::r12);
200 BuildMI(&BB, IA64::IDEF, 0, IA64::rp);
203 BuildMI(&BB, IA64::MOV, 1, GP).addReg(IA64::r1);
206 BuildMI(&BB, IA64::MOV, 1, SP).addReg(IA64::r12);
207 BuildMI(&BB, IA64::MOV, 1, RP).addReg(IA64::rp);
210 unsigned tempOffset=0;
212 // if this is a varargs function, we simply lower llvm.va_start by
213 // pointing to the first entry
216 VarArgsFrameIndex = MFI->CreateFixedObject(8, tempOffset);
219 // here we actually do the moving of args, and store them to the stack
220 // too if this is a varargs function:
221 for (int i = 0; i < count && i < 8; ++i) {
222 BuildMI(&BB, argOpc[i], 1, argVreg[i]).addReg(argPreg[i]);
224 // if this is a varargs function, we copy the input registers to the stack
225 int FI = MFI->CreateFixedObject(8, tempOffset);
226 tempOffset+=8; //XXX: is it safe to use r22 like this?
227 BuildMI(&BB, IA64::MOV, 1, IA64::r22).addFrameIndex(FI);
228 // FIXME: we should use st8.spill here, one day
229 BuildMI(&BB, IA64::ST8, 1, IA64::r22).addReg(argPreg[i]);
233 // Finally, inform the code generator which regs we return values in.
234 // (see the ISD::RET: case in the instruction selector)
235 switch (getValueType(F.getReturnType())) {
236 default: assert(0 && "i have no idea where to return this type!");
237 case MVT::isVoid: break;
243 MF.addLiveOut(IA64::r8);
247 MF.addLiveOut(IA64::F8);
254 std::pair<SDOperand, SDOperand>
255 IA64TargetLowering::LowerCallTo(SDOperand Chain,
256 const Type *RetTy, bool isVarArg,
257 unsigned CallingConv, bool isTailCall,
258 SDOperand Callee, ArgListTy &Args,
261 MachineFunction &MF = DAG.getMachineFunction();
263 unsigned NumBytes = 16;
264 unsigned outRegsUsed = 0;
266 if (Args.size() > 8) {
267 NumBytes += (Args.size() - 8) * 8;
270 outRegsUsed = Args.size();
273 // FIXME? this WILL fail if we ever try to pass around an arg that
274 // consumes more than a single output slot (a 'real' double, int128
275 // some sort of aggregate etc.), as we'll underestimate how many 'outX'
276 // registers we use. Hopefully, the assembler will notice.
277 MF.getInfo<IA64FunctionInfo>()->outRegsUsed=
278 std::max(outRegsUsed, MF.getInfo<IA64FunctionInfo>()->outRegsUsed);
280 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
281 DAG.getConstant(NumBytes, getPointerTy()));
283 std::vector<SDOperand> args_to_use;
284 for (unsigned i = 0, e = Args.size(); i != e; ++i)
286 switch (getValueType(Args[i].second)) {
287 default: assert(0 && "unexpected argument type!");
292 //promote to 64-bits, sign/zero extending based on type
294 if(Args[i].second->isSigned())
295 Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64,
298 Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64,
303 Args[i].first = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Args[i].first);
308 args_to_use.push_back(Args[i].first);
311 std::vector<MVT::ValueType> RetVals;
312 MVT::ValueType RetTyVT = getValueType(RetTy);
313 if (RetTyVT != MVT::isVoid)
314 RetVals.push_back(RetTyVT);
315 RetVals.push_back(MVT::Other);
317 SDOperand TheCall = SDOperand(DAG.getCall(RetVals, Chain,
318 Callee, args_to_use), 0);
319 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
320 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
321 DAG.getConstant(NumBytes, getPointerTy()));
322 return std::make_pair(TheCall, Chain);
326 IA64TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
327 Value *VAListV, SelectionDAG &DAG) {
328 // vastart just stores the address of the VarArgsFrameIndex slot.
329 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
330 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR,
331 VAListP, DAG.getSrcValue(VAListV));
334 std::pair<SDOperand,SDOperand> IA64TargetLowering::
335 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
336 const Type *ArgTy, SelectionDAG &DAG) {
338 MVT::ValueType ArgVT = getValueType(ArgTy);
339 SDOperand Val = DAG.getLoad(MVT::i64, Chain,
340 VAListP, DAG.getSrcValue(VAListV));
341 SDOperand Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), Val,
342 DAG.getSrcValue(NULL));
344 if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
347 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
348 "Other types should have been promoted for varargs!");
351 Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val,
352 DAG.getConstant(Amt, Val.getValueType()));
353 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
354 Val, VAListP, DAG.getSrcValue(VAListV));
355 return std::make_pair(Result, Chain);
360 std::pair<SDOperand, SDOperand> IA64TargetLowering::
361 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
363 assert(0 && "LowerFrameReturnAddress unimplemented");