1 //===-- IA64ISelLowering.cpp - IA64 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the IA64ISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "IA64ISelLowering.h"
15 #include "IA64MachineFunctionInfo.h"
16 #include "IA64TargetMachine.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
26 IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
27 : TargetLowering(TM) {
29 // register class for general registers
30 addRegisterClass(MVT::i64, IA64::GRRegisterClass);
32 // register class for FP registers
33 addRegisterClass(MVT::f64, IA64::FPRegisterClass);
35 // register class for predicate registers
36 addRegisterClass(MVT::i1, IA64::PRRegisterClass);
38 setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
39 setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
40 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
42 setSetCCResultType(MVT::i1);
43 setShiftAmountType(MVT::i64);
45 setOperationAction(ISD::EXTLOAD , MVT::i1 , Promote);
47 setOperationAction(ISD::ZEXTLOAD , MVT::i1 , Expand);
49 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
50 setOperationAction(ISD::SEXTLOAD , MVT::i8 , Expand);
51 setOperationAction(ISD::SEXTLOAD , MVT::i16 , Expand);
52 setOperationAction(ISD::SEXTLOAD , MVT::i32 , Expand);
54 setOperationAction(ISD::FREM , MVT::f32 , Expand);
55 setOperationAction(ISD::FREM , MVT::f64 , Expand);
57 setOperationAction(ISD::UREM , MVT::f32 , Expand);
58 setOperationAction(ISD::UREM , MVT::f64 , Expand);
60 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
61 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
62 setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
64 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
65 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
67 // We don't support sin/cos/sqrt
68 setOperationAction(ISD::FSIN , MVT::f64, Expand);
69 setOperationAction(ISD::FCOS , MVT::f64, Expand);
70 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
71 setOperationAction(ISD::FSIN , MVT::f32, Expand);
72 setOperationAction(ISD::FCOS , MVT::f32, Expand);
73 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
75 // We don't have line number support yet.
76 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
77 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
79 //IA64 has these, but they are not implemented
80 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
81 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
83 computeRegisterProperties();
85 addLegalFPImmediate(+0.0);
86 addLegalFPImmediate(+1.0);
89 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
90 static bool isFloatingPointZero(SDOperand Op) {
91 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
92 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
93 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
94 // Maybe this has already been legalized into the constant pool?
95 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
96 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
97 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
102 std::vector<SDOperand>
103 IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
104 std::vector<SDOperand> ArgValues;
106 // add beautiful description of IA64 stack frame format
107 // here (from intel 24535803.pdf most likely)
109 MachineFunction &MF = DAG.getMachineFunction();
110 MachineFrameInfo *MFI = MF.getFrameInfo();
112 GP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
113 SP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
114 RP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
116 MachineBasicBlock& BB = MF.front();
118 unsigned args_int[] = {IA64::r32, IA64::r33, IA64::r34, IA64::r35,
119 IA64::r36, IA64::r37, IA64::r38, IA64::r39};
121 unsigned args_FP[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11,
122 IA64::F12,IA64::F13,IA64::F14, IA64::F15};
128 unsigned used_FPArgs = 0; // how many FP args have been used so far?
130 unsigned ArgOffset = 0;
133 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
135 SDOperand newroot, argt;
136 if(count < 8) { // need to fix this logic? maybe.
138 switch (getValueType(I->getType())) {
140 assert(0 && "ERROR in LowerArgs: can't lower this type of arg.\n");
142 // fixme? (well, will need to for weird FP structy stuff,
143 // see intel ABI docs)
145 //XXX BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]);
146 MF.addLiveIn(args_FP[used_FPArgs]); // mark this reg as liveIn
147 // floating point args go into f8..f15 as-needed, the increment
148 argVreg[count] = // is below..:
149 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::f64));
150 // FP args go into f8..f15 as needed: (hence the ++)
151 argPreg[count] = args_FP[used_FPArgs++];
152 argOpc[count] = IA64::FMOV;
153 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), argVreg[count],
155 if (I->getType() == Type::FloatTy)
156 argt = DAG.getNode(ISD::FP_ROUND, MVT::f32, argt);
158 case MVT::i1: // NOTE: as far as C abi stuff goes,
159 // bools are just boring old ints
164 //XXX BuildMI(&BB, IA64::IDEF, 0, args_int[count]);
165 MF.addLiveIn(args_int[count]); // mark this register as liveIn
167 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
168 argPreg[count] = args_int[count];
169 argOpc[count] = IA64::MOV;
171 DAG.getCopyFromReg(DAG.getRoot(), argVreg[count], MVT::i64);
172 if ( getValueType(I->getType()) != MVT::i64)
173 argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()),
177 } else { // more than 8 args go into the frame
178 // Create the frame index object for this incoming parameter...
179 ArgOffset = 16 + 8 * (count - 8);
180 int FI = MFI->CreateFixedObject(8, ArgOffset);
182 // Create the SelectionDAG nodes corresponding to a load
183 //from this parameter
184 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
185 argt = newroot = DAG.getLoad(getValueType(I->getType()),
186 DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
189 DAG.setRoot(newroot.getValue(1));
190 ArgValues.push_back(argt);
194 // Create a vreg to hold the output of (what will become)
195 // the "alloc" instruction
196 VirtGPR = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
197 BuildMI(&BB, IA64::PSEUDO_ALLOC, 0, VirtGPR);
198 // we create a PSEUDO_ALLOC (pseudo)instruction for now
200 BuildMI(&BB, IA64::IDEF, 0, IA64::r1);
203 BuildMI(&BB, IA64::IDEF, 0, IA64::r12);
204 BuildMI(&BB, IA64::IDEF, 0, IA64::rp);
207 BuildMI(&BB, IA64::MOV, 1, GP).addReg(IA64::r1);
210 BuildMI(&BB, IA64::MOV, 1, SP).addReg(IA64::r12);
211 BuildMI(&BB, IA64::MOV, 1, RP).addReg(IA64::rp);
215 unsigned tempOffset=0;
217 // if this is a varargs function, we simply lower llvm.va_start by
218 // pointing to the first entry
221 VarArgsFrameIndex = MFI->CreateFixedObject(8, tempOffset);
224 // here we actually do the moving of args, and store them to the stack
225 // too if this is a varargs function:
226 for (int i = 0; i < count && i < 8; ++i) {
227 BuildMI(&BB, argOpc[i], 1, argVreg[i]).addReg(argPreg[i]);
229 // if this is a varargs function, we copy the input registers to the stack
230 int FI = MFI->CreateFixedObject(8, tempOffset);
231 tempOffset+=8; //XXX: is it safe to use r22 like this?
232 BuildMI(&BB, IA64::MOV, 1, IA64::r22).addFrameIndex(FI);
233 // FIXME: we should use st8.spill here, one day
234 BuildMI(&BB, IA64::ST8, 1, IA64::r22).addReg(argPreg[i]);
238 // Finally, inform the code generator which regs we return values in.
239 // (see the ISD::RET: case in the instruction selector)
240 switch (getValueType(F.getReturnType())) {
241 default: assert(0 && "i have no idea where to return this type!");
242 case MVT::isVoid: break;
248 MF.addLiveOut(IA64::r8);
252 MF.addLiveOut(IA64::F8);
259 std::pair<SDOperand, SDOperand>
260 IA64TargetLowering::LowerCallTo(SDOperand Chain,
261 const Type *RetTy, bool isVarArg,
262 unsigned CallingConv, bool isTailCall,
263 SDOperand Callee, ArgListTy &Args,
266 MachineFunction &MF = DAG.getMachineFunction();
268 unsigned NumBytes = 16;
269 unsigned outRegsUsed = 0;
271 if (Args.size() > 8) {
272 NumBytes += (Args.size() - 8) * 8;
275 outRegsUsed = Args.size();
278 // FIXME? this WILL fail if we ever try to pass around an arg that
279 // consumes more than a single output slot (a 'real' double, int128
280 // some sort of aggregate etc.), as we'll underestimate how many 'outX'
281 // registers we use. Hopefully, the assembler will notice.
282 MF.getInfo<IA64FunctionInfo>()->outRegsUsed=
283 std::max(outRegsUsed, MF.getInfo<IA64FunctionInfo>()->outRegsUsed);
285 // keep stack frame 16-byte aligned
286 //assert(NumBytes==((NumBytes+15) & ~15) && "stack frame not 16-byte aligned!");
287 NumBytes = (NumBytes+15) & ~15;
289 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
290 DAG.getConstant(NumBytes, getPointerTy()));
292 SDOperand StackPtr, NullSV;
293 std::vector<SDOperand> Stores;
294 std::vector<SDOperand> RegValuesToPass;
295 unsigned ArgOffset = 16;
297 for (unsigned i = 0, e = Args.size(); i != e; ++i)
299 SDOperand Val = Args[i].first;
300 MVT::ValueType ObjectVT = Val.getValueType();
301 SDOperand ValToStore;
304 default: assert(0 && "unexpected argument type!");
309 //promote to 64-bits, sign/zero extending based on type
311 if(Args[i].second->isSigned())
312 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Val);
314 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Val);
318 if(RegValuesToPass.size() >= 8) {
321 RegValuesToPass.push_back(Val);
326 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
329 if(RegValuesToPass.size() >= 8) {
332 RegValuesToPass.push_back(Val);
339 StackPtr = DAG.getRegister(IA64::r12, MVT::i64);
340 NullSV = DAG.getSrcValue(NULL);
342 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
343 PtrOff = DAG.getNode(ISD::ADD, MVT::i64, StackPtr, PtrOff);
344 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
345 ValToStore, PtrOff, NullSV));
347 ArgOffset += ObjSize;
350 // Emit all stores, make sure they occur before any copies into physregs.
352 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
354 static const unsigned IntArgRegs[] = {
355 IA64::out0, IA64::out1, IA64::out2, IA64::out3,
356 IA64::out4, IA64::out5, IA64::out6, IA64::out7
359 static const unsigned FPArgRegs[] = {
360 IA64::F8, IA64::F9, IA64::F10, IA64::F11,
361 IA64::F12, IA64::F13, IA64::F14, IA64::F15
366 // save the current GP, SP and RP : FIXME: do we need to do all 3 always?
367 SDOperand GPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r1, MVT::i64, InFlag);
368 Chain = GPBeforeCall;
369 InFlag = Chain.getValue(1);
370 SDOperand SPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r12, MVT::i64, InFlag);
371 Chain = SPBeforeCall;
372 InFlag = Chain.getValue(1);
373 SDOperand RPBeforeCall = DAG.getCopyFromReg(Chain, IA64::rp, MVT::i64, InFlag);
374 Chain = RPBeforeCall;
375 InFlag = Chain.getValue(1);
377 // Build a sequence of copy-to-reg nodes chained together with token chain
378 // and flag operands which copy the outgoing integer args into regs out[0-7]
379 // mapped 1:1 and the FP args into regs F8-F15 "lazily"
380 // TODO: for performance, we should only copy FP args into int regs when we
381 // know this is required (i.e. for varardic or external (unknown) functions)
382 unsigned usedFPArgs = 0;
383 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
384 Chain = DAG.getCopyToReg(Chain,
385 MVT::isInteger(RegValuesToPass[i].getValueType()) ?
386 IntArgRegs[i] : FPArgRegs[usedFPArgs++],
387 RegValuesToPass[i], InFlag);
388 InFlag = Chain.getValue(1);
390 //FIXME: for performance, only do the following when required
392 // if we have just copied an FP arg, copy its in-memory representation
393 // to the appropriate integer register
394 if(MVT::isFloatingPoint(RegValuesToPass[i].getValueType())) {
395 std::vector<MVT::ValueType> GETFDRetTypes;
396 std::vector<SDOperand> GETFDOperands;
397 GETFDRetTypes.push_back(MVT::i64);
398 GETFDRetTypes.push_back(MVT::Flag);
399 GETFDOperands.push_back(RegValuesToPass[i]);
400 GETFDOperands.push_back(Chain);
401 GETFDOperands.push_back(InFlag);
403 Chain = DAG.getNode(IA64ISD::GETFD, GETFDRetTypes, GETFDOperands);
404 Chain = DAG.getCopyToReg(Chain, IntArgRegs[i], Chain.getValue(0), Chain.getValue(1)); // ...thrice!
405 InFlag = Chain.getValue(1);
409 std::vector<MVT::ValueType> RetVals;
410 RetVals.push_back(MVT::Other);
411 RetVals.push_back(MVT::Flag);
413 // If the callee is a GlobalAddress node (quite common, every direct call is)
414 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
415 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
416 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i64);
418 std::vector<MVT::ValueType> NodeTys;
419 NodeTys.push_back(MVT::Other); // Returns a chain
420 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
422 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0);
424 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee), 0);
425 InFlag = Chain.getValue(1);
427 // restore the GP, SP and RP after the call
428 Chain = DAG.getCopyToReg(Chain, IA64::r1, GPBeforeCall, InFlag);
429 InFlag = Chain.getValue(1);
430 Chain = DAG.getCopyToReg(Chain, IA64::r12, SPBeforeCall, InFlag);
431 InFlag = Chain.getValue(1);
432 Chain = DAG.getCopyToReg(Chain, IA64::rp, RPBeforeCall, InFlag);
433 InFlag = Chain.getValue(1);
435 MVT::ValueType RetTyVT = getValueType(RetTy);
437 if (RetTyVT != MVT::isVoid) {
439 default: assert(0 && "Unknown value type to return!");
440 case MVT::i1:/* { // bools are just like other integers (returned in r8)
441 SDOperand boolInR8 = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
442 RetVal = DAG.getTargetNode(IA64::CMPNE, MVT::i1, // FIXME: is this flagged correctly?
443 DAG.getRegister(IA64::r0, MVT::i64), boolInR8, Chain, InFlag);
444 Chain = RetVal.getValue(1);
445 // Add a note to keep track of whether it is sign or zero extended - TODO: bools
446 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
447 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
448 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
454 RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
455 Chain = RetVal.getValue(1);
457 // Add a note to keep track of whether it is sign or zero extended - TODO: bools
458 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
459 MVT::i64, RetVal, DAG.getValueType(RetTyVT));
460 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
463 RetVal = DAG.getCopyFromReg(Chain, IA64::r8, MVT::i64, InFlag);
464 Chain = RetVal.getValue(1);
467 RetVal = DAG.getCopyFromReg(Chain, IA64::F8, MVT::f64, InFlag);
468 Chain = RetVal.getValue(1);
473 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
474 DAG.getConstant(NumBytes, getPointerTy()));
476 return std::make_pair(RetVal, Chain);
480 IA64TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
481 Value *VAListV, SelectionDAG &DAG) {
482 // vastart just stores the address of the VarArgsFrameIndex slot.
483 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
484 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR,
485 VAListP, DAG.getSrcValue(VAListV));
488 std::pair<SDOperand,SDOperand> IA64TargetLowering::
489 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
490 const Type *ArgTy, SelectionDAG &DAG) {
492 MVT::ValueType ArgVT = getValueType(ArgTy);
493 SDOperand Val = DAG.getLoad(MVT::i64, Chain,
494 VAListP, DAG.getSrcValue(VAListV));
495 SDOperand Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), Val,
496 DAG.getSrcValue(NULL));
498 if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
501 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
502 "Other types should have been promoted for varargs!");
505 Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val,
506 DAG.getConstant(Amt, Val.getValueType()));
507 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
508 Val, VAListP, DAG.getSrcValue(VAListV));
509 return std::make_pair(Result, Chain);
514 std::pair<SDOperand, SDOperand> IA64TargetLowering::
515 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
517 assert(0 && "LowerFrameReturnAddress unimplemented");