1 //===-- IA64ISelLowering.cpp - IA64 DAG Lowering Implementation -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the IA64ISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "IA64ISelLowering.h"
15 #include "IA64MachineFunctionInfo.h"
16 #include "IA64TargetMachine.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Function.h"
28 IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
29 : TargetLowering(TM) {
31 // register class for general registers
32 addRegisterClass(MVT::i64, IA64::GRRegisterClass);
34 // register class for FP registers
35 addRegisterClass(MVT::f64, IA64::FPRegisterClass);
37 // register class for predicate registers
38 addRegisterClass(MVT::i1, IA64::PRRegisterClass);
40 setLoadExtAction(ISD::EXTLOAD , MVT::i1 , Promote);
42 setLoadExtAction(ISD::ZEXTLOAD , MVT::i1 , Promote);
44 setLoadExtAction(ISD::SEXTLOAD , MVT::i1 , Promote);
45 setLoadExtAction(ISD::SEXTLOAD , MVT::i8 , Expand);
46 setLoadExtAction(ISD::SEXTLOAD , MVT::i16 , Expand);
47 setLoadExtAction(ISD::SEXTLOAD , MVT::i32 , Expand);
49 setOperationAction(ISD::BRIND , MVT::Other, Expand);
50 setOperationAction(ISD::BR_JT , MVT::Other, Expand);
51 setOperationAction(ISD::BR_CC , MVT::Other, Expand);
52 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
54 // ia64 uses SELECT not SELECT_CC
55 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand);
57 // We need to handle ISD::RET for void functions ourselves,
58 // so we get a chance to restore ar.pfs before adding a
60 setOperationAction(ISD::RET, MVT::Other, Custom);
62 setShiftAmountType(MVT::i64);
64 setOperationAction(ISD::FREM , MVT::f32 , Expand);
65 setOperationAction(ISD::FREM , MVT::f64 , Expand);
67 setOperationAction(ISD::UREM , MVT::f32 , Expand);
68 setOperationAction(ISD::UREM , MVT::f64 , Expand);
70 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
72 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
73 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
75 // We don't support sin/cos/sqrt/pow
76 setOperationAction(ISD::FSIN , MVT::f64, Expand);
77 setOperationAction(ISD::FCOS , MVT::f64, Expand);
78 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
79 setOperationAction(ISD::FPOW , MVT::f64, Expand);
80 setOperationAction(ISD::FSIN , MVT::f32, Expand);
81 setOperationAction(ISD::FCOS , MVT::f32, Expand);
82 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
83 setOperationAction(ISD::FPOW , MVT::f32, Expand);
85 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
87 // FIXME: IA64 supports fcopysign natively!
88 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
89 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
91 // We don't have line number support yet.
92 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
93 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
94 setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
95 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
97 // IA64 has ctlz in the form of the 'fnorm' instruction. The Legalizer
98 // expansion for ctlz/cttz in terms of ctpop is much larger, but lower
100 // FIXME: Custom lower CTLZ when compiling for size?
101 setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
102 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
103 setOperationAction(ISD::ROTL , MVT::i64 , Expand);
104 setOperationAction(ISD::ROTR , MVT::i64 , Expand);
106 // FIXME: IA64 has this, but is not implemented. should be mux @rev
107 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
109 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
110 setOperationAction(ISD::VAARG , MVT::Other, Custom);
111 setOperationAction(ISD::VASTART , MVT::Other, Custom);
113 // FIXME: These should be legal
114 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
115 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
117 // Use the default implementation.
118 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
119 setOperationAction(ISD::VAEND , MVT::Other, Expand);
120 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
121 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
122 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
124 // Thread Local Storage
125 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
127 setStackPointerRegisterToSaveRestore(IA64::r12);
129 setJumpBufSize(704); // on ia64-linux, jmp_bufs are 704 bytes..
130 setJumpBufAlignment(16); // ...and must be 16-byte aligned
132 computeRegisterProperties();
134 addLegalFPImmediate(APFloat(+0.0));
135 addLegalFPImmediate(APFloat(-0.0));
136 addLegalFPImmediate(APFloat(+1.0));
137 addLegalFPImmediate(APFloat(-1.0));
140 const char *IA64TargetLowering::getTargetNodeName(unsigned Opcode) const {
143 case IA64ISD::GETFD: return "IA64ISD::GETFD";
144 case IA64ISD::BRCALL: return "IA64ISD::BRCALL";
145 case IA64ISD::RET_FLAG: return "IA64ISD::RET_FLAG";
149 MVT IA64TargetLowering::getSetCCResultType(MVT VT) const {
153 /// getFunctionAlignment - Return the Log2 alignment of this function.
154 unsigned IA64TargetLowering::getFunctionAlignment(const Function *) const {
158 void IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
159 SmallVectorImpl<SDValue> &ArgValues,
162 // add beautiful description of IA64 stack frame format
163 // here (from intel 24535803.pdf most likely)
165 MachineFunction &MF = DAG.getMachineFunction();
166 MachineFrameInfo *MFI = MF.getFrameInfo();
167 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
169 GP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
170 SP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
171 RP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
173 MachineBasicBlock& BB = MF.front();
175 unsigned args_int[] = {IA64::r32, IA64::r33, IA64::r34, IA64::r35,
176 IA64::r36, IA64::r37, IA64::r38, IA64::r39};
178 unsigned args_FP[] = {IA64::F8, IA64::F9, IA64::F10, IA64::F11,
179 IA64::F12,IA64::F13,IA64::F14, IA64::F15};
185 unsigned used_FPArgs = 0; // how many FP args have been used so far?
187 unsigned ArgOffset = 0;
190 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
192 SDValue newroot, argt;
193 if(count < 8) { // need to fix this logic? maybe.
195 switch (getValueType(I->getType()).getSimpleVT()) {
197 assert(0 && "ERROR in LowerArgs: can't lower this type of arg.\n");
199 // fixme? (well, will need to for weird FP structy stuff,
200 // see intel ABI docs)
202 //XXX BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]);
203 MF.getRegInfo().addLiveIn(args_FP[used_FPArgs]);
204 // mark this reg as liveIn
205 // floating point args go into f8..f15 as-needed, the increment
206 argVreg[count] = // is below..:
207 MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::f64));
208 // FP args go into f8..f15 as needed: (hence the ++)
209 argPreg[count] = args_FP[used_FPArgs++];
210 argOpc[count] = IA64::FMOV;
211 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), dl,
212 argVreg[count], MVT::f64);
213 if (I->getType() == Type::FloatTy)
214 argt = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, argt,
215 DAG.getIntPtrConstant(0));
217 case MVT::i1: // NOTE: as far as C abi stuff goes,
218 // bools are just boring old ints
223 //XXX BuildMI(&BB, IA64::IDEF, 0, args_int[count]);
224 MF.getRegInfo().addLiveIn(args_int[count]);
225 // mark this register as liveIn
227 MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
228 argPreg[count] = args_int[count];
229 argOpc[count] = IA64::MOV;
231 DAG.getCopyFromReg(DAG.getRoot(), dl, argVreg[count], MVT::i64);
232 if ( getValueType(I->getType()) != MVT::i64)
233 argt = DAG.getNode(ISD::TRUNCATE, dl, getValueType(I->getType()),
237 } else { // more than 8 args go into the frame
238 // Create the frame index object for this incoming parameter...
239 ArgOffset = 16 + 8 * (count - 8);
240 int FI = MFI->CreateFixedObject(8, ArgOffset);
242 // Create the SelectionDAG nodes corresponding to a load
243 //from this parameter
244 SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
245 argt = newroot = DAG.getLoad(getValueType(I->getType()), dl,
246 DAG.getEntryNode(), FIN, NULL, 0);
249 DAG.setRoot(newroot.getValue(1));
250 ArgValues.push_back(argt);
254 // Create a vreg to hold the output of (what will become)
255 // the "alloc" instruction
256 VirtGPR = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
257 BuildMI(&BB, dl, TII->get(IA64::PSEUDO_ALLOC), VirtGPR);
258 // we create a PSEUDO_ALLOC (pseudo)instruction for now
260 BuildMI(&BB, IA64::IDEF, 0, IA64::r1);
263 BuildMI(&BB, IA64::IDEF, 0, IA64::r12);
264 BuildMI(&BB, IA64::IDEF, 0, IA64::rp);
267 BuildMI(&BB, IA64::MOV, 1, GP).addReg(IA64::r1);
270 BuildMI(&BB, IA64::MOV, 1, SP).addReg(IA64::r12);
271 BuildMI(&BB, IA64::MOV, 1, RP).addReg(IA64::rp);
275 unsigned tempOffset=0;
277 // if this is a varargs function, we simply lower llvm.va_start by
278 // pointing to the first entry
281 VarArgsFrameIndex = MFI->CreateFixedObject(8, tempOffset);
284 // here we actually do the moving of args, and store them to the stack
285 // too if this is a varargs function:
286 for (int i = 0; i < count && i < 8; ++i) {
287 BuildMI(&BB, dl, TII->get(argOpc[i]), argVreg[i]).addReg(argPreg[i]);
289 // if this is a varargs function, we copy the input registers to the stack
290 int FI = MFI->CreateFixedObject(8, tempOffset);
291 tempOffset+=8; //XXX: is it safe to use r22 like this?
292 BuildMI(&BB, dl, TII->get(IA64::MOV), IA64::r22).addFrameIndex(FI);
293 // FIXME: we should use st8.spill here, one day
294 BuildMI(&BB, dl, TII->get(IA64::ST8), IA64::r22).addReg(argPreg[i]);
298 // Finally, inform the code generator which regs we return values in.
299 // (see the ISD::RET: case in the instruction selector)
300 switch (getValueType(F.getReturnType()).getSimpleVT()) {
301 default: assert(0 && "i have no idea where to return this type!");
302 case MVT::isVoid: break;
308 MF.getRegInfo().addLiveOut(IA64::r8);
312 MF.getRegInfo().addLiveOut(IA64::F8);
317 std::pair<SDValue, SDValue>
318 IA64TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
319 bool RetSExt, bool RetZExt, bool isVarArg,
320 bool isInreg, unsigned NumFixedArgs,
321 unsigned CallingConv,
322 bool isTailCall, SDValue Callee,
323 ArgListTy &Args, SelectionDAG &DAG,
326 MachineFunction &MF = DAG.getMachineFunction();
328 unsigned NumBytes = 16;
329 unsigned outRegsUsed = 0;
331 if (Args.size() > 8) {
332 NumBytes += (Args.size() - 8) * 8;
335 outRegsUsed = Args.size();
338 // FIXME? this WILL fail if we ever try to pass around an arg that
339 // consumes more than a single output slot (a 'real' double, int128
340 // some sort of aggregate etc.), as we'll underestimate how many 'outX'
341 // registers we use. Hopefully, the assembler will notice.
342 MF.getInfo<IA64FunctionInfo>()->outRegsUsed=
343 std::max(outRegsUsed, MF.getInfo<IA64FunctionInfo>()->outRegsUsed);
345 // keep stack frame 16-byte aligned
346 // assert(NumBytes==((NumBytes+15) & ~15) &&
347 // "stack frame not 16-byte aligned!");
348 NumBytes = (NumBytes+15) & ~15;
350 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
353 std::vector<SDValue> Stores;
354 std::vector<SDValue> Converts;
355 std::vector<SDValue> RegValuesToPass;
356 unsigned ArgOffset = 16;
358 for (unsigned i = 0, e = Args.size(); i != e; ++i)
360 SDValue Val = Args[i].Node;
361 MVT ObjectVT = Val.getValueType();
362 SDValue ValToStore(0, 0), ValToConvert(0, 0);
364 switch (ObjectVT.getSimpleVT()) {
365 default: assert(0 && "unexpected argument type!");
370 //promote to 64-bits, sign/zero extending based on type
372 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
374 ExtendKind = ISD::SIGN_EXTEND;
375 else if (Args[i].isZExt)
376 ExtendKind = ISD::ZERO_EXTEND;
377 Val = DAG.getNode(ExtendKind, dl, MVT::i64, Val);
382 if(RegValuesToPass.size() >= 8) {
385 RegValuesToPass.push_back(Val);
390 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
393 if(RegValuesToPass.size() >= 8) {
396 RegValuesToPass.push_back(Val);
397 if(1 /* TODO: if(calling external or varadic function)*/ ) {
398 ValToConvert = Val; // additionally pass this FP value as an int
404 if(ValToStore.getNode()) {
405 if(!StackPtr.getNode()) {
406 StackPtr = DAG.getRegister(IA64::r12, MVT::i64);
408 SDValue PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
409 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, PtrOff);
410 Stores.push_back(DAG.getStore(Chain, dl, ValToStore, PtrOff, NULL, 0));
411 ArgOffset += ObjSize;
414 if(ValToConvert.getNode()) {
415 Converts.push_back(DAG.getNode(IA64ISD::GETFD, dl,
416 MVT::i64, ValToConvert));
420 // Emit all stores, make sure they occur before any copies into physregs.
422 Chain = DAG.getNode(ISD::TokenFactor, dl,
423 MVT::Other, &Stores[0],Stores.size());
425 static const unsigned IntArgRegs[] = {
426 IA64::out0, IA64::out1, IA64::out2, IA64::out3,
427 IA64::out4, IA64::out5, IA64::out6, IA64::out7
430 static const unsigned FPArgRegs[] = {
431 IA64::F8, IA64::F9, IA64::F10, IA64::F11,
432 IA64::F12, IA64::F13, IA64::F14, IA64::F15
437 // save the current GP, SP and RP : FIXME: do we need to do all 3 always?
438 SDValue GPBeforeCall = DAG.getCopyFromReg(Chain, dl, IA64::r1,
440 Chain = GPBeforeCall.getValue(1);
441 InFlag = Chain.getValue(2);
442 SDValue SPBeforeCall = DAG.getCopyFromReg(Chain, dl, IA64::r12,
444 Chain = SPBeforeCall.getValue(1);
445 InFlag = Chain.getValue(2);
446 SDValue RPBeforeCall = DAG.getCopyFromReg(Chain, dl, IA64::rp,
448 Chain = RPBeforeCall.getValue(1);
449 InFlag = Chain.getValue(2);
451 // Build a sequence of copy-to-reg nodes chained together with token chain
452 // and flag operands which copy the outgoing integer args into regs out[0-7]
453 // mapped 1:1 and the FP args into regs F8-F15 "lazily"
454 // TODO: for performance, we should only copy FP args into int regs when we
455 // know this is required (i.e. for varardic or external (unknown) functions)
457 // first to the FP->(integer representation) conversions, these are
458 // flagged for now, but shouldn't have to be (TODO)
459 unsigned seenConverts = 0;
460 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
461 if(RegValuesToPass[i].getValueType().isFloatingPoint()) {
462 Chain = DAG.getCopyToReg(Chain, dl, IntArgRegs[i],
463 Converts[seenConverts++], InFlag);
464 InFlag = Chain.getValue(1);
468 // next copy args into the usual places, these are flagged
469 unsigned usedFPArgs = 0;
470 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
471 Chain = DAG.getCopyToReg(Chain, dl,
472 RegValuesToPass[i].getValueType().isInteger() ?
473 IntArgRegs[i] : FPArgRegs[usedFPArgs++], RegValuesToPass[i], InFlag);
474 InFlag = Chain.getValue(1);
477 // If the callee is a GlobalAddress node (quite common, every direct call is)
478 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
480 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
481 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i64);
485 std::vector<MVT> NodeTys;
486 std::vector<SDValue> CallOperands;
487 NodeTys.push_back(MVT::Other); // Returns a chain
488 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
489 CallOperands.push_back(Chain);
490 CallOperands.push_back(Callee);
492 // emit the call itself
493 if (InFlag.getNode())
494 CallOperands.push_back(InFlag);
496 assert(0 && "this should never happen!\n");
498 // to make way for a hack:
499 Chain = DAG.getNode(IA64ISD::BRCALL, dl, NodeTys,
500 &CallOperands[0], CallOperands.size());
501 InFlag = Chain.getValue(1);
503 // restore the GP, SP and RP after the call
504 Chain = DAG.getCopyToReg(Chain, dl, IA64::r1, GPBeforeCall, InFlag);
505 InFlag = Chain.getValue(1);
506 Chain = DAG.getCopyToReg(Chain, dl, IA64::r12, SPBeforeCall, InFlag);
507 InFlag = Chain.getValue(1);
508 Chain = DAG.getCopyToReg(Chain, dl, IA64::rp, RPBeforeCall, InFlag);
509 InFlag = Chain.getValue(1);
511 std::vector<MVT> RetVals;
512 RetVals.push_back(MVT::Other);
513 RetVals.push_back(MVT::Flag);
515 MVT RetTyVT = getValueType(RetTy);
517 if (RetTyVT != MVT::isVoid) {
518 switch (RetTyVT.getSimpleVT()) {
519 default: assert(0 && "Unknown value type to return!");
520 case MVT::i1: { // bools are just like other integers (returned in r8)
521 // we *could* fall through to the truncate below, but this saves a
522 // few redundant predicate ops
523 SDValue boolInR8 = DAG.getCopyFromReg(Chain, dl, IA64::r8,
525 InFlag = boolInR8.getValue(2);
526 Chain = boolInR8.getValue(1);
527 SDValue zeroReg = DAG.getCopyFromReg(Chain, dl, IA64::r0,
529 InFlag = zeroReg.getValue(2);
530 Chain = zeroReg.getValue(1);
532 RetVal = DAG.getSetCC(dl, MVT::i1, boolInR8, zeroReg, ISD::SETNE);
538 RetVal = DAG.getCopyFromReg(Chain, dl, IA64::r8, MVT::i64, InFlag);
539 Chain = RetVal.getValue(1);
541 // keep track of whether it is sign or zero extended (todo: bools?)
543 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
544 dl, MVT::i64, RetVal, DAG.getValueType(RetTyVT));
546 RetVal = DAG.getNode(ISD::TRUNCATE, dl, RetTyVT, RetVal);
549 RetVal = DAG.getCopyFromReg(Chain, dl, IA64::r8, MVT::i64, InFlag);
550 Chain = RetVal.getValue(1);
551 InFlag = RetVal.getValue(2); // XXX dead
554 RetVal = DAG.getCopyFromReg(Chain, dl, IA64::F8, MVT::f64, InFlag);
555 Chain = RetVal.getValue(1);
556 RetVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, RetVal,
557 DAG.getIntPtrConstant(0));
560 RetVal = DAG.getCopyFromReg(Chain, dl, IA64::F8, MVT::f64, InFlag);
561 Chain = RetVal.getValue(1);
562 InFlag = RetVal.getValue(2); // XXX dead
567 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
568 DAG.getIntPtrConstant(0, true), SDValue());
569 return std::make_pair(RetVal, Chain);
572 SDValue IA64TargetLowering::
573 LowerOperation(SDValue Op, SelectionDAG &DAG) {
574 DebugLoc dl = Op.getDebugLoc();
575 switch (Op.getOpcode()) {
576 default: assert(0 && "Should not custom lower this!");
577 case ISD::GlobalTLSAddress:
578 assert(0 && "TLS not implemented for IA64.");
580 SDValue AR_PFSVal, Copy;
582 switch(Op.getNumOperands()) {
584 LLVM_UNREACHABLE("Do not know how to return this many arguments!");
586 AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), dl, VirtGPR, MVT::i64);
587 AR_PFSVal = DAG.getCopyToReg(AR_PFSVal.getValue(1), dl, IA64::AR_PFS,
589 return DAG.getNode(IA64ISD::RET_FLAG, dl, MVT::Other, AR_PFSVal);
591 // Copy the result into the output register & restore ar.pfs
592 MVT ArgVT = Op.getOperand(1).getValueType();
593 unsigned ArgReg = ArgVT.isInteger() ? IA64::r8 : IA64::F8;
595 AR_PFSVal = DAG.getCopyFromReg(Op.getOperand(0), dl, VirtGPR, MVT::i64);
596 Copy = DAG.getCopyToReg(AR_PFSVal.getValue(1), dl, ArgReg,
597 Op.getOperand(1), SDValue());
598 AR_PFSVal = DAG.getCopyToReg(Copy.getValue(0), dl,
599 IA64::AR_PFS, AR_PFSVal, Copy.getValue(1));
600 return DAG.getNode(IA64ISD::RET_FLAG, dl, MVT::Other,
601 AR_PFSVal, AR_PFSVal.getValue(1));
607 MVT VT = getPointerTy();
608 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
609 SDValue VAList = DAG.getLoad(VT, dl, Op.getOperand(0), Op.getOperand(1),
611 // Increment the pointer, VAList, to the next vaarg
612 SDValue VAIncr = DAG.getNode(ISD::ADD, dl, VT, VAList,
613 DAG.getConstant(VT.getSizeInBits()/8,
615 // Store the incremented VAList to the legalized pointer
616 VAIncr = DAG.getStore(VAList.getValue(1), dl, VAIncr,
617 Op.getOperand(1), SV, 0);
618 // Load the actual argument out of the pointer VAList
619 return DAG.getLoad(Op.getValueType(), dl, VAIncr, VAList, NULL, 0);
622 // vastart just stores the address of the VarArgsFrameIndex slot into the
623 // memory location argument.
624 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i64);
625 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
626 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
628 // Frame & Return address. Currently unimplemented
629 case ISD::RETURNADDR: break;
630 case ISD::FRAMEADDR: break;