1 //===- IA64InstrFormats.td - IA64 Instruction Formats --*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // - Warning: the stuff in here isn't really being used, so is mostly
11 // junk. It'll get fixed as the JIT gets built.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Instruction format superclass
17 //===----------------------------------------------------------------------===//
19 class InstIA64<bits<4> op, dag OL, string asmstr> : Instruction {
20 // IA64 instruction baseline
22 let Namespace = "IA64";
24 let AsmString = asmstr;
29 //"Each Itanium instruction is categorized into one of six types."
33 class AForm<bits<4> opcode, bits<6> qpReg, dag OL, string asmstr> :
34 InstIA64<opcode, OL, asmstr> {
36 let Inst{5-0} = qpReg;
39 class AForm_DAG<bits<4> opcode, bits<6> qpReg, dag OL, string asmstr,
41 InstIA64<opcode, OL, asmstr> {
43 let Pattern = pattern;
44 let Inst{5-0} = qpReg;
47 let isBranch = 1, isTerminator = 1 in
48 class BForm<bits<4> opcode, bits<6> x6, bits<3> btype, dag OL, string asmstr> :
49 InstIA64<opcode, OL, asmstr> {
52 let Inst{8-6} = btype;
55 class MForm<bits<4> opcode, bits<6> x6, dag OL, string asmstr> :
56 InstIA64<opcode, OL, asmstr> {
62 // let Inst{20-16} = Rb;
63 let Inst{15-0} = disp;
66 class RawForm<bits<4> opcode, bits<26> rest, dag OL, string asmstr> :
67 InstIA64<opcode, OL, asmstr> {
68 let Inst{25-0} = rest;
71 // Pseudo instructions.
72 class PseudoInstIA64<dag OL, string nm> : InstIA64<0, OL, nm> {
75 class PseudoInstIA64_DAG<dag OL, string nm, list<dag> pattern>
76 : InstIA64<0, OL, nm> {
77 let Pattern = pattern;