1 //===- IA64InstrInfo.cpp - IA64 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the IA64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "IA64InstrInfo.h"
16 #include "IA64InstrBuilder.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "IA64GenInstrInfo.inc"
21 IA64InstrInfo::IA64InstrInfo()
22 : TargetInstrInfoImpl(IA64Insts, sizeof(IA64Insts)/sizeof(IA64Insts[0])),
27 bool IA64InstrInfo::isMoveInstr(const MachineInstr& MI,
29 unsigned& destReg) const {
30 unsigned oc = MI.getOpcode();
31 if (oc == IA64::MOV || oc == IA64::FMOV) {
32 // TODO: this doesn't detect predicate moves
33 assert(MI.getNumOperands() >= 2 &&
34 /* MI.getOperand(0).isRegister() &&
35 MI.getOperand(1).isRegister() && */
36 "invalid register-register move instruction");
37 if( MI.getOperand(0).isRegister() &&
38 MI.getOperand(1).isRegister() ) {
39 // if both operands of the MOV/FMOV are registers, then
40 // yes, this is a move instruction
41 sourceReg = MI.getOperand(1).getReg();
42 destReg = MI.getOperand(0).getReg();
46 return false; // we don't consider e.g. %regN = MOV <FrameIndex #x> a
51 IA64InstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
52 MachineBasicBlock *FBB,
53 const std::vector<MachineOperand> &Cond)const {
54 // Can only insert uncond branches so far.
55 assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
56 BuildMI(&MBB, get(IA64::BRL_NOTCALL)).addMBB(TBB);
60 void IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
61 MachineBasicBlock::iterator MI,
62 unsigned DestReg, unsigned SrcReg,
63 const TargetRegisterClass *DestRC,
64 const TargetRegisterClass *SrcRC) const {
65 if (DestRC != SrcRC) {
66 cerr << "Not yet supported!";
70 if(DestRC == IA64::PRRegisterClass ) // if a bool, we use pseudocode
71 // (SrcReg) DestReg = cmp.eq.unc(r0, r0)
72 BuildMI(MBB, MI, get(IA64::PCMPEQUNC), DestReg)
73 .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
74 else // otherwise, MOV works (for both gen. regs and FP regs)
75 BuildMI(MBB, MI, get(IA64::MOV), DestReg).addReg(SrcReg);
78 void IA64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
79 MachineBasicBlock::iterator MI,
80 unsigned SrcReg, bool isKill,
82 const TargetRegisterClass *RC) const{
84 if (RC == IA64::FPRegisterClass) {
85 BuildMI(MBB, MI, get(IA64::STF_SPILL)).addFrameIndex(FrameIdx)
86 .addReg(SrcReg, false, false, isKill);
87 } else if (RC == IA64::GRRegisterClass) {
88 BuildMI(MBB, MI, get(IA64::ST8)).addFrameIndex(FrameIdx)
89 .addReg(SrcReg, false, false, isKill);
90 } else if (RC == IA64::PRRegisterClass) {
91 /* we use IA64::r2 as a temporary register for doing this hackery. */
93 BuildMI(MBB, MI, get(IA64::MOV), IA64::r2).addReg(IA64::r0);
94 // then conditionally add 1:
95 BuildMI(MBB, MI, get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2)
96 .addImm(1).addReg(SrcReg, false, false, isKill);
97 // and then store it to the stack
98 BuildMI(MBB, MI, get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(IA64::r2);
100 "sorry, I don't know how to store this sort of reg in the stack\n");
103 void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
105 SmallVectorImpl<MachineOperand> &Addr,
106 const TargetRegisterClass *RC,
107 SmallVectorImpl<MachineInstr*> &NewMIs) const {
109 if (RC == IA64::FPRegisterClass) {
111 } else if (RC == IA64::GRRegisterClass) {
113 } else if (RC == IA64::PRRegisterClass) {
117 "sorry, I don't know how to store this sort of reg\n");
120 MachineInstrBuilder MIB = BuildMI(get(Opc));
121 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
122 MachineOperand &MO = Addr[i];
124 MIB.addReg(MO.getReg());
125 else if (MO.isImmediate())
126 MIB.addImm(MO.getImm());
128 MIB.addFrameIndex(MO.getIndex());
130 MIB.addReg(SrcReg, false, false, isKill);
131 NewMIs.push_back(MIB);
136 void IA64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
137 MachineBasicBlock::iterator MI,
138 unsigned DestReg, int FrameIdx,
139 const TargetRegisterClass *RC)const{
141 if (RC == IA64::FPRegisterClass) {
142 BuildMI(MBB, MI, get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx);
143 } else if (RC == IA64::GRRegisterClass) {
144 BuildMI(MBB, MI, get(IA64::LD8), DestReg).addFrameIndex(FrameIdx);
145 } else if (RC == IA64::PRRegisterClass) {
146 // first we load a byte from the stack into r2, our 'predicate hackery'
148 BuildMI(MBB, MI, get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx);
149 // then we compare it to zero. If it _is_ zero, compare-not-equal to
150 // r0 gives us 0, which is what we want, so that's nice.
151 BuildMI(MBB, MI, get(IA64::CMPNE), DestReg).addReg(IA64::r2).addReg(IA64::r0);
153 "sorry, I don't know how to load this sort of reg from the stack\n");
156 void IA64InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
157 SmallVectorImpl<MachineOperand> &Addr,
158 const TargetRegisterClass *RC,
159 SmallVectorImpl<MachineInstr*> &NewMIs) const {
161 if (RC == IA64::FPRegisterClass) {
163 } else if (RC == IA64::GRRegisterClass) {
165 } else if (RC == IA64::PRRegisterClass) {
169 "sorry, I don't know how to store this sort of reg\n");
172 MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
173 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
174 MachineOperand &MO = Addr[i];
176 MIB.addReg(MO.getReg());
177 else if (MO.isImmediate())
178 MIB.addImm(MO.getImm());
180 MIB.addFrameIndex(MO.getIndex());
182 NewMIs.push_back(MIB);