1 //===- IA64InstrInfo.cpp - IA64 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the IA64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "IA64InstrInfo.h"
16 #include "IA64InstrBuilder.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "IA64GenInstrInfo.inc"
21 IA64InstrInfo::IA64InstrInfo()
22 : TargetInstrInfoImpl(IA64Insts, sizeof(IA64Insts)/sizeof(IA64Insts[0])),
27 bool IA64InstrInfo::isMoveInstr(const MachineInstr& MI,
29 unsigned& destReg) const {
30 unsigned oc = MI.getOpcode();
31 if (oc == IA64::MOV || oc == IA64::FMOV) {
32 // TODO: this doesn't detect predicate moves
33 assert(MI.getNumOperands() >= 2 &&
34 /* MI.getOperand(0).isRegister() &&
35 MI.getOperand(1).isRegister() && */
36 "invalid register-register move instruction");
37 if( MI.getOperand(0).isRegister() &&
38 MI.getOperand(1).isRegister() ) {
39 // if both operands of the MOV/FMOV are registers, then
40 // yes, this is a move instruction
41 sourceReg = MI.getOperand(1).getReg();
42 destReg = MI.getOperand(0).getReg();
46 return false; // we don't consider e.g. %regN = MOV <FrameIndex #x> a
51 IA64InstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
52 MachineBasicBlock *FBB,
53 const SmallVectorImpl<MachineOperand> &Cond)const {
54 // Can only insert uncond branches so far.
55 assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
56 BuildMI(&MBB, get(IA64::BRL_NOTCALL)).addMBB(TBB);
60 bool IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
61 MachineBasicBlock::iterator MI,
62 unsigned DestReg, unsigned SrcReg,
63 const TargetRegisterClass *DestRC,
64 const TargetRegisterClass *SrcRC) const {
65 if (DestRC != SrcRC) {
70 if(DestRC == IA64::PRRegisterClass ) // if a bool, we use pseudocode
71 // (SrcReg) DestReg = cmp.eq.unc(r0, r0)
72 BuildMI(MBB, MI, get(IA64::PCMPEQUNC), DestReg)
73 .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
74 else // otherwise, MOV works (for both gen. regs and FP regs)
75 BuildMI(MBB, MI, get(IA64::MOV), DestReg).addReg(SrcReg);
80 void IA64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator MI,
82 unsigned SrcReg, bool isKill,
84 const TargetRegisterClass *RC) const{
86 if (RC == IA64::FPRegisterClass) {
87 BuildMI(MBB, MI, get(IA64::STF_SPILL)).addFrameIndex(FrameIdx)
88 .addReg(SrcReg, false, false, isKill);
89 } else if (RC == IA64::GRRegisterClass) {
90 BuildMI(MBB, MI, get(IA64::ST8)).addFrameIndex(FrameIdx)
91 .addReg(SrcReg, false, false, isKill);
92 } else if (RC == IA64::PRRegisterClass) {
93 /* we use IA64::r2 as a temporary register for doing this hackery. */
95 BuildMI(MBB, MI, get(IA64::MOV), IA64::r2).addReg(IA64::r0);
96 // then conditionally add 1:
97 BuildMI(MBB, MI, get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2)
98 .addImm(1).addReg(SrcReg, false, false, isKill);
99 // and then store it to the stack
100 BuildMI(MBB, MI, get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(IA64::r2);
102 "sorry, I don't know how to store this sort of reg in the stack\n");
105 void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
107 SmallVectorImpl<MachineOperand> &Addr,
108 const TargetRegisterClass *RC,
109 SmallVectorImpl<MachineInstr*> &NewMIs) const {
111 if (RC == IA64::FPRegisterClass) {
113 } else if (RC == IA64::GRRegisterClass) {
115 } else if (RC == IA64::PRRegisterClass) {
119 "sorry, I don't know how to store this sort of reg\n");
122 MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
123 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
124 MachineOperand &MO = Addr[i];
126 MIB.addReg(MO.getReg());
127 else if (MO.isImmediate())
128 MIB.addImm(MO.getImm());
130 MIB.addFrameIndex(MO.getIndex());
132 MIB.addReg(SrcReg, false, false, isKill);
133 NewMIs.push_back(MIB);
138 void IA64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
139 MachineBasicBlock::iterator MI,
140 unsigned DestReg, int FrameIdx,
141 const TargetRegisterClass *RC)const{
143 if (RC == IA64::FPRegisterClass) {
144 BuildMI(MBB, MI, get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx);
145 } else if (RC == IA64::GRRegisterClass) {
146 BuildMI(MBB, MI, get(IA64::LD8), DestReg).addFrameIndex(FrameIdx);
147 } else if (RC == IA64::PRRegisterClass) {
148 // first we load a byte from the stack into r2, our 'predicate hackery'
150 BuildMI(MBB, MI, get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx);
151 // then we compare it to zero. If it _is_ zero, compare-not-equal to
152 // r0 gives us 0, which is what we want, so that's nice.
153 BuildMI(MBB, MI, get(IA64::CMPNE), DestReg).addReg(IA64::r2).addReg(IA64::r0);
155 "sorry, I don't know how to load this sort of reg from the stack\n");
158 void IA64InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
159 SmallVectorImpl<MachineOperand> &Addr,
160 const TargetRegisterClass *RC,
161 SmallVectorImpl<MachineInstr*> &NewMIs) const {
163 if (RC == IA64::FPRegisterClass) {
165 } else if (RC == IA64::GRRegisterClass) {
167 } else if (RC == IA64::PRRegisterClass) {
171 "sorry, I don't know how to store this sort of reg\n");
174 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
175 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
176 MachineOperand &MO = Addr[i];
178 MIB.addReg(MO.getReg());
179 else if (MO.isImmediate())
180 MIB.addImm(MO.getImm());
182 MIB.addFrameIndex(MO.getIndex());
184 NewMIs.push_back(MIB);