1 //===- IA64InstrInfo.cpp - IA64 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the IA64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "IA64InstrInfo.h"
16 #include "IA64InstrBuilder.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "IA64GenInstrInfo.inc"
22 IA64InstrInfo::IA64InstrInfo()
23 : TargetInstrInfoImpl(IA64Insts, sizeof(IA64Insts)/sizeof(IA64Insts[0])),
28 bool IA64InstrInfo::isMoveInstr(const MachineInstr& MI,
31 unsigned& SrcSR, unsigned& DstSR) const {
32 SrcSR = DstSR = 0; // No sub-registers.
34 unsigned oc = MI.getOpcode();
35 if (oc == IA64::MOV || oc == IA64::FMOV) {
36 // TODO: this doesn't detect predicate moves
37 assert(MI.getNumOperands() >= 2 &&
38 /* MI.getOperand(0).isReg() &&
39 MI.getOperand(1).isReg() && */
40 "invalid register-register move instruction");
41 if (MI.getOperand(0).isReg() &&
42 MI.getOperand(1).isReg()) {
43 // if both operands of the MOV/FMOV are registers, then
44 // yes, this is a move instruction
45 sourceReg = MI.getOperand(1).getReg();
46 destReg = MI.getOperand(0).getReg();
50 return false; // we don't consider e.g. %regN = MOV <FrameIndex #x> a
55 IA64InstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
56 MachineBasicBlock *FBB,
57 const SmallVectorImpl<MachineOperand> &Cond)const {
58 // Can only insert uncond branches so far.
59 assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
60 BuildMI(&MBB, get(IA64::BRL_NOTCALL)).addMBB(TBB);
64 bool IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
65 MachineBasicBlock::iterator MI,
66 unsigned DestReg, unsigned SrcReg,
67 const TargetRegisterClass *DestRC,
68 const TargetRegisterClass *SrcRC) const {
69 if (DestRC != SrcRC) {
74 if(DestRC == IA64::PRRegisterClass ) // if a bool, we use pseudocode
75 // (SrcReg) DestReg = cmp.eq.unc(r0, r0)
76 BuildMI(MBB, MI, get(IA64::PCMPEQUNC), DestReg)
77 .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
78 else // otherwise, MOV works (for both gen. regs and FP regs)
79 BuildMI(MBB, MI, get(IA64::MOV), DestReg).addReg(SrcReg);
84 void IA64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
85 MachineBasicBlock::iterator MI,
86 unsigned SrcReg, bool isKill,
88 const TargetRegisterClass *RC) const{
90 if (RC == IA64::FPRegisterClass) {
91 BuildMI(MBB, MI, get(IA64::STF_SPILL)).addFrameIndex(FrameIdx)
92 .addReg(SrcReg, false, false, isKill);
93 } else if (RC == IA64::GRRegisterClass) {
94 BuildMI(MBB, MI, get(IA64::ST8)).addFrameIndex(FrameIdx)
95 .addReg(SrcReg, false, false, isKill);
96 } else if (RC == IA64::PRRegisterClass) {
97 /* we use IA64::r2 as a temporary register for doing this hackery. */
99 BuildMI(MBB, MI, get(IA64::MOV), IA64::r2).addReg(IA64::r0);
100 // then conditionally add 1:
101 BuildMI(MBB, MI, get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2)
102 .addImm(1).addReg(SrcReg, false, false, isKill);
103 // and then store it to the stack
104 BuildMI(MBB, MI, get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(IA64::r2);
106 "sorry, I don't know how to store this sort of reg in the stack\n");
109 void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
111 SmallVectorImpl<MachineOperand> &Addr,
112 const TargetRegisterClass *RC,
113 SmallVectorImpl<MachineInstr*> &NewMIs) const {
115 if (RC == IA64::FPRegisterClass) {
117 } else if (RC == IA64::GRRegisterClass) {
119 } else if (RC == IA64::PRRegisterClass) {
123 "sorry, I don't know how to store this sort of reg\n");
126 MachineInstrBuilder MIB = BuildMI(MF, get(Opc));
127 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
128 MachineOperand &MO = Addr[i];
130 MIB.addReg(MO.getReg());
132 MIB.addImm(MO.getImm());
134 MIB.addFrameIndex(MO.getIndex());
136 MIB.addReg(SrcReg, false, false, isKill);
137 NewMIs.push_back(MIB);
142 void IA64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
143 MachineBasicBlock::iterator MI,
144 unsigned DestReg, int FrameIdx,
145 const TargetRegisterClass *RC)const{
147 if (RC == IA64::FPRegisterClass) {
148 BuildMI(MBB, MI, get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx);
149 } else if (RC == IA64::GRRegisterClass) {
150 BuildMI(MBB, MI, get(IA64::LD8), DestReg).addFrameIndex(FrameIdx);
151 } else if (RC == IA64::PRRegisterClass) {
152 // first we load a byte from the stack into r2, our 'predicate hackery'
154 BuildMI(MBB, MI, get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx);
155 // then we compare it to zero. If it _is_ zero, compare-not-equal to
156 // r0 gives us 0, which is what we want, so that's nice.
157 BuildMI(MBB, MI, get(IA64::CMPNE), DestReg).addReg(IA64::r2).addReg(IA64::r0);
159 "sorry, I don't know how to load this sort of reg from the stack\n");
162 void IA64InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
163 SmallVectorImpl<MachineOperand> &Addr,
164 const TargetRegisterClass *RC,
165 SmallVectorImpl<MachineInstr*> &NewMIs) const {
167 if (RC == IA64::FPRegisterClass) {
169 } else if (RC == IA64::GRRegisterClass) {
171 } else if (RC == IA64::PRRegisterClass) {
175 "sorry, I don't know how to store this sort of reg\n");
178 MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
179 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
180 MachineOperand &MO = Addr[i];
182 MIB.addReg(MO.getReg());
184 MIB.addImm(MO.getImm());
186 MIB.addFrameIndex(MO.getIndex());
188 NewMIs.push_back(MIB);