1 //===- IA64InstrInfo.cpp - IA64 Instruction Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the IA64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "IA64InstrInfo.h"
16 #include "IA64InstrBuilder.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "IA64GenInstrInfo.inc"
21 IA64InstrInfo::IA64InstrInfo()
22 : TargetInstrInfo(IA64Insts, sizeof(IA64Insts)/sizeof(IA64Insts[0])),
27 bool IA64InstrInfo::isMoveInstr(const MachineInstr& MI,
29 unsigned& destReg) const {
30 MachineOpCode oc = MI.getOpcode();
31 if (oc == IA64::MOV || oc == IA64::FMOV) {
32 // TODO: this doesn't detect predicate moves
33 assert(MI.getNumOperands() >= 2 &&
34 /* MI.getOperand(0).isRegister() &&
35 MI.getOperand(1).isRegister() && */
36 "invalid register-register move instruction");
37 if( MI.getOperand(0).isRegister() &&
38 MI.getOperand(1).isRegister() ) {
39 // if both operands of the MOV/FMOV are registers, then
40 // yes, this is a move instruction
41 sourceReg = MI.getOperand(1).getReg();
42 destReg = MI.getOperand(0).getReg();
46 return false; // we don't consider e.g. %regN = MOV <FrameIndex #x> a
51 IA64InstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
52 MachineBasicBlock *FBB,
53 const std::vector<MachineOperand> &Cond)const {
54 // Can only insert uncond branches so far.
55 assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
56 BuildMI(&MBB, get(IA64::BRL_NOTCALL)).addMBB(TBB);