1 //===- IA64InstrInfo.td - Describe the IA64 Instruction Set -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the IA64 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 include "IA64InstrFormats.td"
18 //===----------------------------------------------------------------------===//
19 // IA-64 specific DAG Nodes.
22 def IA64getfd : SDNode<"IA64ISD::GETFD", SDTFPToIntOp, []>;
24 def SDT_IA64RetFlag : SDTypeProfile<0, 0, []>;
25 def retflag : SDNode<"IA64ISD::RET_FLAG", SDT_IA64RetFlag,
26 [SDNPHasChain, SDNPOptInFlag]>;
31 class isA { bit A=1; } // I or M unit
32 class isM { bit M=1; } // M unit
33 class isI { bit I=1; } // I unit
34 class isB { bit B=1; } // B unit
35 class isF { bit F=1; } // F unit
36 class isLX { bit LX=1; } // I/B
40 def u2imm : Operand<i8>;
41 def u6imm : Operand<i8>;
42 def s8imm : Operand<i8> {
43 let PrintMethod = "printS8ImmOperand";
45 def s14imm : Operand<i64> {
46 let PrintMethod = "printS14ImmOperand";
48 def s22imm : Operand<i64> {
49 let PrintMethod = "printS22ImmOperand";
51 def u64imm : Operand<i64> {
52 let PrintMethod = "printU64ImmOperand";
54 def s64imm : Operand<i64> {
55 let PrintMethod = "printS64ImmOperand";
58 let PrintMethod = "printGlobalOperand" in
59 def globaladdress : Operand<i64>;
61 // the asmprinter needs to know about calls
62 let PrintMethod = "printCallOperand" in
63 def calltarget : Operand<i64>;
65 /* new daggy action!!! */
67 def is32ones : PatLeaf<(i64 imm), [{
68 // is32ones predicate - True if the immediate is 0x00000000FFFFFFFF
69 // Used to create ZXT4s appropriately
70 uint64_t v = (uint64_t)N->getValue();
71 return (v == 0x00000000FFFFFFFFLL);
74 // isMIXable predicates - True if the immediate is
75 // 0xFF00FF00FF00FF00, 0x00FF00FF00FF00FF
76 // etc, through 0x00000000FFFFFFFF
77 // Used to test for the suitability of mix*
78 def isMIX1Lable: PatLeaf<(i64 imm), [{
79 return((uint64_t)N->getValue()==0xFF00FF00FF00FF00LL);
81 def isMIX1Rable: PatLeaf<(i64 imm), [{
82 return((uint64_t)N->getValue()==0x00FF00FF00FF00FFLL);
84 def isMIX2Lable: PatLeaf<(i64 imm), [{
85 return((uint64_t)N->getValue()==0xFFFF0000FFFF0000LL);
87 def isMIX2Rable: PatLeaf<(i64 imm), [{
88 return((uint64_t)N->getValue()==0x0000FFFF0000FFFFLL);
90 def isMIX4Lable: PatLeaf<(i64 imm), [{
91 return((uint64_t)N->getValue()==0xFFFFFFFF00000000LL);
93 def isMIX4Rable: PatLeaf<(i64 imm), [{
94 return((uint64_t)N->getValue()==0x00000000FFFFFFFFLL);
97 def isSHLADDimm: PatLeaf<(i64 imm), [{
98 // isSHLADDimm predicate - True if the immediate is exactly 1, 2, 3 or 4
100 // Used to create shladd instructions appropriately
101 int64_t v = (int64_t)N->getValue();
102 return (v >= 1 && v <= 4);
105 def immSExt14 : PatLeaf<(i64 imm), [{
106 // immSExt14 predicate - True if the immediate fits in a 14-bit sign extended
107 // field. Used by instructions like 'adds'.
108 int64_t v = (int64_t)N->getValue();
109 return (v <= 8191 && v >= -8192);
112 // imm64 predicate - True if the immediate fits in a 64-bit
113 // field - i.e., true. used to keep movl happy
114 def imm64 : PatLeaf<(i64 imm)>;
116 def ADD : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
117 "add $dst = $src1, $src2",
118 [(set GR:$dst, (add GR:$src1, GR:$src2))]>, isA;
120 def ADD1 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
121 "add $dst = $src1, $src2, 1",
122 [(set GR:$dst, (add (add GR:$src1, GR:$src2), 1))]>, isA;
124 def ADDS : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, s14imm:$imm),
125 "adds $dst = $imm, $src1",
126 [(set GR:$dst, (add GR:$src1, immSExt14:$imm))]>, isA;
128 def MOVL : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins s64imm:$imm),
130 [(set GR:$dst, imm64:$imm)]>, isLX;
132 def ADDL_GA : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, globaladdress:$imm),
133 "addl $dst = $imm, $src1",
137 def ADDL_EA : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, calltarget:$imm),
138 "addl $dst = $imm, $src1",
141 def SUB : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
142 "sub $dst = $src1, $src2",
143 [(set GR:$dst, (sub GR:$src1, GR:$src2))]>, isA;
145 def SUB1 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
146 "sub $dst = $src1, $src2, 1",
147 [(set GR:$dst, (add (sub GR: $src1, GR:$src2), -1))]>, isA;
149 let isTwoAddress = 1 in {
150 def TPCADDIMM22 : AForm<0x03, 0x0b,
151 (outs GR:$dst), (ins GR:$src1, s22imm:$imm, PR:$qp),
152 "($qp) add $dst = $imm, $dst">, isA;
153 def TPCADDS : AForm_DAG<0x03, 0x0b,
154 (outs GR:$dst), (ins GR:$src1, s14imm:$imm, PR:$qp),
155 "($qp) adds $dst = $imm, $dst",
157 def TPCMPIMM8NE : AForm<0x03, 0x0b,
158 (outs PR:$dst), (ins PR:$src1, s22imm:$imm, GR:$src2, PR:$qp),
159 "($qp) cmp.ne $dst , p0 = $imm, $src2">, isA;
162 // zero extend a bool (predicate reg) into an integer reg
163 def ZXTb : Pat<(zext PR:$src),
164 (TPCADDIMM22 (ADDS r0, 0), 1, PR:$src)>;
165 def AXTb : Pat<(anyext PR:$src),
166 (TPCADDIMM22 (ADDS r0, 0), 1, PR:$src)>;
168 // normal sign/zero-extends
169 def SXT1 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src), "sxt1 $dst = $src",
170 [(set GR:$dst, (sext_inreg GR:$src, i8))]>, isI;
171 def ZXT1 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src), "zxt1 $dst = $src",
172 [(set GR:$dst, (and GR:$src, 255))]>, isI;
173 def SXT2 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src), "sxt2 $dst = $src",
174 [(set GR:$dst, (sext_inreg GR:$src, i16))]>, isI;
175 def ZXT2 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src), "zxt2 $dst = $src",
176 [(set GR:$dst, (and GR:$src, 65535))]>, isI;
177 def SXT4 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src), "sxt4 $dst = $src",
178 [(set GR:$dst, (sext_inreg GR:$src, i32))]>, isI;
179 def ZXT4 : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src), "zxt4 $dst = $src",
180 [(set GR:$dst, (and GR:$src, is32ones))]>, isI;
182 // fixme: shrs vs shru?
183 def MIX1L : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
184 "mix1.l $dst = $src1, $src2",
185 [(set GR:$dst, (or (and GR:$src1, isMIX1Lable),
186 (and (srl GR:$src2, (i64 8)), isMIX1Lable)))]>, isI;
188 def MIX2L : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
189 "mix2.l $dst = $src1, $src2",
190 [(set GR:$dst, (or (and GR:$src1, isMIX2Lable),
191 (and (srl GR:$src2, (i64 16)), isMIX2Lable)))]>, isI;
193 def MIX4L : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
194 "mix4.l $dst = $src1, $src2",
195 [(set GR:$dst, (or (and GR:$src1, isMIX4Lable),
196 (and (srl GR:$src2, (i64 32)), isMIX4Lable)))]>, isI;
198 def MIX1R : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
199 "mix1.r $dst = $src1, $src2",
200 [(set GR:$dst, (or (and (shl GR:$src1, (i64 8)), isMIX1Rable),
201 (and GR:$src2, isMIX1Rable)))]>, isI;
203 def MIX2R : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
204 "mix2.r $dst = $src1, $src2",
205 [(set GR:$dst, (or (and (shl GR:$src1, (i64 16)), isMIX2Rable),
206 (and GR:$src2, isMIX2Rable)))]>, isI;
208 def MIX4R : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
209 "mix4.r $dst = $src1, $src2",
210 [(set GR:$dst, (or (and (shl GR:$src1, (i64 32)), isMIX4Rable),
211 (and GR:$src2, isMIX4Rable)))]>, isI;
213 def GETFSIGD : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins FP:$src),
214 "getf.sig $dst = $src",
217 def SETFSIGD : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins GR:$src),
218 "setf.sig $dst = $src",
221 def XMALD : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3),
222 "xma.l $dst = $src1, $src2, $src3",
224 def XMAHD : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3),
225 "xma.h $dst = $src1, $src2, $src3",
227 def XMAHUD : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3),
228 "xma.hu $dst = $src1, $src2, $src3",
231 // pseudocode for integer multiplication
232 def : Pat<(mul GR:$src1, GR:$src2),
233 (GETFSIGD (XMALD (SETFSIGD GR:$src1), (SETFSIGD GR:$src2), F0))>;
234 def : Pat<(mulhs GR:$src1, GR:$src2),
235 (GETFSIGD (XMAHD (SETFSIGD GR:$src1), (SETFSIGD GR:$src2), F0))>;
236 def : Pat<(mulhu GR:$src1, GR:$src2),
237 (GETFSIGD (XMAHUD (SETFSIGD GR:$src1), (SETFSIGD GR:$src2), F0))>;
239 // TODO: addp4 (addp4 dst = src, r0 is a 32-bit add)
242 // def ADDS : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, s14imm:$imm),
243 // "adds $dst = $imm, $src1">;
245 def AND : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
246 "and $dst = $src1, $src2",
247 [(set GR:$dst, (and GR:$src1, GR:$src2))]>, isA;
248 def ANDCM : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
249 "andcm $dst = $src1, $src2",
250 [(set GR:$dst, (and GR:$src1, (not GR:$src2)))]>, isA;
251 // TODO: and/andcm/or/xor/add/sub/shift immediate forms
252 def OR : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
253 "or $dst = $src1, $src2",
254 [(set GR:$dst, (or GR:$src1, GR:$src2))]>, isA;
256 def pOR : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2, PR:$qp),
257 "($qp) or $dst = $src1, $src2">, isA;
259 // the following are all a bit unfortunate: we throw away the complement
261 def CMPEQ : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
262 "cmp.eq $dst, p0 = $src1, $src2",
263 [(set PR:$dst, (seteq GR:$src1, GR:$src2))]>, isA;
264 def CMPGT : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
265 "cmp.gt $dst, p0 = $src1, $src2",
266 [(set PR:$dst, (setgt GR:$src1, GR:$src2))]>, isA;
267 def CMPGE : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
268 "cmp.ge $dst, p0 = $src1, $src2",
269 [(set PR:$dst, (setge GR:$src1, GR:$src2))]>, isA;
270 def CMPLT : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
271 "cmp.lt $dst, p0 = $src1, $src2",
272 [(set PR:$dst, (setlt GR:$src1, GR:$src2))]>, isA;
273 def CMPLE : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
274 "cmp.le $dst, p0 = $src1, $src2",
275 [(set PR:$dst, (setle GR:$src1, GR:$src2))]>, isA;
276 def CMPNE : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
277 "cmp.ne $dst, p0 = $src1, $src2",
278 [(set PR:$dst, (setne GR:$src1, GR:$src2))]>, isA;
279 def CMPLTU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
280 "cmp.ltu $dst, p0 = $src1, $src2",
281 [(set PR:$dst, (setult GR:$src1, GR:$src2))]>, isA;
282 def CMPGTU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
283 "cmp.gtu $dst, p0 = $src1, $src2",
284 [(set PR:$dst, (setugt GR:$src1, GR:$src2))]>, isA;
285 def CMPLEU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
286 "cmp.leu $dst, p0 = $src1, $src2",
287 [(set PR:$dst, (setule GR:$src1, GR:$src2))]>, isA;
288 def CMPGEU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2),
289 "cmp.geu $dst, p0 = $src1, $src2",
290 [(set PR:$dst, (setuge GR:$src1, GR:$src2))]>, isA;
292 // and we do the whole thing again for FP compares!
293 def FCMPEQ : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
294 "fcmp.eq $dst, p0 = $src1, $src2",
295 [(set PR:$dst, (seteq FP:$src1, FP:$src2))]>, isF;
296 def FCMPGT : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
297 "fcmp.gt $dst, p0 = $src1, $src2",
298 [(set PR:$dst, (setgt FP:$src1, FP:$src2))]>, isF;
299 def FCMPGE : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
300 "fcmp.ge $dst, p0 = $src1, $src2",
301 [(set PR:$dst, (setge FP:$src1, FP:$src2))]>, isF;
302 def FCMPLT : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
303 "fcmp.lt $dst, p0 = $src1, $src2",
304 [(set PR:$dst, (setlt FP:$src1, FP:$src2))]>, isF;
305 def FCMPLE : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
306 "fcmp.le $dst, p0 = $src1, $src2",
307 [(set PR:$dst, (setle FP:$src1, FP:$src2))]>, isF;
308 def FCMPNE : AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
309 "fcmp.neq $dst, p0 = $src1, $src2",
310 [(set PR:$dst, (setne FP:$src1, FP:$src2))]>, isF;
311 def FCMPLTU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
312 "fcmp.lt $dst, p0 = $src1, $src2",
313 [(set PR:$dst, (setult FP:$src1, FP:$src2))]>, isF;
314 def FCMPGTU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
315 "fcmp.gt $dst, p0 = $src1, $src2",
316 [(set PR:$dst, (setugt FP:$src1, FP:$src2))]>, isF;
317 def FCMPLEU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
318 "fcmp.le $dst, p0 = $src1, $src2",
319 [(set PR:$dst, (setule FP:$src1, FP:$src2))]>, isF;
320 def FCMPGEU: AForm_DAG<0x03, 0x0b, (outs PR:$dst), (ins FP:$src1, FP:$src2),
321 "fcmp.ge $dst, p0 = $src1, $src2",
322 [(set PR:$dst, (setuge FP:$src1, FP:$src2))]>, isF;
324 def PCMPEQUNCR0R0 : AForm<0x03, 0x0b, (outs PR:$dst), (ins PR:$qp),
325 "($qp) cmp.eq.unc $dst, p0 = r0, r0">, isA;
327 def : Pat<(trunc GR:$src), // truncate i64 to i1
328 (CMPNE GR:$src, r0)>; // $src!=0? If so, PR:$dst=true
330 let isTwoAddress=1 in {
331 def TPCMPEQR0R0 : AForm<0x03, 0x0b, (outs PR:$dst), (ins PR:$bogus, PR:$qp),
332 "($qp) cmp.eq $dst, p0 = r0, r0">, isA;
333 def TPCMPNER0R0 : AForm<0x03, 0x0b, (outs PR:$dst), (ins PR:$bogus, PR:$qp),
334 "($qp) cmp.ne $dst, p0 = r0, r0">, isA;
337 /* our pseudocode for OR on predicates is:
340 (pA) cmp.eq.unc pC,p0 = r0,r0 // pC = pA
342 (pB) cmp.eq pC,p0 = r0,r0 // if (pB) pC = 1 */
344 def bOR : Pat<(or PR:$src1, PR:$src2),
345 (TPCMPEQR0R0 (PCMPEQUNCR0R0 PR:$src1), PR:$src2)>;
347 /* our pseudocode for AND on predicates is:
349 (pA) cmp.eq.unc pC,p0 = r0,r0 // pC = pA
350 cmp.eq pTemp,p0 = r0,r0 // pTemp = NOT pB
352 (pB) cmp.ne pTemp,p0 = r0,r0
354 (pTemp)cmp.ne pC,p0 = r0,r0 // if (NOT pB) pC = 0 */
356 def bAND : Pat<(and PR:$src1, PR:$src2),
357 ( TPCMPNER0R0 (PCMPEQUNCR0R0 PR:$src1),
358 (TPCMPNER0R0 (CMPEQ r0, r0), PR:$src2) )>;
360 /* one possible routine for XOR on predicates is:
362 // Compute px = py ^ pz
363 // using sum of products: px = (py & !pz) | (pz & !py)
364 // Uses 5 instructions in 3 cycles.
366 (pz) cmp.eq.unc px = r0, r0 // px = pz
367 (py) cmp.eq.unc pt = r0, r0 // pt = py
370 (pt) cmp.ne.and px = r0, r0 // px = px & !pt (px = pz & !pt)
371 (pz) cmp.ne.and pt = r0, r0 // pt = pt & !pz
375 (pt) cmp.eq.or px = r0, r0 // px = px | pt
377 *** Another, which we use here, requires one scratch GR. it is:
379 mov rt = 0 // initialize rt off critical path
383 (pz) cmp.eq.unc px = r0, r0 // px = pz
384 (pz) mov rt = 1 // rt = pz
387 (py) cmp.ne px = 1, rt // if (py) px = !pz
389 .. these routines kindly provided by Jim Hull
392 def bXOR : Pat<(xor PR:$src1, PR:$src2),
393 (TPCMPIMM8NE (PCMPEQUNCR0R0 PR:$src2), 1,
394 (TPCADDS (ADDS r0, 0), 1, PR:$src2),
397 def XOR : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
398 "xor $dst = $src1, $src2",
399 [(set GR:$dst, (xor GR:$src1, GR:$src2))]>, isA;
401 def SHLADD: AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1,s64imm:$imm,GR:$src2),
402 "shladd $dst = $src1, $imm, $src2",
403 [(set GR:$dst, (add GR:$src2, (shl GR:$src1, isSHLADDimm:$imm)))]>, isA;
405 def SHL : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
406 "shl $dst = $src1, $src2",
407 [(set GR:$dst, (shl GR:$src1, GR:$src2))]>, isI;
409 def SHRU : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
410 "shr.u $dst = $src1, $src2",
411 [(set GR:$dst, (srl GR:$src1, GR:$src2))]>, isI;
413 def SHRS : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, GR:$src2),
414 "shr $dst = $src1, $src2",
415 [(set GR:$dst, (sra GR:$src1, GR:$src2))]>, isI;
417 def MOV : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src), "mov $dst = $src">, isA;
418 def FMOV : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
419 "mov $dst = $src">, isF; // XXX: there _is_ no fmov
420 def PMOV : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src, PR:$qp),
421 "($qp) mov $dst = $src">, isA;
423 def SPILL_ALL_PREDICATES_TO_GR : AForm<0x03, 0x0b, (outs GR:$dst), (ins),
424 "mov $dst = pr">, isI;
425 def FILL_ALL_PREDICATES_FROM_GR : AForm<0x03, 0x0b, (outs), (ins GR:$src),
426 "mov pr = $src">, isI;
428 let isTwoAddress = 1 in {
429 def CMOV : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src2, GR:$src, PR:$qp),
430 "($qp) mov $dst = $src">, isA;
433 def PFMOV : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src, PR:$qp),
434 "($qp) mov $dst = $src">, isF;
436 let isTwoAddress = 1 in {
437 def CFMOV : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src2, FP:$src, PR:$qp),
438 "($qp) mov $dst = $src">, isF;
441 def SELECTINT : Pat<(select PR:$which, GR:$src1, GR:$src2),
442 (CMOV (MOV GR:$src2), GR:$src1, PR:$which)>; // note order!
443 def SELECTFP : Pat<(select PR:$which, FP:$src1, FP:$src2),
444 (CFMOV (FMOV FP:$src2), FP:$src1, PR:$which)>; // note order!
445 // TODO: can do this faster, w/o using any integer regs (see pattern isel)
446 def SELECTBOOL : Pat<(select PR:$which, PR:$src1, PR:$src2), // note order!
448 (MOV (TPCADDIMM22 (ADDS r0, 0), 1, PR:$src2)),
449 (TPCADDIMM22 (ADDS r0, 0), 1, PR:$src1), PR:$which), r0)>;
451 // load constants of various sizes // FIXME: prettyprint -ve constants
452 def : Pat<(i64 immSExt14:$imm), (ADDS r0, immSExt14:$imm)>;
453 def : Pat<(i1 -1), (CMPEQ r0, r0)>; // TODO: this should just be a ref to p0
454 def : Pat<(i1 0), (CMPNE r0, r0)>; // TODO: any instruction actually *using*
455 // this predicate should be killed!
457 // TODO: support postincrement (reg, imm9) loads+stores - this needs more
460 let isImplicitDef = 1 in {
461 def IDEF : PseudoInstIA64<(outs variable_ops), (ins), "// IDEF">;
463 def IDEF_GR_D : PseudoInstIA64_DAG<(outs GR:$reg), (ins), "// $reg = IDEF",
464 [(set GR:$reg, (undef))]>;
465 def IDEF_FP_D : PseudoInstIA64_DAG<(outs FP:$reg), (ins), "// $reg = IDEF",
466 [(set FP:$reg, (undef))]>;
467 def IDEF_PR_D : PseudoInstIA64_DAG<(outs PR:$reg), (ins), "// $reg = IDEF",
468 [(set PR:$reg, (undef))]>;
471 def IUSE : PseudoInstIA64<(outs), (ins variable_ops), "// IUSE">;
472 def ADJUSTCALLSTACKUP : PseudoInstIA64<(outs), (ins variable_ops),
473 "// ADJUSTCALLSTACKUP">;
474 def ADJUSTCALLSTACKDOWN : PseudoInstIA64<(outs), (ins variable_ops),
475 "// ADJUSTCALLSTACKDOWN">;
476 def PSEUDO_ALLOC : PseudoInstIA64<(outs), (ins GR:$foo), "// PSEUDO_ALLOC">;
478 def ALLOC : AForm<0x03, 0x0b,
479 (outs GR:$dst), (ins i8imm:$inputs, i8imm:$locals, i8imm:$outputs, i8imm:$rotating),
480 "alloc $dst = ar.pfs,$inputs,$locals,$outputs,$rotating">, isM;
482 let isTwoAddress = 1 in {
483 def TCMPNE : AForm<0x03, 0x0b,
484 (outs PR:$dst), (ins PR:$src2, GR:$src3, GR:$src4),
485 "cmp.ne $dst, p0 = $src3, $src4">, isA;
487 def TPCMPEQOR : AForm<0x03, 0x0b,
488 (outs PR:$dst), (ins PR:$src2, GR:$src3, GR:$src4, PR:$qp),
489 "($qp) cmp.eq.or $dst, p0 = $src3, $src4">, isA;
491 def TPCMPNE : AForm<0x03, 0x0b,
492 (outs PR:$dst), (ins PR:$src2, GR:$src3, GR:$src4, PR:$qp),
493 "($qp) cmp.ne $dst, p0 = $src3, $src4">, isA;
495 def TPCMPEQ : AForm<0x03, 0x0b,
496 (outs PR:$dst), (ins PR:$src2, GR:$src3, GR:$src4, PR:$qp),
497 "($qp) cmp.eq $dst, p0 = $src3, $src4">, isA;
500 def MOVSIMM14 : AForm<0x03, 0x0b, (outs GR:$dst), (ins s14imm:$imm),
501 "mov $dst = $imm">, isA;
502 def MOVSIMM22 : AForm<0x03, 0x0b, (outs GR:$dst), (ins s22imm:$imm),
503 "mov $dst = $imm">, isA;
504 def MOVLIMM64 : AForm<0x03, 0x0b, (outs GR:$dst), (ins s64imm:$imm),
505 "movl $dst = $imm">, isLX;
507 def SHLI : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, u6imm:$imm),
508 "shl $dst = $src1, $imm">, isI;
509 def SHRUI : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, u6imm:$imm),
510 "shr.u $dst = $src1, $imm">, isI;
511 def SHRSI : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, u6imm:$imm),
512 "shr $dst = $src1, $imm">, isI;
514 def EXTRU : AForm<0x03, 0x0b,
515 (outs GR:$dst), (ins GR:$src1, u6imm:$imm1, u6imm:$imm2),
516 "extr.u $dst = $src1, $imm1, $imm2">, isI;
518 def DEPZ : AForm<0x03, 0x0b,
519 (outs GR:$dst), (ins GR:$src1, u6imm:$imm1, u6imm:$imm2),
520 "dep.z $dst = $src1, $imm1, $imm2">, isI;
522 def PCMPEQOR : AForm<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2, PR:$qp),
523 "($qp) cmp.eq.or $dst, p0 = $src1, $src2">, isA;
524 def PCMPEQUNC : AForm<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2, PR:$qp),
525 "($qp) cmp.eq.unc $dst, p0 = $src1, $src2">, isA;
526 def PCMPNE : AForm<0x03, 0x0b, (outs PR:$dst), (ins GR:$src1, GR:$src2, PR:$qp),
527 "($qp) cmp.ne $dst, p0 = $src1, $src2">, isA;
530 def BCMPEQ : AForm<0x03, 0x0b, (outs PR:$dst1, PR:$dst2), (ins GR:$src1, GR:$src2),
531 "cmp.eq $dst1, dst2 = $src1, $src2">, isA;
533 def ADDIMM14 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, s14imm:$imm),
534 "adds $dst = $imm, $src1">, isA;
536 def ADDIMM22 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, s22imm:$imm),
537 "add $dst = $imm, $src1">, isA;
538 def CADDIMM22 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, s22imm:$imm, PR:$qp),
539 "($qp) add $dst = $imm, $src1">, isA;
541 def SUBIMM8 : AForm<0x03, 0x0b, (outs GR:$dst), (ins s8imm:$imm, GR:$src2),
542 "sub $dst = $imm, $src2">, isA;
545 def ST1 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, GR:$value),
546 "st1 [$dstPtr] = $value">, isM;
547 def ST2 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, GR:$value),
548 "st2 [$dstPtr] = $value">, isM;
549 def ST4 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, GR:$value),
550 "st4 [$dstPtr] = $value">, isM;
551 def ST8 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, GR:$value),
552 "st8 [$dstPtr] = $value">, isM;
553 def STF4 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, FP:$value),
554 "stfs [$dstPtr] = $value">, isM;
555 def STF8 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, FP:$value),
556 "stfd [$dstPtr] = $value">, isM;
557 def STF_SPILL : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, FP:$value),
558 "stf.spill [$dstPtr] = $value">, isM;
562 def LD1 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$srcPtr),
563 "ld1 $dst = [$srcPtr]">, isM;
564 def LD2 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$srcPtr),
565 "ld2 $dst = [$srcPtr]">, isM;
566 def LD4 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$srcPtr),
567 "ld4 $dst = [$srcPtr]">, isM;
568 def LD8 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$srcPtr),
569 "ld8 $dst = [$srcPtr]">, isM;
570 def LDF4 : AForm<0x03, 0x0b, (outs FP:$dst), (ins GR:$srcPtr),
571 "ldfs $dst = [$srcPtr]">, isM;
572 def LDF8 : AForm<0x03, 0x0b, (outs FP:$dst), (ins GR:$srcPtr),
573 "ldfd $dst = [$srcPtr]">, isM;
574 def LDF_FILL : AForm<0x03, 0x0b, (outs FP:$dst), (ins GR:$srcPtr),
575 "ldf.fill $dst = [$srcPtr]">, isM;
578 def POPCNT : AForm_DAG<0x03, 0x0b, (outs GR:$dst), (ins GR:$src),
579 "popcnt $dst = $src",
580 [(set GR:$dst, (ctpop GR:$src))]>, isI;
582 // some FP stuff: // TODO: single-precision stuff?
583 def FADD : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2),
584 "fadd $dst = $src1, $src2",
585 [(set FP:$dst, (fadd FP:$src1, FP:$src2))]>, isF;
586 def FADDS: AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2),
587 "fadd.s $dst = $src1, $src2">, isF;
588 def FSUB : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2),
589 "fsub $dst = $src1, $src2",
590 [(set FP:$dst, (fsub FP:$src1, FP:$src2))]>, isF;
591 def FMPY : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2),
592 "fmpy $dst = $src1, $src2",
593 [(set FP:$dst, (fmul FP:$src1, FP:$src2))]>, isF;
594 def FMA : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3),
595 "fma $dst = $src1, $src2, $src3",
596 [(set FP:$dst, (fadd (fmul FP:$src1, FP:$src2), FP:$src3))]>, isF;
597 def FMS : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3),
598 "fms $dst = $src1, $src2, $src3",
599 [(set FP:$dst, (fsub (fmul FP:$src1, FP:$src2), FP:$src3))]>, isF;
600 def FNMA : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3),
601 "fnma $dst = $src1, $src2, $src3",
602 [(set FP:$dst, (fneg (fadd (fmul FP:$src1, FP:$src2), FP:$src3)))]>, isF;
603 def FABS : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
605 [(set FP:$dst, (fabs FP:$src))]>, isF;
606 def FNEG : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
608 [(set FP:$dst, (fneg FP:$src))]>, isF;
609 def FNEGABS : AForm_DAG<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
610 "fnegabs $dst = $src",
611 [(set FP:$dst, (fneg (fabs FP:$src)))]>, isF;
613 let isTwoAddress=1 in {
614 def TCFMAS1 : AForm<0x03, 0x0b,
615 (outs FP:$dst), (ins FP:$bogussrc, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
616 "($qp) fma.s1 $dst = $src1, $src2, $src3">, isF;
617 def TCFMADS0 : AForm<0x03, 0x0b,
618 (outs FP:$dst), (ins FP:$bogussrc, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
619 "($qp) fma.d.s0 $dst = $src1, $src2, $src3">, isF;
622 def CFMAS1 : AForm<0x03, 0x0b,
623 (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3, PR:$qp),
624 "($qp) fma.s1 $dst = $src1, $src2, $src3">, isF;
625 def CFNMAS1 : AForm<0x03, 0x0b,
626 (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3, PR:$qp),
627 "($qp) fnma.s1 $dst = $src1, $src2, $src3">, isF;
629 def CFMADS1 : AForm<0x03, 0x0b,
630 (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3, PR:$qp),
631 "($qp) fma.d.s1 $dst = $src1, $src2, $src3">, isF;
632 def CFMADS0 : AForm<0x03, 0x0b,
633 (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3, PR:$qp),
634 "($qp) fma.d.s0 $dst = $src1, $src2, $src3">, isF;
635 def CFNMADS1 : AForm<0x03, 0x0b,
636 (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3, PR:$qp),
637 "($qp) fnma.d.s1 $dst = $src1, $src2, $src3">, isF;
639 def FRCPAS0 : AForm<0x03, 0x0b, (outs FP:$dstFR, PR:$dstPR), (ins FP:$src1, FP:$src2),
640 "frcpa.s0 $dstFR, $dstPR = $src1, $src2">, isF;
641 def FRCPAS1 : AForm<0x03, 0x0b, (outs FP:$dstFR, PR:$dstPR), (ins FP:$src1, FP:$src2),
642 "frcpa.s1 $dstFR, $dstPR = $src1, $src2">, isF;
644 def XMAL : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src1, FP:$src2, FP:$src3),
645 "xma.l $dst = $src1, $src2, $src3">, isF;
647 def FCVTXF : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
648 "fcvt.xf $dst = $src">, isF;
649 def FCVTXUF : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
650 "fcvt.xuf $dst = $src">, isF;
651 def FCVTXUFS1 : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
652 "fcvt.xuf.s1 $dst = $src">, isF;
653 def FCVTFX : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
654 "fcvt.fx $dst = $src">, isF;
655 def FCVTFXU : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
656 "fcvt.fxu $dst = $src">, isF;
658 def FCVTFXTRUNC : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
659 "fcvt.fx.trunc $dst = $src">, isF;
660 def FCVTFXUTRUNC : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
661 "fcvt.fxu.trunc $dst = $src">, isF;
663 def FCVTFXTRUNCS1 : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
664 "fcvt.fx.trunc.s1 $dst = $src">, isF;
665 def FCVTFXUTRUNCS1 : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
666 "fcvt.fxu.trunc.s1 $dst = $src">, isF;
668 def FNORMD : AForm<0x03, 0x0b, (outs FP:$dst), (ins FP:$src),
669 "fnorm.d $dst = $src">, isF;
671 def GETFD : AForm<0x03, 0x0b, (outs GR:$dst), (ins FP:$src),
672 "getf.d $dst = $src">, isM;
673 def SETFD : AForm<0x03, 0x0b, (outs FP:$dst), (ins GR:$src),
674 "setf.d $dst = $src">, isM;
676 def GETFSIG : AForm<0x03, 0x0b, (outs GR:$dst), (ins FP:$src),
677 "getf.sig $dst = $src">, isM;
678 def SETFSIG : AForm<0x03, 0x0b, (outs FP:$dst), (ins GR:$src),
679 "setf.sig $dst = $src">, isM;
681 // these four FP<->int conversion patterns need checking/cleaning
682 def SINT_TO_FP : Pat<(sint_to_fp GR:$src),
683 (FNORMD (FCVTXF (SETFSIG GR:$src)))>;
684 def UINT_TO_FP : Pat<(uint_to_fp GR:$src),
685 (FNORMD (FCVTXUF (SETFSIG GR:$src)))>;
686 def FP_TO_SINT : Pat<(i64 (fp_to_sint FP:$src)),
687 (GETFSIG (FCVTFXTRUNC FP:$src))>;
688 def FP_TO_UINT : Pat<(i64 (fp_to_uint FP:$src)),
689 (GETFSIG (FCVTFXUTRUNC FP:$src))>;
692 let isTerminator = 1, isBranch = 1 in {
693 def BRL_NOTCALL : RawForm<0x03, 0xb0, (outs), (ins i64imm:$dst),
694 "(p0) brl.cond.sptk $dst">, isB;
695 def BRLCOND_NOTCALL : RawForm<0x03, 0xb0, (outs), (ins PR:$qp, i64imm:$dst),
696 "($qp) brl.cond.sptk $dst">, isB;
697 def BRCOND_NOTCALL : RawForm<0x03, 0xb0, (outs), (ins PR:$qp, GR:$dst),
698 "($qp) br.cond.sptk $dst">, isB;
701 let isCall = 1, /* isTerminator = 1, isBranch = 1, */
702 Uses = [out0,out1,out2,out3,out4,out5,out6,out7],
703 // all calls clobber non-callee-saved registers, and for now, they are these:
704 Defs = [r2,r3,r8,r9,r10,r11,r14,r15,r16,r17,r18,r19,r20,r21,r22,r23,r24,
705 r25,r26,r27,r28,r29,r30,r31,
706 p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,
707 F6,F7,F8,F9,F10,F11,F12,F13,F14,F15,
708 F32,F33,F34,F35,F36,F37,F38,F39,F40,F41,F42,F43,F44,F45,F46,F47,F48,F49,
709 F50,F51,F52,F53,F54,F55,F56,
710 F57,F58,F59,F60,F61,F62,F63,F64,F65,F66,F67,F68,F69,F70,F71,F72,F73,F74,
711 F75,F76,F77,F78,F79,F80,F81,
712 F82,F83,F84,F85,F86,F87,F88,F89,F90,F91,F92,F93,F94,F95,F96,F97,F98,F99,
713 F100,F101,F102,F103,F104,F105,
714 F106,F107,F108,F109,F110,F111,F112,F113,F114,F115,F116,F117,F118,F119,
715 F120,F121,F122,F123,F124,F125,F126,F127,
716 out0,out1,out2,out3,out4,out5,out6,out7] in {
718 def BRCALL: RawForm<0x03, 0xb0, (outs), (ins calltarget:$dst),
719 "br.call.sptk rp = $dst">, isB; // FIXME: teach llvm about branch regs?
722 // calls a globaladdress
723 def BRCALL_IPREL_GA : RawForm<0x03, 0xb0, (outs), (ins calltarget:$dst),
724 "br.call.sptk rp = $dst">, isB; // FIXME: teach llvm about branch regs?
725 // calls an externalsymbol
726 def BRCALL_IPREL_ES : RawForm<0x03, 0xb0, (outs), (ins calltarget:$dst),
727 "br.call.sptk rp = $dst">, isB; // FIXME: teach llvm about branch regs?
728 // calls through a function descriptor
729 def BRCALL_INDIRECT : RawForm<0x03, 0xb0, (outs), (ins GR:$branchreg),
730 "br.call.sptk rp = $branchreg">, isB; // FIXME: teach llvm about branch regs?
731 def BRLCOND_CALL : RawForm<0x03, 0xb0, (outs), (ins PR:$qp, i64imm:$dst),
732 "($qp) brl.cond.call.sptk $dst">, isB;
733 def BRCOND_CALL : RawForm<0x03, 0xb0, (outs), (ins PR:$qp, GR:$dst),
734 "($qp) br.cond.call.sptk $dst">, isB;
738 let isTerminator = 1, isReturn = 1 in
739 def RET : AForm_DAG<0x03, 0x0b, (outs), (ins),
740 "br.ret.sptk.many rp",
741 [(retflag)]>, isB; // return
742 def : Pat<(ret), (RET)>;
744 // the evil stop bit of despair
745 def STOP : PseudoInstIA64<(outs), (ins variable_ops), ";;">;