1 //===- IA64InstrInfo.td - Describe the IA64 Instruction Set -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the IA64 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 include "IA64InstrFormats.td"
18 def u6imm : Operand<i8>;
19 def s8imm : Operand<i8> {
20 let PrintMethod = "printS8ImmOperand";
22 def s14imm : Operand<i16> {
23 let PrintMethod = "printS14ImmOperand";
25 def s22imm : Operand<i32> {
26 let PrintMethod = "printS22ImmOperand";
28 def u64imm : Operand<i64> {
29 let PrintMethod = "printU64ImmOperand";
32 // the asmprinter needs to know about calls
33 let PrintMethod = "printCallOperand" in
34 def calltarget : Operand<i64>;
36 def PHI : PseudoInstIA64<(ops), "PHI">;
37 def IDEF : PseudoInstIA64<(ops), "// IDEF">;
38 def IUSE : PseudoInstIA64<(ops), "// IUSE">;
39 def WTF : PseudoInstIA64<(ops), "que??">;
40 def ADJUSTCALLSTACKUP : PseudoInstIA64<(ops), "// ADJUSTCALLSTACKUP">;
41 def ADJUSTCALLSTACKDOWN : PseudoInstIA64<(ops), "// ADJUSTCALLSTACKDOWN">;
42 def PSEUDO_ALLOC : PseudoInstIA64<(ops), "// PSEUDO_ALLOC">;
44 def ALLOC : AForm<0x03, 0x0b,
45 (ops GR:$dst, i8imm:$inputs, i8imm:$locals, i8imm:$outputs, i8imm:$rotating),
46 "alloc $dst = ar.pfs,$inputs,$locals,$outputs,$rotating;;">;
48 def MOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "mov $dst = $src;;">;
49 def PMOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src, PR:$qp),
50 "($qp) mov $dst = $src;;">;
52 def SPILL_ALL_PREDICATES_TO_GR : AForm<0x03, 0x0b, (ops GR:$dst),
54 def FILL_ALL_PREDICATES_FROM_GR : AForm<0x03, 0x0b, (ops GR:$src),
57 let isTwoAddress = 1 in {
58 def CMOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src2, GR:$src, PR:$qp),
59 "($qp) mov $dst = $src;;">;
62 def PFMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src, PR:$qp),
63 "($qp) mov $dst = $src;;">;
65 let isTwoAddress = 1 in {
66 def CFMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src2, FP:$src, PR:$qp),
67 "($qp) mov $dst = $src;;">;
70 let isTwoAddress = 1 in {
71 def TCMPNE : AForm<0x03, 0x0b,
72 (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4),
73 "cmp.ne $dst, p0 = $src3, $src4;;">;
75 def TPCMPEQOR : AForm<0x03, 0x0b,
76 (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
77 "($qp) cmp.eq.or $dst, p0 = $src3, $src4;;">;
79 def TPCMPNE : AForm<0x03, 0x0b,
80 (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
81 "($qp) cmp.ne $dst, p0 = $src3, $src4;;">;
83 def TPCMPEQ : AForm<0x03, 0x0b,
84 (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
85 "($qp) cmp.eq $dst, p0 = $src3, $src4;;">;
88 def MOVSIMM14 : AForm<0x03, 0x0b, (ops GR:$dst, s14imm:$imm),
90 def MOVSIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, s22imm:$imm),
92 def MOVLIMM64 : AForm<0x03, 0x0b, (ops GR:$dst, u64imm:$imm),
93 "movl $dst = $imm;;">;
95 def AND : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
96 "and $dst = $src1, $src2;;">;
97 def OR : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
98 "or $dst = $src1, $src2;;">;
99 def XOR : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
100 "xor $dst = $src1, $src2;;">;
101 def SHL : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
102 "shl $dst = $src1, $src2;;">;
103 def SHLI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
104 "shl $dst = $src1, $imm;;">;
105 def SHRU : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
106 "shr.u $dst = $src1, $src2;;">;
107 def SHRUI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
108 "shr.u $dst = $src1, $imm;;">;
109 def SHRS : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
110 "shr $dst = $src1, $src2;;">;
111 def SHRSI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
112 "shr $dst = $src1, $imm;;">;
114 def EXTRU : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2),
115 "extr.u $dst = $src1, $imm1, $imm2;;">;
117 def DEPZ : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2), "dep.z $dst = $src1, $imm1, $imm2;;">;
119 def SXT1 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt1 $dst = $src;;">;
120 def ZXT1 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt1 $dst = $src;;">;
121 def SXT2 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt2 $dst = $src;;">;
122 def ZXT2 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt2 $dst = $src;;">;
123 def SXT4 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt4 $dst = $src;;">;
124 def ZXT4 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt4 $dst = $src;;">;
126 // the following are all a bit unfortunate: we throw away the complement
128 def CMPEQ : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
129 "cmp.eq $dst, p0 = $src1, $src2;;">;
130 def CMPGT : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
131 "cmp.gt $dst, p0 = $src1, $src2;;">;
132 def CMPGE : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
133 "cmp.ge $dst, p0 = $src1, $src2;;">;
134 def CMPLT : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
135 "cmp.lt $dst, p0 = $src1, $src2;;">;
136 def CMPLE : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
137 "cmp.le $dst, p0 = $src1, $src2;;">;
138 def CMPNE : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
139 "cmp.ne $dst, p0 = $src1, $src2;;">;
140 def CMPLTU : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
141 "cmp.ltu $dst, p0 = $src1, $src2;;">;
142 def CMPGTU : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
143 "cmp.gtu $dst, p0 = $src1, $src2;;">;
144 def CMPLEU : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
145 "cmp.leu $dst, p0 = $src1, $src2;;">;
146 def CMPGEU : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
147 "cmp.geu $dst, p0 = $src1, $src2;;">;
149 // and we do the whole thing again for FP compares!
150 def FCMPEQ : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
151 "fcmp.eq $dst, p0 = $src1, $src2;;">;
152 def FCMPGT : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
153 "fcmp.gt $dst, p0 = $src1, $src2;;">;
154 def FCMPGE : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
155 "fcmp.ge $dst, p0 = $src1, $src2;;">;
156 def FCMPLT : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
157 "fcmp.lt $dst, p0 = $src1, $src2;;">;
158 def FCMPLE : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
159 "fcmp.le $dst, p0 = $src1, $src2;;">;
160 def FCMPNE : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
161 "fcmp.neq $dst, p0 = $src1, $src2;;">;
162 def FCMPLTU : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
163 "fcmp.ltu $dst, p0 = $src1, $src2;;">;
164 def FCMPGTU : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
165 "fcmp.gtu $dst, p0 = $src1, $src2;;">;
166 def FCMPLEU : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
167 "fcmp.leu $dst, p0 = $src1, $src2;;">;
168 def FCMPGEU : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
169 "fcmp.geu $dst, p0 = $src1, $src2;;">;
171 def PCMPEQOR : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
172 "($qp) cmp.eq.or $dst, p0 = $src1, $src2;;">;
173 def PCMPEQUNC : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
174 "($qp) cmp.eq.unc $dst, p0 = $src1, $src2;;">;
175 def PCMPNE : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
176 "($qp) cmp.ne $dst, p0 = $src1, $src2;;">;
179 def BCMPEQ : AForm<0x03, 0x0b, (ops PR:$dst1, PR:$dst2, GR:$src1, GR:$src2),
180 "cmp.eq $dst1, dst2 = $src1, $src2;;">;
182 def ADD : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
183 "add $dst = $src1, $src2;;">;
184 def ADDIMM14 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
185 "adds $dst = $imm, $src1;;">;
187 def ADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm),
188 "add $dst = $imm, $src1;;">;
189 def CADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
190 "($qp) add $dst = $imm, $src1;;">;
192 let isTwoAddress = 1 in {
193 def TPCADDIMM22 : AForm<0x03, 0x0b,
194 (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
195 "($qp) add $dst = $imm, $dst;;">;
196 def TPCMPIMM8NE : AForm<0x03, 0x0b,
197 (ops PR:$dst, PR:$src1, s22imm:$imm, GR:$src2, PR:$qp),
198 "($qp) cmp.ne $dst , p0 = $imm, $src2;;">;
201 def SUB : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
202 "sub $dst = $src1, $src2;;">;
203 def SUBIMM8 : AForm<0x03, 0x0b, (ops GR:$dst, s8imm:$imm, GR:$src2),
204 "sub $dst = $imm, $src2;;">;
206 def ST1 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
207 "st1 [$dstPtr] = $value;;">;
208 def ST2 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
209 "st2 [$dstPtr] = $value;;">;
210 def ST4 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
211 "st4 [$dstPtr] = $value;;">;
212 def ST8 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
213 "st8 [$dstPtr] = $value;;">;
215 def LD1 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
216 "ld1 $dst = [$srcPtr];;">;
217 def LD2 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
218 "ld2 $dst = [$srcPtr];;">;
219 def LD4 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
220 "ld4 $dst = [$srcPtr];;">;
221 def LD8 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
222 "ld8 $dst = [$srcPtr];;">;
225 def FADD : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
226 "fadd $dst = $src1, $src2;;">;
227 def FADDS: AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
228 "fadd.s $dst = $src1, $src2;;">;
229 def FSUB : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
230 "fsub $dst = $src1, $src2;;">;
231 def FMPY : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
232 "fmpy $dst = $src1, $src2;;">;
233 def FMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
234 "mov $dst = $src;;">; // XXX: there _is_ no fmov
235 def FMA : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
236 "fma $dst = $src1, $src2, $src3;;">;
237 def FMS : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
238 "fms $dst = $src1, $src2, $src3;;">;
239 def FNMA : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
240 "fnma $dst = $src1, $src2, $src3;;">;
241 def FABS : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
242 "fabs $dst = $src;;">;
243 def FNEG : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
244 "fneg $dst = $src;;">;
245 def FNEGABS : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
246 "fnegabs $dst = $src;;">;
248 def CFMAS1 : AForm<0x03, 0x0b,
249 (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
250 "($qp) fma.s1 $dst = $src1, $src2, $src3;;">;
251 def CFNMAS1 : AForm<0x03, 0x0b,
252 (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
253 "($qp) fnma.s1 $dst = $src1, $src2, $src3;;">;
255 def FRCPAS1 : AForm<0x03, 0x0b, (ops FP:$dstFR, PR:$dstPR, FP:$src1, FP:$src2),
256 "frcpa.s1 $dstFR, $dstPR = $src1, $src2;;">;
258 def XMAL : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
259 "xma.l $dst = $src1, $src2, $src3;;">;
261 def FCVTXF : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
262 "fcvt.xf $dst = $src;;">;
263 def FCVTXUF : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
264 "fcvt.xuf $dst = $src;;">;
265 def FCVTXUFS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
266 "fcvt.xuf.s1 $dst = $src;;">;
267 def FCVTFX : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
268 "fcvt.fx $dst = $src;;">;
269 def FCVTFXU : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
270 "fcvt.fxu $dst = $src;;">;
272 def FCVTFXTRUNC : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
273 "fcvt.fx.trunc $dst = $src;;">;
274 def FCVTFXUTRUNC : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
275 "fcvt.fxu.trunc $dst = $src;;">;
277 def FCVTFXTRUNCS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
278 "fcvt.fx.trunc.s1 $dst = $src;;">;
279 def FCVTFXUTRUNCS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
280 "fcvt.fxu.trunc.s1 $dst = $src;;">;
282 def FNORMD : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
283 "fnorm.d $dst = $src;;">;
285 def GETFD : AForm<0x03, 0x0b, (ops GR:$dst, FP:$src),
286 "getf.d $dst = $src;;">;
287 def SETFD : AForm<0x03, 0x0b, (ops FP:$dst, GR:$src),
288 "setf.d $dst = $src;;">;
290 def GETFSIG : AForm<0x03, 0x0b, (ops GR:$dst, FP:$src),
291 "getf.sig $dst = $src;;">;
292 def SETFSIG : AForm<0x03, 0x0b, (ops FP:$dst, GR:$src),
293 "setf.sig $dst = $src;;">;
295 def LDF4 : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
296 "ldfs $dst = [$srcPtr];;">;
297 def LDF8 : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
298 "ldfd $dst = [$srcPtr];;">;
300 def STF4 : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
301 "stfs [$dstPtr] = $value;;">;
302 def STF8 : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
303 "stfd [$dstPtr] = $value;;">;
305 let isTerminator = 1, isBranch = 1 in {
306 def BRLCOND_NOTCALL : RawForm<0x03, 0xb0, (ops PR:$qp, i64imm:$dst),
307 "($qp) brl.cond.sptk $dst;;">;
308 def BRCOND_NOTCALL : RawForm<0x03, 0xb0, (ops PR:$qp, GR:$dst),
309 "($qp) br.cond.sptk $dst;;">;
312 let isCall = 1, isTerminator = 1, isBranch = 1,
313 // all calls clobber non-callee-saved registers, and for now, they are these:
314 Defs = [r2,r3,r8,r9,r10,r11,r14,r15,r16,r17,r18,r19,r20,r21,r22,r23,r24,
315 r25,r26,r27,r28,r29,r30,r31,
316 p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,
317 F6,F7,F8,F9,F10,F11,F12,F13,F14,F15,
318 F32,F33,F34,F35,F36,F37,F38,F39,F40,F41,F42,F43,F44,F45,F46,F47,F48,F49,
319 F50,F51,F52,F53,F54,F55,F56,
320 F57,F58,F59,F60,F61,F62,F63,F64,F65,F66,F67,F68,F69,F70,F71,F72,F73,F74,
321 F75,F76,F77,F78,F79,F80,F81,
322 F82,F83,F84,F85,F86,F87,F88,F89,F90,F91,F92,F93,F94,F95,F96,F97,F98,F99,
323 F100,F101,F102,F103,F104,F105,
324 F106,F107,F108,F109,F110,F111,F112,F113,F114,F115,F116,F117,F118,F119,
325 F120,F121,F122,F123,F124,F125,F126,F127,
326 out0,out1,out2,out3,out4,out5,out6,out7] in {
327 def BRCALL : RawForm<0x03, 0xb0, (ops calltarget:$dst),
328 "br.call.sptk rp = $dst;;">; // FIXME: teach llvm about branch regs?
329 def BRLCOND_CALL : RawForm<0x03, 0xb0, (ops PR:$qp, i64imm:$dst),
330 "($qp) brl.cond.call.sptk $dst;;">;
331 def BRCOND_CALL : RawForm<0x03, 0xb0, (ops PR:$qp, GR:$dst),
332 "($qp) br.cond.call.sptk $dst;;">;
335 let isTerminator = 1, isReturn = 1 in
336 def RET : RawForm<0x03, 0xb0, (ops), "br.ret.sptk.many rp;;">; // return