1 //===- IA64InstrInfo.td - Describe the IA64 Instruction Set -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the IA64 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 include "IA64InstrFormats.td"
18 def u6imm : Operand<i8>;
19 def s8imm : Operand<i8> {
20 let PrintMethod = "printS8ImmOperand";
22 def s14imm : Operand<i16> {
23 let PrintMethod = "printS14ImmOperand";
25 def s16imm : Operand<i16>;
26 def s21imm : Operand<i32> {
27 let PrintMethod = "printS21ImmOperand";
29 def u32imm : Operand<i32> {
30 let PrintMethod = "printU32ImmOperand";
32 def s32imm : Operand<i32> {
33 let PrintMethod = "printS32ImmOperand";
35 def u64imm : Operand<i64> {
36 let PrintMethod = "printU64ImmOperand";
39 // the asmprinter needs to know about calls
40 let PrintMethod = "printCallOperand" in
41 def calltarget : Operand<i64>;
43 def PHI : PseudoInstIA64<(ops), "PHI">;
44 def IDEF : PseudoInstIA64<(ops), "// IDEF">;
45 def IUSE : PseudoInstIA64<(ops), "// IUSE">;
46 def WTF : PseudoInstIA64<(ops), "que??">;
47 def ADJUSTCALLSTACKUP : PseudoInstIA64<(ops), "// ADJUSTCALLSTACKUP">;
48 def ADJUSTCALLSTACKDOWN : PseudoInstIA64<(ops), "// ADJUSTCALLSTACKDOWN">;
49 def PSEUDO_ALLOC : PseudoInstIA64<(ops), "// PSEUDO_ALLOC">;
51 def ALLOC : AForm<0x03, 0x0b,
52 (ops GR:$dst, i8imm:$inputs, i8imm:$locals, i8imm:$outputs, i8imm:$rotating),
53 "alloc $dst = ar.pfs,$inputs,$locals,$outputs,$rotating;;">;
55 def MOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "mov $dst = $src;;">;
56 def PMOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src, PR:$qp),
57 "($qp) mov $dst = $src;;">;
59 def SPILL_ALL_PREDICATES_TO_GR : AForm<0x03, 0x0b, (ops GR:$dst),
61 def FILL_ALL_PREDICATES_FROM_GR : AForm<0x03, 0x0b, (ops GR:$src),
64 let isTwoAddress = 1 in {
65 def CMOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src2, GR:$src, PR:$qp),
66 "($qp) mov $dst = $src;;">;
69 def PFMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src, PR:$qp),
70 "($qp) mov $dst = $src;;">;
72 let isTwoAddress = 1 in {
73 def CFMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src2, FP:$src, PR:$qp),
74 "($qp) mov $dst = $src;;">;
77 let isTwoAddress = 1 in {
78 def TCMPNE : AForm<0x03, 0x0b,
79 (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4),
80 "cmp.ne $dst, p0 = $src3, $src4;;">;
82 def TPCMPEQOR : AForm<0x03, 0x0b,
83 (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
84 "($qp) cmp.eq.or $dst, p0 = $src3, $src4;;">;
86 def TPCMPNE : AForm<0x03, 0x0b,
87 (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
88 "($qp) cmp.ne $dst, p0 = $src3, $src4;;">;
90 def TPCMPEQ : AForm<0x03, 0x0b,
91 (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
92 "($qp) cmp.eq $dst, p0 = $src3, $src4;;">;
95 def MOVI32 : AForm<0x03, 0x0b, (ops GR:$dst, u32imm:$imm),
97 def MOVLI32 : AForm<0x03, 0x0b, (ops GR:$dst, u32imm:$imm),
98 "movl $dst = $imm;;">;
99 def MOVLSI32 : AForm<0x03, 0x0b, (ops GR:$dst, s32imm:$imm),
100 "movl $dst = $imm;;">;
101 def MOVLI64 : AForm<0x03, 0x0b, (ops GR:$dst, u64imm:$imm),
102 "movl $dst = $imm;;">;
104 def AND : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
105 "and $dst = $src1, $src2;;">;
106 def OR : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
107 "or $dst = $src1, $src2;;">;
108 def XOR : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
109 "xor $dst = $src1, $src2;;">;
110 def SHL : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
111 "shl $dst = $src1, $src2;;">;
112 def SHLI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm),
113 "shl $dst = $src1, $imm;;">; // FIXME: 6 immediate bits, not 21
114 def SHRU : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
115 "shr.u $dst = $src1, $src2;;">;
116 def SHRUI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm),
117 "shr.u $dst = $src1, $imm;;">;
118 def SHRS : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
119 "shr $dst = $src1, $src2;;">;
120 def SHRSI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm),
121 "shr $dst = $src1, $imm;;">;
123 def EXTRU : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2),
124 "extr.u $dst = $src1, $imm1, $imm2;;">;
126 def DEPZ : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2), "dep.z $dst = $src1, $imm1, $imm2;;">;
128 def SXT1 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt1 $dst = $src;;">;
129 def ZXT1 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt1 $dst = $src;;">;
130 def SXT2 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt2 $dst = $src;;">;
131 def ZXT2 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt2 $dst = $src;;">;
132 def SXT4 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt4 $dst = $src;;">;
133 def ZXT4 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt4 $dst = $src;;">;
135 // the following are all a bit unfortunate: we throw away the complement
137 def CMPEQ : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
138 "cmp.eq $dst, p0 = $src1, $src2;;">;
139 def CMPGT : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
140 "cmp.gt $dst, p0 = $src1, $src2;;">;
141 def CMPGE : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
142 "cmp.ge $dst, p0 = $src1, $src2;;">;
143 def CMPLT : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
144 "cmp.lt $dst, p0 = $src1, $src2;;">;
145 def CMPLE : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
146 "cmp.le $dst, p0 = $src1, $src2;;">;
147 def CMPNE : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
148 "cmp.ne $dst, p0 = $src1, $src2;;">;
149 def CMPLTU : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
150 "cmp.ltu $dst, p0 = $src1, $src2;;">;
151 def CMPGTU : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
152 "cmp.gtu $dst, p0 = $src1, $src2;;">;
153 def CMPLEU : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
154 "cmp.leu $dst, p0 = $src1, $src2;;">;
155 def CMPGEU : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
156 "cmp.geu $dst, p0 = $src1, $src2;;">;
158 // and we do the whole thing again for FP compares!
159 def FCMPEQ : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
160 "fcmp.eq $dst, p0 = $src1, $src2;;">;
161 def FCMPGT : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
162 "fcmp.gt $dst, p0 = $src1, $src2;;">;
163 def FCMPGE : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
164 "fcmp.ge $dst, p0 = $src1, $src2;;">;
165 def FCMPLT : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
166 "fcmp.lt $dst, p0 = $src1, $src2;;">;
167 def FCMPLE : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
168 "fcmp.le $dst, p0 = $src1, $src2;;">;
169 def FCMPNE : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
170 "fcmp.neq $dst, p0 = $src1, $src2;;">;
171 def FCMPLTU : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
172 "fcmp.ltu $dst, p0 = $src1, $src2;;">;
173 def FCMPGTU : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
174 "fcmp.gtu $dst, p0 = $src1, $src2;;">;
175 def FCMPLEU : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
176 "fcmp.leu $dst, p0 = $src1, $src2;;">;
177 def FCMPGEU : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
178 "fcmp.geu $dst, p0 = $src1, $src2;;">;
180 def PCMPEQOR : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
181 "($qp) cmp.eq.or $dst, p0 = $src1, $src2;;">;
182 def PCMPEQUNC : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
183 "($qp) cmp.eq.unc $dst, p0 = $src1, $src2;;">;
184 def PCMPNE : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
185 "($qp) cmp.ne $dst, p0 = $src1, $src2;;">;
188 def BCMPEQ : AForm<0x03, 0x0b, (ops PR:$dst1, PR:$dst2, GR:$src1, GR:$src2),
189 "cmp.eq $dst1, dst2 = $src1, $src2;;">;
191 def ADD : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
192 "add $dst = $src1, $src2;;">;
193 def ADDIMM14 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
194 "adds $dst = $imm, $src1;;">;
196 def ADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm),
197 "add $dst = $imm, $src1;;">;
198 def CADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm, PR:$qp),
199 "($qp) add $dst = $imm, $src1;;">;
201 let isTwoAddress = 1 in {
202 def TPCADDIMM22 : AForm<0x03, 0x0b,
203 (ops GR:$dst, GR:$src1, s21imm:$imm, PR:$qp),
204 "($qp) add $dst = $imm, $dst;;">;
205 def TPCMPIMM8NE : AForm<0x03, 0x0b,
206 (ops PR:$dst, PR:$src1, s21imm:$imm, GR:$src2, PR:$qp),
207 "($qp) cmp.ne $dst , p0 = $imm, $src2;;">;
210 def SUB : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
211 "sub $dst = $src1, $src2;;">;
212 def SUBIMM8 : AForm<0x03, 0x0b, (ops GR:$dst, s8imm:$imm, GR:$src2),
213 "sub $dst = $imm, $src2;;">;
215 def ST1 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
216 "st1 [$dstPtr] = $value;;">;
217 def ST2 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
218 "st2 [$dstPtr] = $value;;">;
219 def ST4 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
220 "st4 [$dstPtr] = $value;;">;
221 def ST8 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
222 "st8 [$dstPtr] = $value;;">;
224 def LD1 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
225 "ld1 $dst = [$srcPtr];;">;
226 def LD2 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
227 "ld2 $dst = [$srcPtr];;">;
228 def LD4 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
229 "ld4 $dst = [$srcPtr];;">;
230 def LD8 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
231 "ld8 $dst = [$srcPtr];;">;
234 def FADD : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
235 "fadd $dst = $src1, $src2;;">;
236 def FADDS: AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
237 "fadd.s $dst = $src1, $src2;;">;
238 def FSUB : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
239 "fsub $dst = $src1, $src2;;">;
240 def FMPY : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
241 "fmpy $dst = $src1, $src2;;">;
242 def FMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
243 "mov $dst = $src;;">; // XXX: there _is_ no fmov
244 def FMA : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
245 "fma $dst = $src1, $src2, $src3;;">;
246 def FMS : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
247 "fms $dst = $src1, $src2, $src3;;">;
248 def FNMA : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
249 "fnma $dst = $src1, $src2, $src3;;">;
250 def FABS : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
251 "fabs $dst = $src;;">;
252 def FNEG : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
253 "fneg $dst = $src;;">;
254 def FNEGABS : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
255 "fnegabs $dst = $src;;">;
257 def CFMAS1 : AForm<0x03, 0x0b,
258 (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
259 "($qp) fma.s1 $dst = $src1, $src2, $src3;;">;
260 def CFNMAS1 : AForm<0x03, 0x0b,
261 (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
262 "($qp) fnma.s1 $dst = $src1, $src2, $src3;;">;
264 def FRCPAS1 : AForm<0x03, 0x0b, (ops FP:$dstFR, PR:$dstPR, FP:$src1, FP:$src2),
265 "frcpa.s1 $dstFR, $dstPR = $src1, $src2;;">;
267 def XMAL : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
268 "xma.l $dst = $src1, $src2, $src3;;">;
270 def FCVTXF : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
271 "fcvt.xf $dst = $src;;">;
272 def FCVTXUF : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
273 "fcvt.xuf $dst = $src;;">;
274 def FCVTXUFS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
275 "fcvt.xuf.s1 $dst = $src;;">;
276 def FCVTFX : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
277 "fcvt.fx $dst = $src;;">;
278 def FCVTFXU : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
279 "fcvt.fxu $dst = $src;;">;
281 def FCVTFXTRUNC : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
282 "fcvt.fx.trunc $dst = $src;;">;
283 def FCVTFXUTRUNC : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
284 "fcvt.fxu.trunc $dst = $src;;">;
286 def FCVTFXTRUNCS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
287 "fcvt.fx.trunc.s1 $dst = $src;;">;
288 def FCVTFXUTRUNCS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
289 "fcvt.fxu.trunc.s1 $dst = $src;;">;
291 def FNORMD : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
292 "fnorm.d $dst = $src;;">;
294 def GETFD : AForm<0x03, 0x0b, (ops GR:$dst, FP:$src),
295 "getf.d $dst = $src;;">;
296 def SETFD : AForm<0x03, 0x0b, (ops FP:$dst, GR:$src),
297 "setf.d $dst = $src;;">;
299 def GETFSIG : AForm<0x03, 0x0b, (ops GR:$dst, FP:$src),
300 "getf.sig $dst = $src;;">;
301 def SETFSIG : AForm<0x03, 0x0b, (ops FP:$dst, GR:$src),
302 "setf.sig $dst = $src;;">;
304 def LDF4 : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
305 "ldfs $dst = [$srcPtr];;">;
306 def LDF8 : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
307 "ldfd $dst = [$srcPtr];;">;
309 def STF4 : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
310 "stfs [$dstPtr] = $value;;">;
311 def STF8 : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
312 "stfd [$dstPtr] = $value;;">;
314 let isTerminator = 1, isBranch = 1 in {
315 def BRLCOND_NOTCALL : RawForm<0x03, 0xb0, (ops PR:$qp, i64imm:$dst),
316 "($qp) brl.cond.sptk $dst;;">;
317 def BRCOND_NOTCALL : RawForm<0x03, 0xb0, (ops PR:$qp, GR:$dst),
318 "($qp) br.cond.sptk $dst;;">;
321 let isCall = 1, isTerminator = 1, isBranch = 1,
322 // all calls clobber non-callee-saved registers, and for now, they are these:
323 Defs = [r2,r3,r8,r9,r10,r11,r14,r15,r16,r17,r18,r19,r20,r21,r22,r23,r24,
324 r25,r26,r27,r28,r29,r30,r31,
325 p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,
326 F6,F7,F8,F9,F10,F11,F12,F13,F14,F15,
327 F32,F33,F34,F35,F36,F37,F38,F39,F40,F41,F42,F43,F44,F45,F46,F47,F48,F49,
328 F50,F51,F52,F53,F54,F55,F56,
329 F57,F58,F59,F60,F61,F62,F63,F64,F65,F66,F67,F68,F69,F70,F71,F72,F73,F74,
330 F75,F76,F77,F78,F79,F80,F81,
331 F82,F83,F84,F85,F86,F87,F88,F89,F90,F91,F92,F93,F94,F95,F96,F97,F98,F99,
332 F100,F101,F102,F103,F104,F105,
333 F106,F107,F108,F109,F110,F111,F112,F113,F114,F115,F116,F117,F118,F119,
334 F120,F121,F122,F123,F124,F125,F126,F127,
335 out0,out1,out2,out3,out4,out5,out6,out7] in {
336 def BRCALL : RawForm<0x03, 0xb0, (ops calltarget:$dst),
337 "br.call.sptk rp = $dst;;">; // FIXME: teach llvm about branch regs?
338 def BRLCOND_CALL : RawForm<0x03, 0xb0, (ops PR:$qp, i64imm:$dst),
339 "($qp) brl.cond.call.sptk $dst;;">;
340 def BRCOND_CALL : RawForm<0x03, 0xb0, (ops PR:$qp, GR:$dst),
341 "($qp) br.cond.call.sptk $dst;;">;
344 let isTerminator = 1, isReturn = 1 in
345 def RET : RawForm<0x03, 0xb0, (ops), "br.ret.sptk.many rp;;">; // return