1 //===- IA64InstrInfo.td - Describe the IA64 Instruction Set -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the IA64 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 include "IA64InstrFormats.td"
18 //===----------------------------------------------------------------------===//
19 // IA-64 specific DAG Nodes.
22 def IA64getfd : SDNode<"IA64ISD::GETFD", SDTFPToIntOp, []>;
26 def u2imm : Operand<i8>;
27 def u6imm : Operand<i8>;
28 def s8imm : Operand<i8> {
29 let PrintMethod = "printS8ImmOperand";
31 def s14imm : Operand<i64> {
32 let PrintMethod = "printS14ImmOperand";
34 def s22imm : Operand<i64> {
35 let PrintMethod = "printS22ImmOperand";
37 def u64imm : Operand<i64> {
38 let PrintMethod = "printU64ImmOperand";
40 def s64imm : Operand<i64> {
41 let PrintMethod = "printS64ImmOperand";
44 let PrintMethod = "printGlobalOperand" in
45 def globaladdress : Operand<i64>;
47 // the asmprinter needs to know about calls
48 let PrintMethod = "printCallOperand" in
49 def calltarget : Operand<i64>;
51 /* new daggy action!!! */
53 def is32ones : PatLeaf<(i64 imm), [{
54 // is32ones predicate - True if the immediate is 0x00000000FFFFFFFF
55 // Used to create ZXT4s appropriately
56 uint64_t v = (uint64_t)N->getValue();
57 return (v == 0x00000000FFFFFFFFLL);
60 // isMIXable predicates - True if the immediate is
61 // 0xFF00FF00FF00FF00, 0x00FF00FF00FF00FF
62 // etc, through 0x00000000FFFFFFFF
63 // Used to test for the suitability of mix*
64 def isMIX1Lable: PatLeaf<(i64 imm), [{
65 return((uint64_t)N->getValue()==0xFF00FF00FF00FF00LL);
67 def isMIX1Rable: PatLeaf<(i64 imm), [{
68 return((uint64_t)N->getValue()==0x00FF00FF00FF00FFLL);
70 def isMIX2Lable: PatLeaf<(i64 imm), [{
71 return((uint64_t)N->getValue()==0xFFFF0000FFFF0000LL);
73 def isMIX2Rable: PatLeaf<(i64 imm), [{
74 return((uint64_t)N->getValue()==0x0000FFFF0000FFFFLL);
76 def isMIX4Lable: PatLeaf<(i64 imm), [{
77 return((uint64_t)N->getValue()==0xFFFFFFFF00000000LL);
79 def isMIX4Rable: PatLeaf<(i64 imm), [{
80 return((uint64_t)N->getValue()==0x00000000FFFFFFFFLL);
83 def isSHLADDimm: PatLeaf<(i64 imm), [{
84 // isSHLADDimm predicate - True if the immediate is exactly 1, 2, 3 or 4
86 // Used to create shladd instructions appropriately
87 int64_t v = (int64_t)N->getValue();
88 return (v >= 1 && v <= 4);
91 def immSExt14 : PatLeaf<(i64 imm), [{
92 // immSExt14 predicate - True if the immediate fits in a 14-bit sign extended
93 // field. Used by instructions like 'adds'.
94 int64_t v = (int64_t)N->getValue();
95 return (v <= 8191 && v >= -8192);
98 def imm64 : PatLeaf<(i64 imm), [{
99 // imm64 predicate - True if the immediate fits in a 64-bit
100 // field - i.e., true. used to keep movl happy
104 def ADD : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
105 "add $dst = $src1, $src2;;",
106 [(set GR:$dst, (add GR:$src1, GR:$src2))]>;
108 def ADD1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
109 "add $dst = $src1, $src2, 1;;",
110 [(set GR:$dst, (add (add GR:$src1, GR:$src2), 1))]>;
112 def ADDS : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
113 "adds $dst = $imm, $src1;;",
114 [(set GR:$dst, (add GR:$src1, immSExt14:$imm))]>;
116 def PADDS: AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm, PR:$qp),
117 "($qp) adds $dst = $imm, $src1;;",
120 def MOVL : AForm_DAG<0x03, 0x0b, (ops GR:$dst, s64imm:$imm),
121 "movl $dst = $imm;;",
122 [(set GR:$dst, imm64:$imm)]>;
124 def ADDL_GA : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, globaladdress:$imm),
125 "addl $dst = $imm, $src1;;",
129 def ADDL_EA : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, calltarget:$imm),
130 "addl $dst = $imm, $src1;;",
133 def SUB : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
134 "sub $dst = $src1, $src2;;",
135 [(set GR:$dst, (sub GR:$src1, GR:$src2))]>;
137 def SUB1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
138 "sub $dst = $src1, $src2, 1;;",
139 [(set GR:$dst, (add (sub GR: $src1, GR:$src2), -1))]>;
141 let isTwoAddress = 1 in {
142 def TPCADDIMM22 : AForm<0x03, 0x0b,
143 (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
144 "($qp) add $dst = $imm, $dst;;">;
145 def TPCMPIMM8NE : AForm<0x03, 0x0b,
146 (ops PR:$dst, PR:$src1, s22imm:$imm, GR:$src2, PR:$qp),
147 "($qp) cmp.ne $dst , p0 = $imm, $src2;;">;
150 // zero extend a bool (predicate reg) into an integer reg
151 def ZXTb : Pat<(zext PR:$src),
152 (TPCADDIMM22 (ADDS r0, 0), 1, PR:$src)>;
154 // normal sign/zero-extends
155 def SXT1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt1 $dst = $src;;",
156 [(set GR:$dst, (sext_inreg GR:$src, i8))]>;
157 def ZXT1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt1 $dst = $src;;",
158 [(set GR:$dst, (and GR:$src, 255))]>;
159 def SXT2 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt2 $dst = $src;;",
160 [(set GR:$dst, (sext_inreg GR:$src, i16))]>;
161 def ZXT2 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt2 $dst = $src;;",
162 [(set GR:$dst, (and GR:$src, 65535))]>;
163 def SXT4 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt4 $dst = $src;;",
164 [(set GR:$dst, (sext_inreg GR:$src, i32))]>;
165 def ZXT4 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt4 $dst = $src;;",
166 [(set GR:$dst, (and GR:$src, is32ones))]>;
168 // fixme: shrs vs shru?
169 def MIX1L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
170 "mix1.l $dst = $src1, $src2;;",
171 [(set GR:$dst, (or (and GR:$src1, isMIX1Lable),
172 (and (srl GR:$src2, (i64 8)), isMIX1Lable)))]>;
174 def MIX2L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
175 "mix2.l $dst = $src1, $src2;;",
176 [(set GR:$dst, (or (and GR:$src1, isMIX2Lable),
177 (and (srl GR:$src2, (i64 16)), isMIX2Lable)))]>;
179 def MIX4L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
180 "mix4.l $dst = $src1, $src2;;",
181 [(set GR:$dst, (or (and GR:$src1, isMIX4Lable),
182 (and (srl GR:$src2, (i64 32)), isMIX4Lable)))]>;
184 def MIX1R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
185 "mix1.r $dst = $src1, $src2;;",
186 [(set GR:$dst, (or (and (shl GR:$src1, (i64 8)), isMIX1Rable),
187 (and GR:$src2, isMIX1Rable)))]>;
189 def MIX2R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
190 "mix2.r $dst = $src1, $src2;;",
191 [(set GR:$dst, (or (and (shl GR:$src1, (i64 16)), isMIX2Rable),
192 (and GR:$src2, isMIX2Rable)))]>;
194 def MIX4R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
195 "mix4.r $dst = $src1, $src2;;",
196 [(set GR:$dst, (or (and (shl GR:$src1, (i64 32)), isMIX4Rable),
197 (and GR:$src2, isMIX4Rable)))]>;
199 def GETFSIGD : AForm_DAG<0x03, 0x0b, (ops GR:$dst, FP:$src),
200 "getf.sig $dst = $src;;",
203 def SETFSIGD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, GR:$src),
204 "setf.sig $dst = $src;;",
207 def XMALD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
208 "xma.l $dst = $src1, $src2, $src3;;",
210 def XMAHD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
211 "xma.h $dst = $src1, $src2, $src3;;",
213 def XMAHUD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
214 "xma.hu $dst = $src1, $src2, $src3;;",
217 // pseudocode for integer multiplication
218 def : Pat<(mul GR:$src1, GR:$src2),
219 (GETFSIGD (XMALD (SETFSIGD GR:$src1), (SETFSIGD GR:$src2), F0))>;
220 def : Pat<(mulhs GR:$src1, GR:$src2),
221 (GETFSIGD (XMAHD (SETFSIGD GR:$src1), (SETFSIGD GR:$src2), F0))>;
222 def : Pat<(mulhu GR:$src1, GR:$src2),
223 (GETFSIGD (XMAHUD (SETFSIGD GR:$src1), (SETFSIGD GR:$src2), F0))>;
225 // TODO: addp4 (addp4 dst = src, r0 is a 32-bit add)
228 // def ADDS : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
229 // "adds $dst = $imm, $src1;;">;
231 def AND : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
232 "and $dst = $src1, $src2;;",
233 [(set GR:$dst, (and GR:$src1, GR:$src2))]>;
234 def ANDCM : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
235 "andcm $dst = $src1, $src2;;",
236 [(set GR:$dst, (and GR:$src1, (not GR:$src2)))]>;
237 // TODO: and/andcm/or/xor/add/sub/shift immediate forms
238 def OR : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
239 "or $dst = $src1, $src2;;",
240 [(set GR:$dst, (or GR:$src1, GR:$src2))]>;
242 def pOR : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2, PR:$qp),
243 "($qp) or $dst = $src1, $src2;;">;
245 // the following are all a bit unfortunate: we throw away the complement
247 def CMPEQ : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
248 "cmp.eq $dst, p0 = $src1, $src2;;",
249 [(set PR:$dst, (seteq GR:$src1, GR:$src2))]>;
250 def CMPGT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
251 "cmp.gt $dst, p0 = $src1, $src2;;",
252 [(set PR:$dst, (setgt GR:$src1, GR:$src2))]>;
253 def CMPGE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
254 "cmp.ge $dst, p0 = $src1, $src2;;",
255 [(set PR:$dst, (setge GR:$src1, GR:$src2))]>;
256 def CMPLT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
257 "cmp.lt $dst, p0 = $src1, $src2;;",
258 [(set PR:$dst, (setlt GR:$src1, GR:$src2))]>;
259 def CMPLE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
260 "cmp.le $dst, p0 = $src1, $src2;;",
261 [(set PR:$dst, (setle GR:$src1, GR:$src2))]>;
262 def CMPNE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
263 "cmp.ne $dst, p0 = $src1, $src2;;",
264 [(set PR:$dst, (setne GR:$src1, GR:$src2))]>;
265 def CMPLTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
266 "cmp.ltu $dst, p0 = $src1, $src2;;",
267 [(set PR:$dst, (setult GR:$src1, GR:$src2))]>;
268 def CMPGTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
269 "cmp.gtu $dst, p0 = $src1, $src2;;",
270 [(set PR:$dst, (setugt GR:$src1, GR:$src2))]>;
271 def CMPLEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
272 "cmp.leu $dst, p0 = $src1, $src2;;",
273 [(set PR:$dst, (setule GR:$src1, GR:$src2))]>;
274 def CMPGEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
275 "cmp.geu $dst, p0 = $src1, $src2;;",
276 [(set PR:$dst, (setuge GR:$src1, GR:$src2))]>;
278 // and we do the whole thing again for FP compares!
279 def FCMPEQ : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
280 "fcmp.eq $dst, p0 = $src1, $src2;;",
281 [(set PR:$dst, (seteq FP:$src1, FP:$src2))]>;
282 def FCMPGT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
283 "fcmp.gt $dst, p0 = $src1, $src2;;",
284 [(set PR:$dst, (setgt FP:$src1, FP:$src2))]>;
285 def FCMPGE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
286 "fcmp.ge $dst, p0 = $src1, $src2;;",
287 [(set PR:$dst, (setge FP:$src1, FP:$src2))]>;
288 def FCMPLT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
289 "fcmp.lt $dst, p0 = $src1, $src2;;",
290 [(set PR:$dst, (setlt FP:$src1, FP:$src2))]>;
291 def FCMPLE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
292 "fcmp.le $dst, p0 = $src1, $src2;;",
293 [(set PR:$dst, (setle FP:$src1, FP:$src2))]>;
294 def FCMPNE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
295 "fcmp.neq $dst, p0 = $src1, $src2;;",
296 [(set PR:$dst, (setne FP:$src1, FP:$src2))]>;
297 def FCMPLTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
298 "fcmp.ltu $dst, p0 = $src1, $src2;;",
299 [(set PR:$dst, (setult FP:$src1, FP:$src2))]>;
300 def FCMPGTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
301 "fcmp.gtu $dst, p0 = $src1, $src2;;",
302 [(set PR:$dst, (setugt FP:$src1, FP:$src2))]>;
303 def FCMPLEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
304 "fcmp.leu $dst, p0 = $src1, $src2;;",
305 [(set PR:$dst, (setule FP:$src1, FP:$src2))]>;
306 def FCMPGEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
307 "fcmp.geu $dst, p0 = $src1, $src2;;",
308 [(set PR:$dst, (setuge FP:$src1, FP:$src2))]>;
310 def PCMPEQUNCR0R0 : AForm<0x03, 0x0b, (ops PR:$dst, PR:$qp),
311 "($qp) cmp.eq.unc $dst, p0 = r0, r0;;">;
313 def : Pat<(trunc GR:$src), // truncate i64 to i1
314 (CMPNE GR:$src, r0)>; // $src!=0? If so, PR:$dst=true
316 let isTwoAddress=1 in {
317 def TPCMPEQR0R0 : AForm<0x03, 0x0b, (ops PR:$dst, PR:$bogus, PR:$qp),
318 "($qp) cmp.eq $dst, p0 = r0, r0;;">;
319 def TPCMPNER0R0 : AForm<0x03, 0x0b, (ops PR:$dst, PR:$bogus, PR:$qp),
320 "($qp) cmp.ne $dst, p0 = r0, r0;;">;
323 /* our pseudocode for OR on predicates is:
326 (pA) cmp.eq.unc pC,p0 = r0,r0 // pC = pA
328 (pB) cmp.eq pC,p0 = r0,r0 // if (pB) pC = 1 */
330 def bOR : Pat<(or PR:$src1, PR:$src2),
331 (TPCMPEQR0R0 (PCMPEQUNCR0R0 PR:$src1), PR:$src2)>;
333 /* our pseudocode for AND on predicates is:
335 (pA) cmp.eq.unc pC,p0 = r0,r0 // pC = pA
336 cmp.eq pTemp,p0 = r0,r0 // pTemp = NOT pB
338 (pB) cmp.ne pTemp,p0 = r0,r0
340 (pTemp)cmp.ne pC,p0 = r0,r0 // if (NOT pB) pC = 0 */
342 def bAND : Pat<(and PR:$src1, PR:$src2),
343 ( TPCMPNER0R0 (PCMPEQUNCR0R0 PR:$src1),
344 (TPCMPNER0R0 (CMPEQ r0, r0), PR:$src2) )>;
346 /* one possible routine for XOR on predicates is:
348 // Compute px = py ^ pz
349 // using sum of products: px = (py & !pz) | (pz & !py)
350 // Uses 5 instructions in 3 cycles.
352 (pz) cmp.eq.unc px = r0, r0 // px = pz
353 (py) cmp.eq.unc pt = r0, r0 // pt = py
356 (pt) cmp.ne.and px = r0, r0 // px = px & !pt (px = pz & !pt)
357 (pz) cmp.ne.and pt = r0, r0 // pt = pt & !pz
361 (pt) cmp.eq.or px = r0, r0 // px = px | pt
363 *** Another, which we use here, requires one scratch GR. it is:
365 mov rt = 0 // initialize rt off critical path
369 (pz) cmp.eq.unc px = r0, r0 // px = pz
370 (pz) mov rt = 1 // rt = pz
373 (py) cmp.ne px = 1, rt // if (py) px = !pz
375 .. these routines kindly provided by Jim Hull
378 def bXOR : Pat<(xor PR:$src1, PR:$src2),
379 (TPCMPIMM8NE (PCMPEQUNCR0R0 PR:$src2), 1,
380 (PADDS r0, 1, PR:$src2),
383 def XOR : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
384 "xor $dst = $src1, $src2;;",
385 [(set GR:$dst, (xor GR:$src1, GR:$src2))]>;
387 def SHLADD: AForm_DAG<0x03, 0x0b, (ops GR:$dst,GR:$src1,s64imm:$imm,GR:$src2),
388 "shladd $dst = $src1, $imm, $src2;;",
389 [(set GR:$dst, (add GR:$src2, (shl GR:$src1, isSHLADDimm:$imm)))]>;
391 def SHL : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
392 "shl $dst = $src1, $src2;;",
393 [(set GR:$dst, (shl GR:$src1, GR:$src2))]>;
395 def SHRU : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
396 "shr.u $dst = $src1, $src2;;",
397 [(set GR:$dst, (srl GR:$src1, GR:$src2))]>;
399 def SHRS : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
400 "shr $dst = $src1, $src2;;",
401 [(set GR:$dst, (sra GR:$src1, GR:$src2))]>;
403 def MOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "mov $dst = $src;;">;
404 def FMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
405 "mov $dst = $src;;">; // XXX: there _is_ no fmov
406 def PMOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src, PR:$qp),
407 "($qp) mov $dst = $src;;">;
409 def SPILL_ALL_PREDICATES_TO_GR : AForm<0x03, 0x0b, (ops GR:$dst),
411 def FILL_ALL_PREDICATES_FROM_GR : AForm<0x03, 0x0b, (ops GR:$src),
414 let isTwoAddress = 1 in {
415 def CMOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src2, GR:$src, PR:$qp),
416 "($qp) mov $dst = $src;;">;
419 def PFMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src, PR:$qp),
420 "($qp) mov $dst = $src;;">;
422 let isTwoAddress = 1 in {
423 def CFMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src2, FP:$src, PR:$qp),
424 "($qp) mov $dst = $src;;">;
427 // TODO: select bools
428 def SELECTINT : Pat<(select PR:$which, GR:$src1, GR:$src2),
429 (CMOV (MOV GR:$src2), GR:$src1, PR:$which)>; // note order!
430 def SELECTFP : Pat<(select PR:$which, FP:$src1, FP:$src2),
431 (CFMOV (FMOV FP:$src2), FP:$src1, PR:$which)>; // note order!
433 // load constants of various sizes // FIXME: prettyprint -ve constants
434 def : Pat<(i64 immSExt14:$imm), (ADDS r0, immSExt14:$imm)>;
435 def : Pat<(i64 imm64:$imm), (MOVL imm64:$imm)>;
436 def : Pat<(i1 -1), (CMPEQ r0, r0)>; // TODO: this should just be a ref to p0
437 def : Pat<(i1 0), (CMPNE r0, r0)>; // TODO: any instruction actually *using*
438 // this predicate should be killed!
440 // TODO: support postincrement (reg, imm9) loads+stores - this needs more
443 def PHI : PseudoInstIA64<(ops variable_ops), "PHI">;
444 def IDEF : PseudoInstIA64<(ops variable_ops), "// IDEF">;
446 def IDEF_GR_D : PseudoInstIA64_DAG<(ops GR:$reg), "// $reg = IDEF",
447 [(set GR:$reg, (undef))]>;
448 def IDEF_FP_D : PseudoInstIA64_DAG<(ops FP:$reg), "// $reg = IDEF",
449 [(set FP:$reg, (undef))]>;
450 def IDEF_PR_D : PseudoInstIA64_DAG<(ops PR:$reg), "// $reg = IDEF",
451 [(set PR:$reg, (undef))]>;
453 def IUSE : PseudoInstIA64<(ops variable_ops), "// IUSE">;
454 def ADJUSTCALLSTACKUP : PseudoInstIA64<(ops variable_ops),
455 "// ADJUSTCALLSTACKUP">;
456 def ADJUSTCALLSTACKDOWN : PseudoInstIA64<(ops variable_ops),
457 "// ADJUSTCALLSTACKDOWN">;
458 def PSEUDO_ALLOC : PseudoInstIA64<(ops GR:$foo), "// PSEUDO_ALLOC">;
460 def ALLOC : AForm<0x03, 0x0b,
461 (ops GR:$dst, i8imm:$inputs, i8imm:$locals, i8imm:$outputs, i8imm:$rotating),
462 "alloc $dst = ar.pfs,$inputs,$locals,$outputs,$rotating;;">;
464 let isTwoAddress = 1 in {
465 def TCMPNE : AForm<0x03, 0x0b,
466 (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4),
467 "cmp.ne $dst, p0 = $src3, $src4;;">;
469 def TPCMPEQOR : AForm<0x03, 0x0b,
470 (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
471 "($qp) cmp.eq.or $dst, p0 = $src3, $src4;;">;
473 def TPCMPNE : AForm<0x03, 0x0b,
474 (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
475 "($qp) cmp.ne $dst, p0 = $src3, $src4;;">;
477 def TPCMPEQ : AForm<0x03, 0x0b,
478 (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
479 "($qp) cmp.eq $dst, p0 = $src3, $src4;;">;
482 def MOVSIMM14 : AForm<0x03, 0x0b, (ops GR:$dst, s14imm:$imm),
483 "mov $dst = $imm;;">;
484 def MOVSIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, s22imm:$imm),
485 "mov $dst = $imm;;">;
486 def MOVLIMM64 : AForm<0x03, 0x0b, (ops GR:$dst, s64imm:$imm),
487 "movl $dst = $imm;;">;
489 def SHLI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
490 "shl $dst = $src1, $imm;;">;
491 def SHRUI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
492 "shr.u $dst = $src1, $imm;;">;
493 def SHRSI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
494 "shr $dst = $src1, $imm;;">;
496 def EXTRU : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2),
497 "extr.u $dst = $src1, $imm1, $imm2;;">;
499 def DEPZ : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2), "dep.z $dst = $src1, $imm1, $imm2;;">;
501 def PCMPEQOR : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
502 "($qp) cmp.eq.or $dst, p0 = $src1, $src2;;">;
503 def PCMPEQUNC : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
504 "($qp) cmp.eq.unc $dst, p0 = $src1, $src2;;">;
505 def PCMPNE : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
506 "($qp) cmp.ne $dst, p0 = $src1, $src2;;">;
509 def BCMPEQ : AForm<0x03, 0x0b, (ops PR:$dst1, PR:$dst2, GR:$src1, GR:$src2),
510 "cmp.eq $dst1, dst2 = $src1, $src2;;">;
512 def ADDIMM14 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
513 "adds $dst = $imm, $src1;;">;
515 def ADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm),
516 "add $dst = $imm, $src1;;">;
517 def CADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
518 "($qp) add $dst = $imm, $src1;;">;
520 def SUBIMM8 : AForm<0x03, 0x0b, (ops GR:$dst, s8imm:$imm, GR:$src2),
521 "sub $dst = $imm, $src2;;">;
524 def ST1 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
525 "st1 [$dstPtr] = $value;;">;
526 def ST2 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
527 "st2 [$dstPtr] = $value;;">;
528 def ST4 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
529 "st4 [$dstPtr] = $value;;">;
530 def ST8 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
531 "st8 [$dstPtr] = $value;;">;
532 def STF4 : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
533 "stfs [$dstPtr] = $value;;">;
534 def STF8 : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
535 "stfd [$dstPtr] = $value;;">;
539 def LD1 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
540 "ld1 $dst = [$srcPtr];;">;
541 def LD2 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
542 "ld2 $dst = [$srcPtr];;">;
543 def LD4 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
544 "ld4 $dst = [$srcPtr];;">;
545 def LD8 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
546 "ld8 $dst = [$srcPtr];;">;
547 def LDF4 : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
548 "ldfs $dst = [$srcPtr];;">;
549 def LDF8 : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
550 "ldfd $dst = [$srcPtr];;">;
553 def POPCNT : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src),
554 "popcnt $dst = $src;;",
555 [(set GR:$dst, (ctpop GR:$src))]>;
557 // some FP stuff: // TODO: single-precision stuff?
558 def FADD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
559 "fadd $dst = $src1, $src2;;",
560 [(set FP:$dst, (fadd FP:$src1, FP:$src2))]>;
561 def FADDS: AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
562 "fadd.s $dst = $src1, $src2;;">;
563 def FSUB : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
564 "fsub $dst = $src1, $src2;;",
565 [(set FP:$dst, (fsub FP:$src1, FP:$src2))]>;
566 def FMPY : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
567 "fmpy $dst = $src1, $src2;;",
568 [(set FP:$dst, (fmul FP:$src1, FP:$src2))]>;
569 def FMA : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
570 "fma $dst = $src1, $src2, $src3;;",
571 [(set FP:$dst, (fadd (fmul FP:$src1, FP:$src2), FP:$src3))]>;
572 def FMS : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
573 "fms $dst = $src1, $src2, $src3;;",
574 [(set FP:$dst, (fsub (fmul FP:$src1, FP:$src2), FP:$src3))]>;
575 def FNMA : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
576 "fnma $dst = $src1, $src2, $src3;;",
577 [(set FP:$dst, (fneg (fadd (fmul FP:$src1, FP:$src2), FP:$src3)))]>;
578 def FABS : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src),
579 "fabs $dst = $src;;",
580 [(set FP:$dst, (fabs FP:$src))]>;
581 def FNEG : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src),
582 "fneg $dst = $src;;",
583 [(set FP:$dst, (fneg FP:$src))]>;
584 def FNEGABS : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src),
585 "fnegabs $dst = $src;;",
586 [(set FP:$dst, (fneg (fabs FP:$src)))]>;
588 def CFMAS1 : AForm<0x03, 0x0b,
589 (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
590 "($qp) fma.s1 $dst = $src1, $src2, $src3;;">;
591 def CFNMAS1 : AForm<0x03, 0x0b,
592 (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
593 "($qp) fnma.s1 $dst = $src1, $src2, $src3;;">;
595 def FRCPAS1 : AForm<0x03, 0x0b, (ops FP:$dstFR, PR:$dstPR, FP:$src1, FP:$src2),
596 "frcpa.s1 $dstFR, $dstPR = $src1, $src2;;">;
598 def XMAL : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
599 "xma.l $dst = $src1, $src2, $src3;;">;
601 def FCVTXF : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
602 "fcvt.xf $dst = $src;;">;
603 def FCVTXUF : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
604 "fcvt.xuf $dst = $src;;">;
605 def FCVTXUFS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
606 "fcvt.xuf.s1 $dst = $src;;">;
607 def FCVTFX : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
608 "fcvt.fx $dst = $src;;">;
609 def FCVTFXU : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
610 "fcvt.fxu $dst = $src;;">;
612 def FCVTFXTRUNC : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
613 "fcvt.fx.trunc $dst = $src;;">;
614 def FCVTFXUTRUNC : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
615 "fcvt.fxu.trunc $dst = $src;;">;
617 def FCVTFXTRUNCS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
618 "fcvt.fx.trunc.s1 $dst = $src;;">;
619 def FCVTFXUTRUNCS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
620 "fcvt.fxu.trunc.s1 $dst = $src;;">;
622 def FNORMD : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
623 "fnorm.d $dst = $src;;">;
625 def GETFD : AForm<0x03, 0x0b, (ops GR:$dst, FP:$src),
626 "getf.d $dst = $src;;">;
627 def SETFD : AForm<0x03, 0x0b, (ops FP:$dst, GR:$src),
628 "setf.d $dst = $src;;">;
630 def GETFSIG : AForm<0x03, 0x0b, (ops GR:$dst, FP:$src),
631 "getf.sig $dst = $src;;">;
632 def SETFSIG : AForm<0x03, 0x0b, (ops FP:$dst, GR:$src),
633 "setf.sig $dst = $src;;">;
635 // these four FP<->int conversion patterns need checking/cleaning
636 def SINT_TO_FP : Pat<(sint_to_fp GR:$src),
637 (FNORMD (FCVTXF (SETFSIG GR:$src)))>;
638 def UINT_TO_FP : Pat<(uint_to_fp GR:$src),
639 (FNORMD (FCVTXUF (SETFSIG GR:$src)))>;
640 def FP_TO_SINT : Pat<(i64 (fp_to_sint FP:$src)),
641 (GETFSIG (FCVTFXTRUNC FP:$src))>;
642 def FP_TO_UINT : Pat<(i64 (fp_to_uint FP:$src)),
643 (GETFSIG (FCVTFXUTRUNC FP:$src))>;
646 let isTerminator = 1, isBranch = 1 in {
647 def BRL_NOTCALL : RawForm<0x03, 0xb0, (ops i64imm:$dst),
648 "(p0) brl.cond.sptk $dst;;">;
649 def BRLCOND_NOTCALL : RawForm<0x03, 0xb0, (ops PR:$qp, i64imm:$dst),
650 "($qp) brl.cond.sptk $dst;;">;
651 def BRCOND_NOTCALL : RawForm<0x03, 0xb0, (ops PR:$qp, GR:$dst),
652 "($qp) br.cond.sptk $dst;;">;
655 let isCall = 1, /* isTerminator = 1, isBranch = 1, */
656 Uses = [out0,out1,out2,out3,out4,out5,out6,out7],
657 // all calls clobber non-callee-saved registers, and for now, they are these:
658 Defs = [r2,r3,r8,r9,r10,r11,r14,r15,r16,r17,r18,r19,r20,r21,r22,r23,r24,
659 r25,r26,r27,r28,r29,r30,r31,
660 p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,
661 F6,F7,F8,F9,F10,F11,F12,F13,F14,F15,
662 F32,F33,F34,F35,F36,F37,F38,F39,F40,F41,F42,F43,F44,F45,F46,F47,F48,F49,
663 F50,F51,F52,F53,F54,F55,F56,
664 F57,F58,F59,F60,F61,F62,F63,F64,F65,F66,F67,F68,F69,F70,F71,F72,F73,F74,
665 F75,F76,F77,F78,F79,F80,F81,
666 F82,F83,F84,F85,F86,F87,F88,F89,F90,F91,F92,F93,F94,F95,F96,F97,F98,F99,
667 F100,F101,F102,F103,F104,F105,
668 F106,F107,F108,F109,F110,F111,F112,F113,F114,F115,F116,F117,F118,F119,
669 F120,F121,F122,F123,F124,F125,F126,F127,
670 out0,out1,out2,out3,out4,out5,out6,out7] in {
672 def BRCALL: RawForm<0x03, 0xb0, (ops calltarget:$dst),
673 "br.call.sptk rp = $dst;;">; // FIXME: teach llvm about branch regs?
676 // calls a globaladdress
677 def BRCALL_IPREL_GA : RawForm<0x03, 0xb0, (ops calltarget:$dst),
678 "br.call.sptk rp = $dst;;">; // FIXME: teach llvm about branch regs?
679 // calls an externalsymbol
680 def BRCALL_IPREL_ES : RawForm<0x03, 0xb0, (ops calltarget:$dst),
681 "br.call.sptk rp = $dst;;">; // FIXME: teach llvm about branch regs?
682 // calls through a function descriptor
683 def BRCALL_INDIRECT : RawForm<0x03, 0xb0, (ops GR:$branchreg),
684 "br.call.sptk rp = $branchreg;;">; // FIXME: teach llvm about branch regs?
685 def BRLCOND_CALL : RawForm<0x03, 0xb0, (ops PR:$qp, i64imm:$dst),
686 "($qp) brl.cond.call.sptk $dst;;">;
687 def BRCOND_CALL : RawForm<0x03, 0xb0, (ops PR:$qp, GR:$dst),
688 "($qp) br.cond.call.sptk $dst;;">;
691 let isTerminator = 1, isReturn = 1 in
692 def RET : RawForm<0x03, 0xb0, (ops), "br.ret.sptk.many rp;;">; // return