1 //===- IA64InstrInfo.td - Describe the IA64 Instruction Set -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the IA64 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 include "IA64InstrFormats.td"
18 def u2imm : Operand<i8>;
19 def u6imm : Operand<i8>;
20 def s8imm : Operand<i8> {
21 let PrintMethod = "printS8ImmOperand";
23 def s14imm : Operand<i64> {
24 let PrintMethod = "printS14ImmOperand";
26 def s22imm : Operand<i32> {
27 let PrintMethod = "printS22ImmOperand";
29 def u64imm : Operand<i64> {
30 let PrintMethod = "printU64ImmOperand";
32 def s64imm : Operand<i64> {
33 let PrintMethod = "printS64ImmOperand";
36 let PrintMethod = "printGlobalOperand" in
37 def globaladdress : Operand<i64>;
39 // the asmprinter needs to know about calls
40 let PrintMethod = "printCallOperand" in
41 def calltarget : Operand<i64>;
43 /* new daggy action!!! */
45 def is32ones : PatLeaf<(i64 imm), [{
46 // is32ones predicate - True if the immediate is 0x00000000FFFFFFFF
47 // Used to create ZXT4s appropriately
48 uint64_t v = (uint64_t)N->getValue();
49 return (v == 0x00000000FFFFFFFFLL);
52 // isMIXable predicates - True if the immediate is
53 // 0xFF00FF00FF00FF00, 0x00FF00FF00FF00FF
54 // etc, through 0x00000000FFFFFFFF
55 // Used to test for the suitability of mix*
56 def isMIX1Lable: PatLeaf<(i64 imm), [{
57 return((uint64_t)N->getValue()==0xFF00FF00FF00FF00LL);
59 def isMIX1Rable: PatLeaf<(i64 imm), [{
60 return((uint64_t)N->getValue()==0x00FF00FF00FF00FFLL);
62 def isMIX2Lable: PatLeaf<(i64 imm), [{
63 return((uint64_t)N->getValue()==0xFFFF0000FFFF0000LL);
65 def isMIX2Rable: PatLeaf<(i64 imm), [{
66 return((uint64_t)N->getValue()==0x0000FFFF0000FFFFLL);
68 def isMIX4Lable: PatLeaf<(i64 imm), [{
69 return((uint64_t)N->getValue()==0xFFFFFFFF00000000LL);
71 def isMIX4Rable: PatLeaf<(i64 imm), [{
72 return((uint64_t)N->getValue()==0x00000000FFFFFFFFLL);
75 def isSHLADDimm: PatLeaf<(i64 imm), [{
76 // isSHLADDimm predicate - True if the immediate is exactly 1, 2, 3 or 4
78 // Used to create shladd instructions appropriately
79 int64_t v = (int64_t)N->getValue();
80 return (v >= 1 && v <= 4);
83 def immSExt14 : PatLeaf<(i64 imm), [{
84 // immSExt14 predicate - True if the immediate fits in a 14-bit sign extended
85 // field. Used by instructions like 'adds'.
86 int64_t v = (int64_t)N->getValue();
87 return (v <= 8191 && v >= -8192);
90 def imm64 : PatLeaf<(i64 imm), [{
91 // imm64 predicate - True if the immediate fits in a 64-bit
92 // field - i.e., true. used to keep movl happy
96 def ADD : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
97 "add $dst = $src1, $src2;;",
98 [(set GR:$dst, (add GR:$src1, GR:$src2))]>;
100 def ADD1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
101 "add $dst = $src1, $src2, 1;;",
102 [(set GR:$dst, (add (add GR:$src1, GR:$src2), 1))]>;
104 def ADDS : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
105 "adds $dst = $imm, $src1;;",
106 [(set GR:$dst, (add GR:$src1, immSExt14:$imm))]>;
108 def MOVL : AForm_DAG<0x03, 0x0b, (ops GR:$dst, s64imm:$imm),
109 "movl $dst = $imm;;",
110 [(set GR:$dst, imm64:$imm)]>;
112 def ADDL_GA : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, globaladdress:$imm),
113 "addl $dst = $imm, $src1;;",
116 def SUB : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
117 "sub $dst = $src1, $src2;;",
118 [(set GR:$dst, (sub GR:$src1, GR:$src2))]>;
120 def SUB1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
121 "sub $dst = $src1, $src2, 1;;",
122 [(set GR:$dst, (add (sub GR: $src1, GR:$src2), -1))]>;
124 let isTwoAddress = 1 in {
125 def TPCADDIMM22 : AForm<0x03, 0x0b,
126 (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
127 "($qp) add $dst = $imm, $dst;;">;
128 def TPCMPIMM8NE : AForm<0x03, 0x0b,
129 (ops PR:$dst, PR:$src1, s22imm:$imm, GR:$src2, PR:$qp),
130 "($qp) cmp.ne $dst , p0 = $imm, $src2;;">;
133 // zero extend a bool (predicate reg) into an integer reg
134 def ZXTb : Pat<(zext PR:$src),
135 (TPCADDIMM22 (ADDS r0, 0), 1, PR:$src)>;
137 // normal sign/zero-extends
138 def SXT1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt1 $dst = $src;;",
139 [(set GR:$dst, (sext_inreg GR:$src, i8))]>;
140 def ZXT1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt1 $dst = $src;;",
141 [(set GR:$dst, (and GR:$src, 255))]>;
142 def SXT2 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt2 $dst = $src;;",
143 [(set GR:$dst, (sext_inreg GR:$src, i16))]>;
144 def ZXT2 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt2 $dst = $src;;",
145 [(set GR:$dst, (and GR:$src, 65535))]>;
146 def SXT4 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt4 $dst = $src;;",
147 [(set GR:$dst, (sext_inreg GR:$src, i32))]>;
148 def ZXT4 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt4 $dst = $src;;",
149 [(set GR:$dst, (and GR:$src, is32ones))]>;
151 // fixme: shrs vs shru?
152 def MIX1L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
153 "mix1.l $dst = $src1, $src2;;",
154 [(set GR:$dst, (or (and GR:$src1, isMIX1Lable),
155 (and (srl GR:$src2, 8), isMIX1Lable)))]>;
157 def MIX2L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
158 "mix2.l $dst = $src1, $src2;;",
159 [(set GR:$dst, (or (and GR:$src1, isMIX2Lable),
160 (and (srl GR:$src2, 16), isMIX2Lable)))]>;
162 def MIX4L : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
163 "mix4.l $dst = $src1, $src2;;",
164 [(set GR:$dst, (or (and GR:$src1, isMIX4Lable),
165 (and (srl GR:$src2, 32), isMIX4Lable)))]>;
167 def MIX1R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
168 "mix1.r $dst = $src1, $src2;;",
169 [(set GR:$dst, (or (and (shl GR:$src1, 8), isMIX1Rable),
170 (and GR:$src2, isMIX1Rable)))]>;
172 def MIX2R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
173 "mix2.r $dst = $src1, $src2;;",
174 [(set GR:$dst, (or (and (shl GR:$src1, 16), isMIX2Rable),
175 (and GR:$src2, isMIX2Rable)))]>;
177 def MIX4R : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
178 "mix4.r $dst = $src1, $src2;;",
179 [(set GR:$dst, (or (and (shl GR:$src1, 32), isMIX4Rable),
180 (and GR:$src2, isMIX4Rable)))]>;
182 def GETFSIGD : AForm_DAG<0x03, 0x0b, (ops GR:$dst, FP:$src),
183 "getf.sig $dst = $src;;",
186 def SETFSIGD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, GR:$src),
187 "setf.sig $dst = $src;;",
190 def XMALD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
191 "xma.l $dst = $src1, $src2, $src3;;",
193 def XMAHD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
194 "xma.h $dst = $src1, $src2, $src3;;",
196 def XMAHUD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
197 "xma.hu $dst = $src1, $src2, $src3;;",
200 // pseudocode for integer multiplication
201 def : Pat<(mul GR:$src1, GR:$src2),
202 (GETFSIGD (XMALD (SETFSIGD GR:$src1), (SETFSIGD GR:$src2), F0))>;
203 def : Pat<(mulhs GR:$src1, GR:$src2),
204 (GETFSIGD (XMAHD (SETFSIGD GR:$src1), (SETFSIGD GR:$src2), F0))>;
205 def : Pat<(mulhu GR:$src1, GR:$src2),
206 (GETFSIGD (XMAHUD (SETFSIGD GR:$src1), (SETFSIGD GR:$src2), F0))>;
208 // TODO: addp4 (addp4 dst = src, r0 is a 32-bit add)
211 // def ADDS : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
212 // "adds $dst = $imm, $src1;;">;
214 // load constants of various sizes // FIXME: prettyprint -ve constants
215 def : Pat<(i64 immSExt14:$imm), (ADDS r0, immSExt14:$imm)>;
216 def : Pat<(i64 imm64:$imm), (MOVL imm64:$imm)>;
217 // TODO: def : Pat<(i1 1), (<stuff>)>;
219 def AND : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
220 "and $dst = $src1, $src2;;",
221 [(set GR:$dst, (and GR:$src1, GR:$src2))]>;
222 def ANDCM : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
223 "andcm $dst = $src1, $src2;;",
224 [(set GR:$dst, (and GR:$src1, (not GR:$src2)))]>;
225 // TODO: and/andcm/or/xor/add/sub/shift immediate forms
226 def OR : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
227 "or $dst = $src1, $src2;;",
228 [(set GR:$dst, (or GR:$src1, GR:$src2))]>;
230 def pOR : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2, PR:$qp),
231 "($qp) or $dst = $src1, $src2;;">;
233 def PCMPEQUNCR0R0 : AForm<0x03, 0x0b, (ops PR:$dst, PR:$qp),
234 "($qp) cmp.eq.unc $dst, p0 = r0, r0;;">;
236 let isTwoAddress=1 in
237 def TPCMPEQR0R0 : AForm<0x03, 0x0b, (ops PR:$dst, PR:$bogus, PR:$qp),
238 "($qp) cmp.eq $dst, p0 = r0, r0;;">;
240 /* our pseudocode for OR on predicates is:
243 (pA) cmp.eq.unc pC,p0 = r0,r0 // pC = pA
245 (pB) cmp.eq pC,p0 = r0,r0 // if (pB) pC = 1 */
247 def bOR : Pat<(or PR:$src1, PR:$src2),
248 (TPCMPEQR0R0 (PCMPEQUNCR0R0 PR:$src1), PR:$src2)>;
250 // FIXME: these are bogus
251 def bXOR : Pat<(xor PR:$src1, PR:$src2),
252 (PCMPEQUNCR0R0 PR:$src1)>;
254 def XOR : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
255 "xor $dst = $src1, $src2;;",
256 [(set GR:$dst, (xor GR:$src1, GR:$src2))]>;
258 def SHLADD: AForm_DAG<0x03, 0x0b, (ops GR:$dst,GR:$src1,s64imm:$imm,GR:$src2),
259 "shladd $dst = $src1, $imm, $src2;;",
260 [(set GR:$dst, (add GR:$src2, (shl GR:$src1, isSHLADDimm:$imm)))]>;
262 def SHL : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
263 "shl $dst = $src1, $src2;;",
264 [(set GR:$dst, (shl GR:$src1, GR:$src2))]>;
266 def SHRU : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
267 "shr.u $dst = $src1, $src2;;",
268 [(set GR:$dst, (srl GR:$src1, GR:$src2))]>;
270 def SHRS : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
271 "shr $dst = $src1, $src2;;",
272 [(set GR:$dst, (sra GR:$src1, GR:$src2))]>;
274 // the following are all a bit unfortunate: we throw away the complement
276 def CMPEQ : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
277 "cmp.eq $dst, p0 = $src1, $src2;;",
278 [(set PR:$dst, (seteq GR:$src1, GR:$src2))]>;
279 def CMPGT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
280 "cmp.gt $dst, p0 = $src1, $src2;;",
281 [(set PR:$dst, (setgt GR:$src1, GR:$src2))]>;
282 def CMPGE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
283 "cmp.ge $dst, p0 = $src1, $src2;;",
284 [(set PR:$dst, (setge GR:$src1, GR:$src2))]>;
285 def CMPLT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
286 "cmp.lt $dst, p0 = $src1, $src2;;",
287 [(set PR:$dst, (setlt GR:$src1, GR:$src2))]>;
288 def CMPLE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
289 "cmp.le $dst, p0 = $src1, $src2;;",
290 [(set PR:$dst, (setle GR:$src1, GR:$src2))]>;
291 def CMPNE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
292 "cmp.ne $dst, p0 = $src1, $src2;;",
293 [(set PR:$dst, (setne GR:$src1, GR:$src2))]>;
294 def CMPLTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
295 "cmp.ltu $dst, p0 = $src1, $src2;;",
296 [(set PR:$dst, (setult GR:$src1, GR:$src2))]>;
297 def CMPGTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
298 "cmp.gtu $dst, p0 = $src1, $src2;;",
299 [(set PR:$dst, (setugt GR:$src1, GR:$src2))]>;
300 def CMPLEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
301 "cmp.leu $dst, p0 = $src1, $src2;;",
302 [(set PR:$dst, (setule GR:$src1, GR:$src2))]>;
303 def CMPGEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
304 "cmp.geu $dst, p0 = $src1, $src2;;",
305 [(set PR:$dst, (setuge GR:$src1, GR:$src2))]>;
307 // and we do the whole thing again for FP compares!
308 def FCMPEQ : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
309 "fcmp.eq $dst, p0 = $src1, $src2;;",
310 [(set PR:$dst, (seteq FP:$src1, FP:$src2))]>;
311 def FCMPGT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
312 "fcmp.gt $dst, p0 = $src1, $src2;;",
313 [(set PR:$dst, (setgt FP:$src1, FP:$src2))]>;
314 def FCMPGE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
315 "fcmp.ge $dst, p0 = $src1, $src2;;",
316 [(set PR:$dst, (setge FP:$src1, FP:$src2))]>;
317 def FCMPLT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
318 "fcmp.lt $dst, p0 = $src1, $src2;;",
319 [(set PR:$dst, (setlt FP:$src1, FP:$src2))]>;
320 def FCMPLE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
321 "fcmp.le $dst, p0 = $src1, $src2;;",
322 [(set PR:$dst, (setle FP:$src1, FP:$src2))]>;
323 def FCMPNE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
324 "fcmp.neq $dst, p0 = $src1, $src2;;",
325 [(set PR:$dst, (setne FP:$src1, FP:$src2))]>;
326 def FCMPLTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
327 "fcmp.ltu $dst, p0 = $src1, $src2;;",
328 [(set PR:$dst, (setult FP:$src1, FP:$src2))]>;
329 def FCMPGTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
330 "fcmp.gtu $dst, p0 = $src1, $src2;;",
331 [(set PR:$dst, (setugt FP:$src1, FP:$src2))]>;
332 def FCMPLEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
333 "fcmp.leu $dst, p0 = $src1, $src2;;",
334 [(set PR:$dst, (setule FP:$src1, FP:$src2))]>;
335 def FCMPGEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
336 "fcmp.geu $dst, p0 = $src1, $src2;;",
337 [(set PR:$dst, (setuge FP:$src1, FP:$src2))]>;
339 // TODO: support postincrement (reg, imm9) loads+stores - this needs more
342 def PHI : PseudoInstIA64<(ops variable_ops), "PHI">;
343 def IDEF : PseudoInstIA64<(ops variable_ops), "// IDEF">;
345 def IDEF_GR_D : PseudoInstIA64_DAG<(ops GR:$reg), "// $reg = IDEF",
346 [(set GR:$reg, (undef))]>;
347 def IDEF_FP_D : PseudoInstIA64_DAG<(ops FP:$reg), "// $reg = IDEF",
348 [(set FP:$reg, (undef))]>;
349 def IDEF_PR_D : PseudoInstIA64_DAG<(ops PR:$reg), "// $reg = IDEF",
350 [(set PR:$reg, (undef))]>;
352 def IUSE : PseudoInstIA64<(ops variable_ops), "// IUSE">;
353 def ADJUSTCALLSTACKUP : PseudoInstIA64<(ops variable_ops),
354 "// ADJUSTCALLSTACKUP">;
355 def ADJUSTCALLSTACKDOWN : PseudoInstIA64<(ops variable_ops),
356 "// ADJUSTCALLSTACKDOWN">;
357 def PSEUDO_ALLOC : PseudoInstIA64<(ops GR:$foo), "// PSEUDO_ALLOC">;
359 def ALLOC : AForm<0x03, 0x0b,
360 (ops GR:$dst, i8imm:$inputs, i8imm:$locals, i8imm:$outputs, i8imm:$rotating),
361 "alloc $dst = ar.pfs,$inputs,$locals,$outputs,$rotating;;">;
363 def MOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "mov $dst = $src;;">;
364 def PMOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src, PR:$qp),
365 "($qp) mov $dst = $src;;">;
367 def SPILL_ALL_PREDICATES_TO_GR : AForm<0x03, 0x0b, (ops GR:$dst),
369 def FILL_ALL_PREDICATES_FROM_GR : AForm<0x03, 0x0b, (ops GR:$src),
372 let isTwoAddress = 1 in {
373 def CMOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src2, GR:$src, PR:$qp),
374 "($qp) mov $dst = $src;;">;
377 def PFMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src, PR:$qp),
378 "($qp) mov $dst = $src;;">;
380 let isTwoAddress = 1 in {
381 def CFMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src2, FP:$src, PR:$qp),
382 "($qp) mov $dst = $src;;">;
385 let isTwoAddress = 1 in {
386 def TCMPNE : AForm<0x03, 0x0b,
387 (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4),
388 "cmp.ne $dst, p0 = $src3, $src4;;">;
390 def TPCMPEQOR : AForm<0x03, 0x0b,
391 (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
392 "($qp) cmp.eq.or $dst, p0 = $src3, $src4;;">;
394 def TPCMPNE : AForm<0x03, 0x0b,
395 (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
396 "($qp) cmp.ne $dst, p0 = $src3, $src4;;">;
398 def TPCMPEQ : AForm<0x03, 0x0b,
399 (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
400 "($qp) cmp.eq $dst, p0 = $src3, $src4;;">;
403 def MOVSIMM14 : AForm<0x03, 0x0b, (ops GR:$dst, s14imm:$imm),
404 "mov $dst = $imm;;">;
405 def MOVSIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, s22imm:$imm),
406 "mov $dst = $imm;;">;
407 def MOVLIMM64 : AForm<0x03, 0x0b, (ops GR:$dst, s64imm:$imm),
408 "movl $dst = $imm;;">;
410 def SHLI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
411 "shl $dst = $src1, $imm;;">;
412 def SHRUI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
413 "shr.u $dst = $src1, $imm;;">;
414 def SHRSI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
415 "shr $dst = $src1, $imm;;">;
417 def EXTRU : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2),
418 "extr.u $dst = $src1, $imm1, $imm2;;">;
420 def DEPZ : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2), "dep.z $dst = $src1, $imm1, $imm2;;">;
422 def PCMPEQOR : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
423 "($qp) cmp.eq.or $dst, p0 = $src1, $src2;;">;
424 def PCMPEQUNC : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
425 "($qp) cmp.eq.unc $dst, p0 = $src1, $src2;;">;
426 def PCMPNE : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
427 "($qp) cmp.ne $dst, p0 = $src1, $src2;;">;
430 def BCMPEQ : AForm<0x03, 0x0b, (ops PR:$dst1, PR:$dst2, GR:$src1, GR:$src2),
431 "cmp.eq $dst1, dst2 = $src1, $src2;;">;
433 def ADDIMM14 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
434 "adds $dst = $imm, $src1;;">;
436 def ADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm),
437 "add $dst = $imm, $src1;;">;
438 def CADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
439 "($qp) add $dst = $imm, $src1;;">;
441 def SUBIMM8 : AForm<0x03, 0x0b, (ops GR:$dst, s8imm:$imm, GR:$src2),
442 "sub $dst = $imm, $src2;;">;
445 def ST1 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
446 "st1 [$dstPtr] = $value;;">;
447 def ST2 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
448 "st2 [$dstPtr] = $value;;">;
449 def ST4 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
450 "st4 [$dstPtr] = $value;;">;
451 def ST8 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
452 "st8 [$dstPtr] = $value;;">;
453 def STF4 : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
454 "stfs [$dstPtr] = $value;;">;
455 def STF8 : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
456 "stfd [$dstPtr] = $value;;">;
460 def LD1 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
461 "ld1 $dst = [$srcPtr];;">;
462 def LD2 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
463 "ld2 $dst = [$srcPtr];;">;
464 def LD4 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
465 "ld4 $dst = [$srcPtr];;">;
466 def LD8 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
467 "ld8 $dst = [$srcPtr];;">;
468 def LDF4 : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
469 "ldfs $dst = [$srcPtr];;">;
470 def LDF8 : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
471 "ldfd $dst = [$srcPtr];;">;
474 def POPCNT : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src),
475 "popcnt $dst = $src;;",
476 [(set GR:$dst, (ctpop GR:$src))]>;
478 // some FP stuff: // TODO: single-precision stuff?
479 def FADD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
480 "fadd $dst = $src1, $src2;;",
481 [(set FP:$dst, (fadd FP:$src1, FP:$src2))]>;
482 def FADDS: AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
483 "fadd.s $dst = $src1, $src2;;">;
484 def FSUB : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
485 "fsub $dst = $src1, $src2;;",
486 [(set FP:$dst, (fsub FP:$src1, FP:$src2))]>;
487 def FMPY : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
488 "fmpy $dst = $src1, $src2;;",
489 [(set FP:$dst, (fmul FP:$src1, FP:$src2))]>;
490 def FMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
491 "mov $dst = $src;;">; // XXX: there _is_ no fmov
492 def FMA : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
493 "fma $dst = $src1, $src2, $src3;;",
494 [(set FP:$dst, (fadd (fmul FP:$src1, FP:$src2), FP:$src3))]>;
495 def FMS : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
496 "fms $dst = $src1, $src2, $src3;;",
497 [(set FP:$dst, (fsub (fmul FP:$src1, FP:$src2), FP:$src3))]>;
498 def FNMA : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
499 "fnma $dst = $src1, $src2, $src3;;",
500 [(set FP:$dst, (fneg (fadd (fmul FP:$src1, FP:$src2), FP:$src3)))]>;
501 def FABS : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
502 "fabs $dst = $src;;">;
503 def FNEG : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src),
504 "fneg $dst = $src;;",
505 [(set FP:$dst, (fneg FP:$src))]>;
506 def FNEGABS : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
507 "fnegabs $dst = $src;;">;
509 def CFMAS1 : AForm<0x03, 0x0b,
510 (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
511 "($qp) fma.s1 $dst = $src1, $src2, $src3;;">;
512 def CFNMAS1 : AForm<0x03, 0x0b,
513 (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
514 "($qp) fnma.s1 $dst = $src1, $src2, $src3;;">;
516 def FRCPAS1 : AForm<0x03, 0x0b, (ops FP:$dstFR, PR:$dstPR, FP:$src1, FP:$src2),
517 "frcpa.s1 $dstFR, $dstPR = $src1, $src2;;">;
519 def XMAL : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
520 "xma.l $dst = $src1, $src2, $src3;;">;
522 def FCVTXF : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
523 "fcvt.xf $dst = $src;;">;
524 def FCVTXUF : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
525 "fcvt.xuf $dst = $src;;">;
526 def FCVTXUFS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
527 "fcvt.xuf.s1 $dst = $src;;">;
528 def FCVTFX : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
529 "fcvt.fx $dst = $src;;">;
530 def FCVTFXU : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
531 "fcvt.fxu $dst = $src;;">;
533 def FCVTFXTRUNC : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
534 "fcvt.fx.trunc $dst = $src;;">;
535 def FCVTFXUTRUNC : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
536 "fcvt.fxu.trunc $dst = $src;;">;
538 def FCVTFXTRUNCS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
539 "fcvt.fx.trunc.s1 $dst = $src;;">;
540 def FCVTFXUTRUNCS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
541 "fcvt.fxu.trunc.s1 $dst = $src;;">;
543 def FNORMD : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
544 "fnorm.d $dst = $src;;">;
546 def GETFD : AForm<0x03, 0x0b, (ops GR:$dst, FP:$src),
547 "getf.d $dst = $src;;">;
548 def SETFD : AForm<0x03, 0x0b, (ops FP:$dst, GR:$src),
549 "setf.d $dst = $src;;">;
551 def GETFSIG : AForm<0x03, 0x0b, (ops GR:$dst, FP:$src),
552 "getf.sig $dst = $src;;">;
553 def SETFSIG : AForm<0x03, 0x0b, (ops FP:$dst, GR:$src),
554 "setf.sig $dst = $src;;">;
556 let isTerminator = 1, isBranch = 1 in {
557 def BRL_NOTCALL : RawForm<0x03, 0xb0, (ops i64imm:$dst),
558 "(p0) brl.cond.sptk $dst;;">;
559 def BRLCOND_NOTCALL : RawForm<0x03, 0xb0, (ops PR:$qp, i64imm:$dst),
560 "($qp) brl.cond.sptk $dst;;">;
561 def BRCOND_NOTCALL : RawForm<0x03, 0xb0, (ops PR:$qp, GR:$dst),
562 "($qp) br.cond.sptk $dst;;">;
565 let isCall = 1, isTerminator = 1, isBranch = 1,
566 Uses = [out0,out1,out2,out3,out4,out5,out6,out7],
567 // all calls clobber non-callee-saved registers, and for now, they are these:
568 Defs = [r2,r3,r8,r9,r10,r11,r14,r15,r16,r17,r18,r19,r20,r21,r22,r23,r24,
569 r25,r26,r27,r28,r29,r30,r31,
570 p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,
571 F6,F7,F8,F9,F10,F11,F12,F13,F14,F15,
572 F32,F33,F34,F35,F36,F37,F38,F39,F40,F41,F42,F43,F44,F45,F46,F47,F48,F49,
573 F50,F51,F52,F53,F54,F55,F56,
574 F57,F58,F59,F60,F61,F62,F63,F64,F65,F66,F67,F68,F69,F70,F71,F72,F73,F74,
575 F75,F76,F77,F78,F79,F80,F81,
576 F82,F83,F84,F85,F86,F87,F88,F89,F90,F91,F92,F93,F94,F95,F96,F97,F98,F99,
577 F100,F101,F102,F103,F104,F105,
578 F106,F107,F108,F109,F110,F111,F112,F113,F114,F115,F116,F117,F118,F119,
579 F120,F121,F122,F123,F124,F125,F126,F127,
580 out0,out1,out2,out3,out4,out5,out6,out7] in {
582 def BRCALL: RawForm<0x03, 0xb0, (ops calltarget:$dst),
583 "br.call.sptk rp = $dst;;">; // FIXME: teach llvm about branch regs?
585 def BRCALL_IPREL : RawForm<0x03, 0xb0, (ops calltarget:$dst, variable_ops),
586 "br.call.sptk rp = $dst;;">; // FIXME: teach llvm about branch regs?
587 def BRCALL_INDIRECT : RawForm<0x03, 0xb0, (ops GR:$branchreg, variable_ops),
588 "br.call.sptk rp = $branchreg;;">; // FIXME: teach llvm about branch regs?
589 def BRLCOND_CALL : RawForm<0x03, 0xb0, (ops PR:$qp, i64imm:$dst),
590 "($qp) brl.cond.call.sptk $dst;;">;
591 def BRCOND_CALL : RawForm<0x03, 0xb0, (ops PR:$qp, GR:$dst),
592 "($qp) br.cond.call.sptk $dst;;">;
595 let isTerminator = 1, isReturn = 1 in
596 def RET : RawForm<0x03, 0xb0, (ops), "br.ret.sptk.many rp;;">; // return