1 //===- IA64InstrInfo.td - Describe the IA64 Instruction Set -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the IA64 instruction set, defining the instructions, and
11 // properties of the instructions which are needed for code generation, machine
12 // code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 include "IA64InstrFormats.td"
18 def u6imm : Operand<i8>;
19 def s8imm : Operand<i8> {
20 let PrintMethod = "printS8ImmOperand";
22 def s14imm : Operand<i64> {
23 let PrintMethod = "printS14ImmOperand";
25 def s22imm : Operand<i32> {
26 let PrintMethod = "printS22ImmOperand";
28 def u64imm : Operand<i64> {
29 let PrintMethod = "printU64ImmOperand";
31 def s64imm : Operand<i64> {
32 let PrintMethod = "printS64ImmOperand";
35 let PrintMethod = "printGlobalOperand" in
36 def globaladdress : Operand<i64>;
38 // the asmprinter needs to know about calls
39 let PrintMethod = "printCallOperand" in
40 def calltarget : Operand<i64>;
42 /* new daggy action!!! */
44 def immSExt14 : PatLeaf<(i64 imm), [{
45 // immSExt14 predicate - True if the immediate fits in a 14-bit sign extended
46 // field. Used by instructions like 'adds'.
47 int64_t v = (int64_t)N->getValue();
48 return (v <= 8191 && v >= -8192);
51 def imm64 : PatLeaf<(i64 imm), [{
52 // imm64 predicate - True if the immediate fits in a 64-bit
53 // field - i.e., true. used to keep movl happy
57 def ADD : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
58 "add $dst = $src1, $src2;;",
59 [(set GR:$dst, (add GR:$src1, GR:$src2))]>;
61 def ADD1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
62 "add $dst = $src1, $src2, 1;;",
63 [(set GR:$dst, (add (add GR:$src1, GR:$src2), 1))]>;
65 def ADDS : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
66 "adds $dst = $imm, $src1;;",
67 [(set GR:$dst, (add GR:$src1, immSExt14:$imm))]>;
69 def MOVL : AForm_DAG<0x03, 0x0b, (ops GR:$dst, s64imm:$imm),
71 [(set GR:$dst, imm64:$imm)]>;
73 def ADDL_GA : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, globaladdress:$imm),
74 "addl $dst = $imm, $src1;;",
77 def SUB : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
78 "sub $dst = $src1, $src2;;",
79 [(set GR:$dst, (sub GR:$src1, GR:$src2))]>;
81 def SUB1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
82 "sub $dst = $src1, $src2, 1;;",
83 [(set GR:$dst, (add (sub GR: $src1, GR:$src2), -1))]>;
85 def GETFSIGD : AForm_DAG<0x03, 0x0b, (ops GR:$dst, FP:$src),
86 "getf.sig $dst = $src;;",
89 def SETFSIGD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, GR:$src),
90 "setf.sig $dst = $src;;",
93 def XMALD : AForm_DAG<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
94 "xma.l $dst = $src1, $src2, $src3;;",
97 // pseudocode for integer multiplication
98 def : Pat<(mul GR:$src1, GR:$src2),
99 (GETFSIGD (XMALD (SETFSIGD GR:$src1), (SETFSIGD GR:$src2), F0))>;
101 // TODO: addp4 (addp4 dst = src, r0 is a 32-bit add)
104 // def ADDS : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
105 // "adds $dst = $imm, $src1;;">;
107 // load constants of various sizes // FIXME: prettyprint -ve constants
108 def : Pat<(i64 immSExt14:$imm), (ADDS r0, immSExt14:$imm)>;
109 def : Pat<(i64 imm64:$imm), (MOVL imm64:$imm)>;
111 def AND : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
112 "and $dst = $src1, $src2;;",
113 [(set GR:$dst, (and GR:$src1, GR:$src2))]>;
114 def ANDCM : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
115 "andcm $dst = $src1, $src2;;",
116 [(set GR:$dst, (and GR:$src1, (not GR:$src2)))]>;
117 // TODO: and/andcm/or/xor/add/sub/shift immediate forms
118 def OR : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
119 "or $dst = $src1, $src2;;",
120 [(set GR:$dst, (or GR:$src1, GR:$src2))]>;
122 def pOR : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2, PR:$qp),
123 "($qp) or $dst = $src1, $src2;;">;
125 def PCMPEQUNCR0R0 : AForm<0x03, 0x0b, (ops PR:$dst, PR:$qp),
126 "($qp) cmp.eq.unc $dst, p0 = r0, r0;;">;
128 let isTwoAddress=1 in
129 def TPCMPEQR0R0 : AForm<0x03, 0x0b, (ops PR:$dst, PR:$bogus, PR:$qp),
130 "($qp) cmp.eq $dst, p0 = r0, r0;;">;
132 /* our pseudocode for OR on predicates is:
138 (pA) cmp.eq.unc pC,p0 = r0,r0 // pC = pA
140 (pB) cmp.eq pC,p0 = r0,r0 // if (pB) pC = 1
144 let isTwoAddress = 1 in {
145 def TPCMPEQ : AForm<0x03, 0x0b,
146 (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
147 "($qp) cmp.eq $dst, p0 = $src3, $src4;;">;
151 // FIXME: these are bogus
152 def bOR : Pat<(or PR:$src1, PR:$src2),
153 (PCMPEQUNCR0R0 PR:$src1)>;
155 def bXOR : Pat<(xor PR:$src1, PR:$src2),
156 (PCMPEQUNCR0R0 PR:$src1)>;
158 def XOR : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
159 "xor $dst = $src1, $src2;;",
160 [(set GR:$dst, (xor GR:$src1, GR:$src2))]>;
162 def SHL : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
163 "shl $dst = $src1, $src2;;",
164 [(set GR:$dst, (shl GR:$src1, GR:$src2))]>;
167 def CMPEQ : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
168 "cmp.eq $dst, p0 = $src1, $src2;;">;
169 def CMPGT : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
170 "cmp.gt $dst, p0 = $src1, $src2;;">;
171 def CMPGE : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
172 "cmp.ge $dst, p0 = $src1, $src2;;">;
173 def CMPLT : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
174 "cmp.lt $dst, p0 = $src1, $src2;;">;
175 def CMPLE : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
176 "cmp.le $dst, p0 = $src1, $src2;;">;
177 def CMPNE : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
178 "cmp.ne $dst, p0 = $src1, $src2;;">;
179 def CMPLTU : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
180 "cmp.ltu $dst, p0 = $src1, $src2;;">;
181 def CMPGTU : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
182 "cmp.gtu $dst, p0 = $src1, $src2;;">;
183 def CMPLEU : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
184 "cmp.leu $dst, p0 = $src1, $src2;;">;
185 def CMPGEU : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
186 "cmp.geu $dst, p0 = $src1, $src2;;">;
189 // the following are all a bit unfortunate: we throw away the complement
191 def CMPEQ : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
192 "cmp.eq $dst, p0 = $src1, $src2;;",
193 [(set PR:$dst, (seteq GR:$src1, GR:$src2))]>;
194 def CMPGT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
195 "cmp.gt $dst, p0 = $src1, $src2;;",
196 [(set PR:$dst, (setgt GR:$src1, GR:$src2))]>;
197 def CMPGE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
198 "cmp.ge $dst, p0 = $src1, $src2;;",
199 [(set PR:$dst, (setge GR:$src1, GR:$src2))]>;
200 def CMPLT : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
201 "cmp.lt $dst, p0 = $src1, $src2;;",
202 [(set PR:$dst, (setlt GR:$src1, GR:$src2))]>;
203 def CMPLE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
204 "cmp.le $dst, p0 = $src1, $src2;;",
205 [(set PR:$dst, (setle GR:$src1, GR:$src2))]>;
206 def CMPNE : AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
207 "cmp.ne $dst, p0 = $src1, $src2;;",
208 [(set PR:$dst, (setne GR:$src1, GR:$src2))]>;
209 def CMPLTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
210 "cmp.eq $dst, p0 = $src1, $src2;;",
211 [(set PR:$dst, (setult GR:$src1, GR:$src2))]>;
212 def CMPGTU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
213 "cmp.eq $dst, p0 = $src1, $src2;;",
214 [(set PR:$dst, (setugt GR:$src1, GR:$src2))]>;
215 def CMPLEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
216 "cmp.eq $dst, p0 = $src1, $src2;;",
217 [(set PR:$dst, (setule GR:$src1, GR:$src2))]>;
218 def CMPGEU: AForm_DAG<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2),
219 "cmp.eq $dst, p0 = $src1, $src2;;",
220 [(set PR:$dst, (setuge GR:$src1, GR:$src2))]>;
222 // FIXME: tabelgen doesn't know that zxt1 is cheaper on ia64 than "andi",
223 // need to fix this one day
225 def SXT1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt1 $dst = $src;;",
226 [(set GR:$dst, (sext_inreg GR:$src, i8))]>;
227 def ZXT1 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt1 $dst = $src;;",
228 [(set GR:$dst, (and GR:$src, 255))]>;
229 def SXT2 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt2 $dst = $src;;",
230 [(set GR:$dst, (sext_inreg GR:$src, i16))]>;
231 def ZXT2 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt2 $dst = $src;;",
232 [(set GR:$dst, (and GR:$src, 65535))]>;
233 def SXT4 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt4 $dst = $src;;",
234 [(set GR:$dst, (sext_inreg GR:$src, i32))]>;
235 def ZXT4 : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt4 $dst = $src;;",
236 [(set GR:$dst, (and GR:$src, 1341835918))]>; // hehhehe NO - FIXME
238 // TODO: support postincrement (reg, imm9) loads+stores - this needs more
241 def PHI : PseudoInstIA64<(ops variable_ops), "PHI">;
242 def IDEF : PseudoInstIA64<(ops variable_ops), "// IDEF">;
243 def IUSE : PseudoInstIA64<(ops variable_ops), "// IUSE">;
244 def ADJUSTCALLSTACKUP : PseudoInstIA64<(ops variable_ops),
245 "// ADJUSTCALLSTACKUP">;
246 def ADJUSTCALLSTACKDOWN : PseudoInstIA64<(ops variable_ops),
247 "// ADJUSTCALLSTACKDOWN">;
248 def PSEUDO_ALLOC : PseudoInstIA64<(ops GR:$foo), "// PSEUDO_ALLOC">;
250 def ALLOC : AForm<0x03, 0x0b,
251 (ops GR:$dst, i8imm:$inputs, i8imm:$locals, i8imm:$outputs, i8imm:$rotating),
252 "alloc $dst = ar.pfs,$inputs,$locals,$outputs,$rotating;;">;
254 def MOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "mov $dst = $src;;">;
255 def PMOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src, PR:$qp),
256 "($qp) mov $dst = $src;;">;
258 def SPILL_ALL_PREDICATES_TO_GR : AForm<0x03, 0x0b, (ops GR:$dst),
260 def FILL_ALL_PREDICATES_FROM_GR : AForm<0x03, 0x0b, (ops GR:$src),
263 let isTwoAddress = 1 in {
264 def CMOV : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src2, GR:$src, PR:$qp),
265 "($qp) mov $dst = $src;;">;
268 def PFMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src, PR:$qp),
269 "($qp) mov $dst = $src;;">;
271 let isTwoAddress = 1 in {
272 def CFMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src2, FP:$src, PR:$qp),
273 "($qp) mov $dst = $src;;">;
276 let isTwoAddress = 1 in {
277 def TCMPNE : AForm<0x03, 0x0b,
278 (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4),
279 "cmp.ne $dst, p0 = $src3, $src4;;">;
281 def TPCMPEQOR : AForm<0x03, 0x0b,
282 (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
283 "($qp) cmp.eq.or $dst, p0 = $src3, $src4;;">;
285 def TPCMPNE : AForm<0x03, 0x0b,
286 (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
287 "($qp) cmp.ne $dst, p0 = $src3, $src4;;">;
289 def TPCMPEQ : AForm<0x03, 0x0b,
290 (ops PR:$dst, PR:$src2, GR:$src3, GR:$src4, PR:$qp),
291 "($qp) cmp.eq $dst, p0 = $src3, $src4;;">;
294 def MOVSIMM14 : AForm<0x03, 0x0b, (ops GR:$dst, s14imm:$imm),
295 "mov $dst = $imm;;">;
296 def MOVSIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, s22imm:$imm),
297 "mov $dst = $imm;;">;
298 def MOVLIMM64 : AForm<0x03, 0x0b, (ops GR:$dst, s64imm:$imm),
299 "movl $dst = $imm;;">;
302 def AND : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
303 "and $dst = $src1, $src2;;">;
304 def OR : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
305 "or $dst = $src1, $src2;;">;
306 def XOR : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
307 "xor $dst = $src1, $src2;;">;
308 def SHL : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
309 "shl $dst = $src1, $src2;;">;
311 def SHLI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
312 "shl $dst = $src1, $imm;;">;
313 def SHRU : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
314 "shr.u $dst = $src1, $src2;;">;
315 def SHRUI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
316 "shr.u $dst = $src1, $imm;;">;
317 def SHRS : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
318 "shr $dst = $src1, $src2;;">;
319 def SHRSI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
320 "shr $dst = $src1, $imm;;">;
322 def SHLADD : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm, GR:$src2),
323 "shladd $dst = $src1, $imm, $src2;;">;
325 def EXTRU : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2),
326 "extr.u $dst = $src1, $imm1, $imm2;;">;
328 def DEPZ : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2), "dep.z $dst = $src1, $imm1, $imm2;;">;
331 def SXT1 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt1 $dst = $src;;">;
332 def ZXT1 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt1 $dst = $src;;">;
333 def SXT2 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt2 $dst = $src;;">;
334 def ZXT2 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt2 $dst = $src;;">;
335 def SXT4 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "sxt4 $dst = $src;;">;
336 def ZXT4 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "zxt4 $dst = $src;;">;
339 // and we do the whole thing again for FP compares!
340 def FCMPEQ : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
341 "fcmp.eq $dst, p0 = $src1, $src2;;">;
342 def FCMPGT : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
343 "fcmp.gt $dst, p0 = $src1, $src2;;">;
344 def FCMPGE : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
345 "fcmp.ge $dst, p0 = $src1, $src2;;">;
346 def FCMPLT : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
347 "fcmp.lt $dst, p0 = $src1, $src2;;">;
348 def FCMPLE : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
349 "fcmp.le $dst, p0 = $src1, $src2;;">;
350 def FCMPNE : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
351 "fcmp.neq $dst, p0 = $src1, $src2;;">;
352 def FCMPLTU : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
353 "fcmp.ltu $dst, p0 = $src1, $src2;;">;
354 def FCMPGTU : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
355 "fcmp.gtu $dst, p0 = $src1, $src2;;">;
356 def FCMPLEU : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
357 "fcmp.leu $dst, p0 = $src1, $src2;;">;
358 def FCMPGEU : AForm<0x03, 0x0b, (ops PR:$dst, FP:$src1, FP:$src2),
359 "fcmp.geu $dst, p0 = $src1, $src2;;">;
361 def PCMPEQOR : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
362 "($qp) cmp.eq.or $dst, p0 = $src1, $src2;;">;
363 def PCMPEQUNC : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
364 "($qp) cmp.eq.unc $dst, p0 = $src1, $src2;;">;
365 def PCMPNE : AForm<0x03, 0x0b, (ops PR:$dst, GR:$src1, GR:$src2, PR:$qp),
366 "($qp) cmp.ne $dst, p0 = $src1, $src2;;">;
369 def BCMPEQ : AForm<0x03, 0x0b, (ops PR:$dst1, PR:$dst2, GR:$src1, GR:$src2),
370 "cmp.eq $dst1, dst2 = $src1, $src2;;">;
372 def ADDIMM14 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
373 "adds $dst = $imm, $src1;;">;
375 def ADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm),
376 "add $dst = $imm, $src1;;">;
377 def CADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
378 "($qp) add $dst = $imm, $src1;;">;
380 let isTwoAddress = 1 in {
381 def TPCADDIMM22 : AForm<0x03, 0x0b,
382 (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
383 "($qp) add $dst = $imm, $dst;;">;
384 def TPCMPIMM8NE : AForm<0x03, 0x0b,
385 (ops PR:$dst, PR:$src1, s22imm:$imm, GR:$src2, PR:$qp),
386 "($qp) cmp.ne $dst , p0 = $imm, $src2;;">;
389 def SUBIMM8 : AForm<0x03, 0x0b, (ops GR:$dst, s8imm:$imm, GR:$src2),
390 "sub $dst = $imm, $src2;;">;
392 def ST1 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
393 "st1 [$dstPtr] = $value;;">;
394 def ST2 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
395 "st2 [$dstPtr] = $value;;">;
396 def ST4 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
397 "st4 [$dstPtr] = $value;;">;
398 def ST8 : AForm<0x03, 0x0b, (ops GR:$dstPtr, GR:$value),
399 "st8 [$dstPtr] = $value;;">;
401 def LD1 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
402 "ld1 $dst = [$srcPtr];;">;
403 def LD2 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
404 "ld2 $dst = [$srcPtr];;">;
405 def LD4 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
406 "ld4 $dst = [$srcPtr];;">;
407 def LD8 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$srcPtr),
408 "ld8 $dst = [$srcPtr];;">;
410 def POPCNT : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src), "popcnt $dst = $src;;">;
413 def FADD : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
414 "fadd $dst = $src1, $src2;;">;
415 def FADDS: AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
416 "fadd.s $dst = $src1, $src2;;">;
417 def FSUB : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
418 "fsub $dst = $src1, $src2;;">;
419 def FMPY : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2),
420 "fmpy $dst = $src1, $src2;;">;
421 def FMOV : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
422 "mov $dst = $src;;">; // XXX: there _is_ no fmov
423 def FMA : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
424 "fma $dst = $src1, $src2, $src3;;">;
425 def FMS : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
426 "fms $dst = $src1, $src2, $src3;;">;
427 def FNMA : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
428 "fnma $dst = $src1, $src2, $src3;;">;
429 def FABS : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
430 "fabs $dst = $src;;">;
431 def FNEG : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
432 "fneg $dst = $src;;">;
433 def FNEGABS : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
434 "fnegabs $dst = $src;;">;
436 def CFMAS1 : AForm<0x03, 0x0b,
437 (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
438 "($qp) fma.s1 $dst = $src1, $src2, $src3;;">;
439 def CFNMAS1 : AForm<0x03, 0x0b,
440 (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),
441 "($qp) fnma.s1 $dst = $src1, $src2, $src3;;">;
443 def FRCPAS1 : AForm<0x03, 0x0b, (ops FP:$dstFR, PR:$dstPR, FP:$src1, FP:$src2),
444 "frcpa.s1 $dstFR, $dstPR = $src1, $src2;;">;
446 def XMAL : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
447 "xma.l $dst = $src1, $src2, $src3;;">;
449 def FCVTXF : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
450 "fcvt.xf $dst = $src;;">;
451 def FCVTXUF : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
452 "fcvt.xuf $dst = $src;;">;
453 def FCVTXUFS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
454 "fcvt.xuf.s1 $dst = $src;;">;
455 def FCVTFX : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
456 "fcvt.fx $dst = $src;;">;
457 def FCVTFXU : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
458 "fcvt.fxu $dst = $src;;">;
460 def FCVTFXTRUNC : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
461 "fcvt.fx.trunc $dst = $src;;">;
462 def FCVTFXUTRUNC : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
463 "fcvt.fxu.trunc $dst = $src;;">;
465 def FCVTFXTRUNCS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
466 "fcvt.fx.trunc.s1 $dst = $src;;">;
467 def FCVTFXUTRUNCS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
468 "fcvt.fxu.trunc.s1 $dst = $src;;">;
470 def FNORMD : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
471 "fnorm.d $dst = $src;;">;
473 def GETFD : AForm<0x03, 0x0b, (ops GR:$dst, FP:$src),
474 "getf.d $dst = $src;;">;
475 def SETFD : AForm<0x03, 0x0b, (ops FP:$dst, GR:$src),
476 "setf.d $dst = $src;;">;
478 def GETFSIG : AForm<0x03, 0x0b, (ops GR:$dst, FP:$src),
479 "getf.sig $dst = $src;;">;
480 def SETFSIG : AForm<0x03, 0x0b, (ops FP:$dst, GR:$src),
481 "setf.sig $dst = $src;;">;
483 def LDF4 : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
484 "ldfs $dst = [$srcPtr];;">;
485 def LDF8 : AForm<0x03, 0x0b, (ops FP:$dst, GR:$srcPtr),
486 "ldfd $dst = [$srcPtr];;">;
488 def STF4 : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
489 "stfs [$dstPtr] = $value;;">;
490 def STF8 : AForm<0x03, 0x0b, (ops GR:$dstPtr, FP:$value),
491 "stfd [$dstPtr] = $value;;">;
493 let isTerminator = 1, isBranch = 1 in {
494 def BRL_NOTCALL : RawForm<0x03, 0xb0, (ops i64imm:$dst),
495 "(p0) brl.cond.sptk $dst;;">;
496 def BRLCOND_NOTCALL : RawForm<0x03, 0xb0, (ops PR:$qp, i64imm:$dst),
497 "($qp) brl.cond.sptk $dst;;">;
498 def BRCOND_NOTCALL : RawForm<0x03, 0xb0, (ops PR:$qp, GR:$dst),
499 "($qp) br.cond.sptk $dst;;">;
502 let isCall = 1, isTerminator = 1, isBranch = 1,
503 Uses = [out0,out1,out2,out3,out4,out5,out6,out7],
504 // all calls clobber non-callee-saved registers, and for now, they are these:
505 Defs = [r2,r3,r8,r9,r10,r11,r14,r15,r16,r17,r18,r19,r20,r21,r22,r23,r24,
506 r25,r26,r27,r28,r29,r30,r31,
507 p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,
508 F6,F7,F8,F9,F10,F11,F12,F13,F14,F15,
509 F32,F33,F34,F35,F36,F37,F38,F39,F40,F41,F42,F43,F44,F45,F46,F47,F48,F49,
510 F50,F51,F52,F53,F54,F55,F56,
511 F57,F58,F59,F60,F61,F62,F63,F64,F65,F66,F67,F68,F69,F70,F71,F72,F73,F74,
512 F75,F76,F77,F78,F79,F80,F81,
513 F82,F83,F84,F85,F86,F87,F88,F89,F90,F91,F92,F93,F94,F95,F96,F97,F98,F99,
514 F100,F101,F102,F103,F104,F105,
515 F106,F107,F108,F109,F110,F111,F112,F113,F114,F115,F116,F117,F118,F119,
516 F120,F121,F122,F123,F124,F125,F126,F127,
517 out0,out1,out2,out3,out4,out5,out6,out7] in {
519 def BRCALL: RawForm<0x03, 0xb0, (ops calltarget:$dst),
520 "br.call.sptk rp = $dst;;">; // FIXME: teach llvm about branch regs?
522 def BRCALL_IPREL : RawForm<0x03, 0xb0, (ops calltarget:$dst, variable_ops),
523 "br.call.sptk rp = $dst;;">; // FIXME: teach llvm about branch regs?
524 def BRCALL_INDIRECT : RawForm<0x03, 0xb0, (ops GR:$branchreg, variable_ops),
525 "br.call.sptk rp = $branchreg;;">; // FIXME: teach llvm about branch regs?
526 def BRLCOND_CALL : RawForm<0x03, 0xb0, (ops PR:$qp, i64imm:$dst),
527 "($qp) brl.cond.call.sptk $dst;;">;
528 def BRCOND_CALL : RawForm<0x03, 0xb0, (ops PR:$qp, GR:$dst),
529 "($qp) br.cond.call.sptk $dst;;">;
532 let isTerminator = 1, isReturn = 1 in
533 def RET : RawForm<0x03, 0xb0, (ops), "br.ret.sptk.many rp;;">; // return