1 //===- IA64RegisterInfo.cpp - IA64 Register Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the IA64 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on IA64.
13 //===----------------------------------------------------------------------===//
16 #include "IA64RegisterInfo.h"
17 #include "IA64InstrBuilder.h"
18 #include "IA64MachineFunctionInfo.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Type.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineLocation.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/Target/TargetFrameInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Target/TargetInstrInfo.h"
31 #include "llvm/ADT/BitVector.h"
32 #include "llvm/ADT/STLExtras.h"
35 IA64RegisterInfo::IA64RegisterInfo(const TargetInstrInfo &tii)
36 : IA64GenRegisterInfo(IA64::ADJUSTCALLSTACKDOWN, IA64::ADJUSTCALLSTACKUP),
39 void IA64RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
40 MachineBasicBlock::iterator I,
42 const MachineInstr *Orig) const {
43 MachineInstr *MI = Orig->clone();
44 MI->getOperand(0).setReg(DestReg);
48 const unsigned* IA64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
50 static const unsigned CalleeSavedRegs[] = {
53 return CalleeSavedRegs;
56 const TargetRegisterClass* const*
57 IA64RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
58 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
61 return CalleeSavedRegClasses;
64 BitVector IA64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
65 BitVector Reserved(getNumRegs());
66 Reserved.set(IA64::r0);
67 Reserved.set(IA64::r1);
68 Reserved.set(IA64::r2);
69 Reserved.set(IA64::r5);
70 Reserved.set(IA64::r12);
71 Reserved.set(IA64::r13);
72 Reserved.set(IA64::r22);
73 Reserved.set(IA64::rp);
77 //===----------------------------------------------------------------------===//
78 // Stack Frame Processing methods
79 //===----------------------------------------------------------------------===//
81 // hasFP - Return true if the specified function should have a dedicated frame
82 // pointer register. This is true if the function has variable sized allocas or
83 // if frame pointer elimination is disabled.
85 bool IA64RegisterInfo::hasFP(const MachineFunction &MF) const {
86 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
89 void IA64RegisterInfo::
90 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
91 MachineBasicBlock::iterator I) const {
93 // If we have a frame pointer, turn the adjcallstackup instruction into a
94 // 'sub SP, <amt>' and the adjcallstackdown instruction into 'add SP,
96 MachineInstr *Old = I;
97 unsigned Amount = Old->getOperand(0).getImm();
99 // We need to keep the stack aligned properly. To do this, we round the
100 // amount of space needed for the outgoing arguments up to the next
101 // alignment boundary.
102 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
103 Amount = (Amount+Align-1)/Align*Align;
106 if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) {
107 New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
110 assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP);
111 New=BuildMI(TII.get(IA64::ADDIMM22), IA64::r12).addReg(IA64::r12)
115 // Replace the pseudo instruction with a new instruction...
123 void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
124 int SPAdj, RegScavenger *RS)const{
125 assert(SPAdj == 0 && "Unexpected");
128 MachineInstr &MI = *II;
129 MachineBasicBlock &MBB = *MI.getParent();
130 MachineFunction &MF = *MBB.getParent();
134 while (!MI.getOperand(i).isFrameIndex()) {
136 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
139 int FrameIndex = MI.getOperand(i).getIndex();
141 // choose a base register: ( hasFP? framepointer : stack pointer )
142 unsigned BaseRegister = FP ? IA64::r5 : IA64::r12;
143 // Add the base register
144 MI.getOperand(i).ChangeToRegister(BaseRegister, false);
146 // Now add the frame object offset to the offset from r1.
147 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
149 // If we're not using a Frame Pointer that has been set to the value of the
150 // SP before having the stack size subtracted from it, then add the stack size
151 // to Offset to get the correct offset.
152 Offset += MF.getFrameInfo()->getStackSize();
154 // XXX: we use 'r22' as another hack+slash temporary register here :(
155 if (Offset <= 8191 && Offset >= -8192) { // smallish offset
157 MI.getOperand(i).ChangeToRegister(IA64::r22, false);
159 MachineInstr* nMI=BuildMI(TII.get(IA64::ADDIMM22), IA64::r22)
160 .addReg(BaseRegister).addImm(Offset);
164 MI.getOperand(i).ChangeToRegister(IA64::r22, false);
166 nMI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(Offset);
168 nMI=BuildMI(TII.get(IA64::ADD), IA64::r22).addReg(BaseRegister)
175 void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
176 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
177 MachineBasicBlock::iterator MBBI = MBB.begin();
178 MachineFrameInfo *MFI = MF.getFrameInfo();
182 // first, we handle the 'alloc' instruction, that should be right up the
183 // top of any function
184 static const unsigned RegsInOrder[96] = { // there are 96 GPRs the
186 IA64::r32, IA64::r33, IA64::r34, IA64::r35,
187 IA64::r36, IA64::r37, IA64::r38, IA64::r39, IA64::r40, IA64::r41,
188 IA64::r42, IA64::r43, IA64::r44, IA64::r45, IA64::r46, IA64::r47,
189 IA64::r48, IA64::r49, IA64::r50, IA64::r51, IA64::r52, IA64::r53,
190 IA64::r54, IA64::r55, IA64::r56, IA64::r57, IA64::r58, IA64::r59,
191 IA64::r60, IA64::r61, IA64::r62, IA64::r63, IA64::r64, IA64::r65,
192 IA64::r66, IA64::r67, IA64::r68, IA64::r69, IA64::r70, IA64::r71,
193 IA64::r72, IA64::r73, IA64::r74, IA64::r75, IA64::r76, IA64::r77,
194 IA64::r78, IA64::r79, IA64::r80, IA64::r81, IA64::r82, IA64::r83,
195 IA64::r84, IA64::r85, IA64::r86, IA64::r87, IA64::r88, IA64::r89,
196 IA64::r90, IA64::r91, IA64::r92, IA64::r93, IA64::r94, IA64::r95,
197 IA64::r96, IA64::r97, IA64::r98, IA64::r99, IA64::r100, IA64::r101,
198 IA64::r102, IA64::r103, IA64::r104, IA64::r105, IA64::r106, IA64::r107,
199 IA64::r108, IA64::r109, IA64::r110, IA64::r111, IA64::r112, IA64::r113,
200 IA64::r114, IA64::r115, IA64::r116, IA64::r117, IA64::r118, IA64::r119,
201 IA64::r120, IA64::r121, IA64::r122, IA64::r123, IA64::r124, IA64::r125,
202 IA64::r126, IA64::r127 };
204 unsigned numStackedGPRsUsed=0;
205 for (int i=0; i != 96; i++) {
206 if (MF.getRegInfo().isPhysRegUsed(RegsInOrder[i]))
207 numStackedGPRsUsed=i+1; // (i+1 and not ++ - consider fn(fp, fp, int)
210 unsigned numOutRegsUsed=MF.getInfo<IA64FunctionInfo>()->outRegsUsed;
212 // XXX FIXME : this code should be a bit more reliable (in case there _isn't_
213 // a pseudo_alloc in the MBB)
214 unsigned dstRegOfPseudoAlloc;
215 for(MBBI = MBB.begin(); /*MBBI->getOpcode() != IA64::PSEUDO_ALLOC*/; ++MBBI) {
216 assert(MBBI != MBB.end());
217 if(MBBI->getOpcode() == IA64::PSEUDO_ALLOC) {
218 dstRegOfPseudoAlloc=MBBI->getOperand(0).getReg();
223 MI=BuildMI(TII.get(IA64::ALLOC)).addReg(dstRegOfPseudoAlloc).addImm(0). \
224 addImm(numStackedGPRsUsed).addImm(numOutRegsUsed).addImm(0);
225 MBB.insert(MBBI, MI);
227 // Get the number of bytes to allocate from the FrameInfo
228 unsigned NumBytes = MFI->getStackSize();
231 NumBytes += 8; // reserve space for the old FP
233 // Do we need to allocate space on the stack?
237 // Add 16 bytes at the bottom of the stack (scratch area)
238 // and round the size to a multiple of the alignment.
239 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
240 unsigned Size = 16 + (FP ? 8 : 0);
241 NumBytes = (NumBytes+Size+Align-1)/Align*Align;
243 // Update frame info to pretend that this is part of the stack...
244 MFI->setStackSize(NumBytes);
246 // adjust stack pointer: r12 -= numbytes
247 if (NumBytes <= 8191) {
248 MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
250 MBB.insert(MBBI, MI);
251 } else { // we use r22 as a scratch register here
252 MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(-NumBytes);
253 // FIXME: MOVLSI32 expects a _u_32imm
254 MBB.insert(MBBI, MI); // first load the decrement into r22
255 MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
256 MBB.insert(MBBI, MI); // then add (subtract) it to r12 (stack ptr)
259 // now if we need to, save the old FP and set the new
261 MI = BuildMI(TII.get(IA64::ST8)).addReg(IA64::r12).addReg(IA64::r5);
262 MBB.insert(MBBI, MI);
263 // this must be the last instr in the prolog ? (XXX: why??)
264 MI = BuildMI(TII.get(IA64::MOV), IA64::r5).addReg(IA64::r12);
265 MBB.insert(MBBI, MI);
270 void IA64RegisterInfo::emitEpilogue(MachineFunction &MF,
271 MachineBasicBlock &MBB) const {
272 const MachineFrameInfo *MFI = MF.getFrameInfo();
273 MachineBasicBlock::iterator MBBI = prior(MBB.end());
275 assert(MBBI->getOpcode() == IA64::RET &&
276 "Can only insert epilog into returning blocks");
280 // Get the number of bytes allocated from the FrameInfo...
281 unsigned NumBytes = MFI->getStackSize();
283 //now if we need to, restore the old FP
286 //copy the FP into the SP (discards allocas)
287 MI=BuildMI(TII.get(IA64::MOV), IA64::r12).addReg(IA64::r5);
288 MBB.insert(MBBI, MI);
290 MI=BuildMI(TII.get(IA64::LD8), IA64::r5).addReg(IA64::r5);
291 MBB.insert(MBBI, MI);
296 if (NumBytes <= 8191) {
297 MI=BuildMI(TII.get(IA64::ADDIMM22),IA64::r12).addReg(IA64::r12).
299 MBB.insert(MBBI, MI);
301 MI=BuildMI(TII.get(IA64::MOVLIMM64), IA64::r22).addImm(NumBytes);
302 MBB.insert(MBBI, MI);
303 MI=BuildMI(TII.get(IA64::ADD), IA64::r12).addReg(IA64::r12).
305 MBB.insert(MBBI, MI);
311 unsigned IA64RegisterInfo::getRARegister() const {
312 assert(0 && "What is the return address register");
316 unsigned IA64RegisterInfo::getFrameRegister(MachineFunction &MF) const {
317 return hasFP(MF) ? IA64::r5 : IA64::r12;
320 unsigned IA64RegisterInfo::getEHExceptionRegister() const {
321 assert(0 && "What is the exception register");
325 unsigned IA64RegisterInfo::getEHHandlerRegister() const {
326 assert(0 && "What is the exception handler register");
330 int IA64RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
331 assert(0 && "What is the dwarf register number");
335 #include "IA64GenRegisterInfo.inc"