1 //===- IA64RegisterInfo.cpp - IA64 Register Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Duraid Madina and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the IA64 implementation of the MRegisterInfo class. This
11 // file is responsible for the frame pointer elimination optimization on IA64.
13 //===----------------------------------------------------------------------===//
16 #include "IA64RegisterInfo.h"
17 #include "IA64InstrBuilder.h"
18 #include "IA64MachineFunctionInfo.h"
19 #include "llvm/Constants.h"
20 #include "llvm/Type.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/Target/TargetFrameInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetOptions.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/ADT/STLExtras.h"
34 IA64RegisterInfo::IA64RegisterInfo()
35 : IA64GenRegisterInfo(IA64::ADJUSTCALLSTACKDOWN, IA64::ADJUSTCALLSTACKUP) {}
37 void IA64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
38 MachineBasicBlock::iterator MI,
39 unsigned SrcReg, int FrameIdx,
40 const TargetRegisterClass *RC) const{
42 if (RC == IA64::FPRegisterClass) {
43 BuildMI(MBB, MI, IA64::STF_SPILL, 2).addFrameIndex(FrameIdx).addReg(SrcReg);
44 } else if (RC == IA64::GRRegisterClass) {
45 BuildMI(MBB, MI, IA64::ST8, 2).addFrameIndex(FrameIdx).addReg(SrcReg);
47 else if (RC == IA64::PRRegisterClass) {
48 /* we use IA64::r2 as a temporary register for doing this hackery. */
50 BuildMI(MBB, MI, IA64::MOV, 1, IA64::r2).addReg(IA64::r0);
51 // then conditionally add 1:
52 BuildMI(MBB, MI, IA64::CADDIMM22, 3, IA64::r2).addReg(IA64::r2)
53 .addImm(1).addReg(SrcReg);
54 // and then store it to the stack
55 BuildMI(MBB, MI, IA64::ST8, 2).addFrameIndex(FrameIdx).addReg(IA64::r2);
57 "sorry, I don't know how to store this sort of reg in the stack\n");
60 void IA64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
61 MachineBasicBlock::iterator MI,
62 unsigned DestReg, int FrameIdx,
63 const TargetRegisterClass *RC)const{
65 if (RC == IA64::FPRegisterClass) {
66 BuildMI(MBB, MI, IA64::LDF_FILL, 1, DestReg).addFrameIndex(FrameIdx);
67 } else if (RC == IA64::GRRegisterClass) {
68 BuildMI(MBB, MI, IA64::LD8, 1, DestReg).addFrameIndex(FrameIdx);
69 } else if (RC == IA64::PRRegisterClass) {
70 // first we load a byte from the stack into r2, our 'predicate hackery'
72 BuildMI(MBB, MI, IA64::LD8, 1, IA64::r2).addFrameIndex(FrameIdx);
73 // then we compare it to zero. If it _is_ zero, compare-not-equal to
74 // r0 gives us 0, which is what we want, so that's nice.
75 BuildMI(MBB, MI, IA64::CMPNE, 2, DestReg).addReg(IA64::r2).addReg(IA64::r0);
77 "sorry, I don't know how to load this sort of reg from the stack\n");
80 void IA64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
81 MachineBasicBlock::iterator MI,
82 unsigned DestReg, unsigned SrcReg,
83 const TargetRegisterClass *RC) const {
85 if(RC == IA64::PRRegisterClass ) // if a bool, we use pseudocode
86 // (SrcReg) DestReg = cmp.eq.unc(r0, r0)
87 BuildMI(MBB, MI, IA64::PCMPEQUNC, 1, DestReg).addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg);
88 else // otherwise, MOV works (for both gen. regs and FP regs)
89 BuildMI(MBB, MI, IA64::MOV, 1, DestReg).addReg(SrcReg);
92 //===----------------------------------------------------------------------===//
93 // Stack Frame Processing methods
94 //===----------------------------------------------------------------------===//
96 // hasFP - Return true if the specified function should have a dedicated frame
97 // pointer register. This is true if the function has variable sized allocas or
98 // if frame pointer elimination is disabled.
100 static bool hasFP(MachineFunction &MF) {
101 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
104 void IA64RegisterInfo::
105 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
106 MachineBasicBlock::iterator I) const {
109 // If we have a frame pointer, turn the adjcallstackup instruction into a
110 // 'sub SP, <amt>' and the adjcallstackdown instruction into 'add SP,
112 MachineInstr *Old = I;
113 unsigned Amount = Old->getOperand(0).getImmedValue();
115 // We need to keep the stack aligned properly. To do this, we round the
116 // amount of space needed for the outgoing arguments up to the next
117 // alignment boundary.
118 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
119 Amount = (Amount+Align-1)/Align*Align;
122 if (Old->getOpcode() == IA64::ADJUSTCALLSTACKDOWN) {
123 New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
126 assert(Old->getOpcode() == IA64::ADJUSTCALLSTACKUP);
127 New=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12)
131 // Replace the pseudo instruction with a new instruction...
139 void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
141 MachineInstr &MI = *II;
142 MachineBasicBlock &MBB = *MI.getParent();
143 MachineFunction &MF = *MBB.getParent();
147 while (!MI.getOperand(i).isFrameIndex()) {
149 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
152 int FrameIndex = MI.getOperand(i).getFrameIndex();
154 // choose a base register: ( hasFP? framepointer : stack pointer )
155 unsigned BaseRegister = FP ? IA64::r15 : IA64::r12;
156 // Add the base register
157 MI.SetMachineOperandReg(i, BaseRegister);
159 // Now add the frame object offset to the offset from r1.
160 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
162 // If we're not using a Frame Pointer that has been set to the value of the
163 // SP before having the stack size subtracted from it, then add the stack size
164 // to Offset to get the correct offset.
165 Offset += MF.getFrameInfo()->getStackSize();
167 // XXX: we use 'r22' as another hack+slash temporary register here :(
168 if ( Offset <= 8191 && Offset >= -8192) { // smallish offset
170 MI.SetMachineOperandReg(i, IA64::r22);
172 MachineInstr* nMI=BuildMI(IA64::ADDIMM22, 2, IA64::r22)
173 .addReg(BaseRegister).addSImm(Offset);
177 MI.SetMachineOperandReg(i, IA64::r22);
179 nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addSImm(Offset);
181 nMI=BuildMI(IA64::ADD, 2, IA64::r22).addReg(BaseRegister)
188 void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const {
189 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
190 MachineBasicBlock::iterator MBBI = MBB.begin();
191 MachineFrameInfo *MFI = MF.getFrameInfo();
195 // first, we handle the 'alloc' instruction, that should be right up the
196 // top of any function
197 static const unsigned RegsInOrder[96] = { // there are 96 GPRs the
199 IA64::r32, IA64::r33, IA64::r34, IA64::r35,
200 IA64::r36, IA64::r37, IA64::r38, IA64::r39, IA64::r40, IA64::r41,
201 IA64::r42, IA64::r43, IA64::r44, IA64::r45, IA64::r46, IA64::r47,
202 IA64::r48, IA64::r49, IA64::r50, IA64::r51, IA64::r52, IA64::r53,
203 IA64::r54, IA64::r55, IA64::r56, IA64::r57, IA64::r58, IA64::r59,
204 IA64::r60, IA64::r61, IA64::r62, IA64::r63, IA64::r64, IA64::r65,
205 IA64::r66, IA64::r67, IA64::r68, IA64::r69, IA64::r70, IA64::r71,
206 IA64::r72, IA64::r73, IA64::r74, IA64::r75, IA64::r76, IA64::r77,
207 IA64::r78, IA64::r79, IA64::r80, IA64::r81, IA64::r82, IA64::r83,
208 IA64::r84, IA64::r85, IA64::r86, IA64::r87, IA64::r88, IA64::r89,
209 IA64::r90, IA64::r91, IA64::r92, IA64::r93, IA64::r94, IA64::r95,
210 IA64::r96, IA64::r97, IA64::r98, IA64::r99, IA64::r100, IA64::r101,
211 IA64::r102, IA64::r103, IA64::r104, IA64::r105, IA64::r106, IA64::r107,
212 IA64::r108, IA64::r109, IA64::r110, IA64::r111, IA64::r112, IA64::r113,
213 IA64::r114, IA64::r115, IA64::r116, IA64::r117, IA64::r118, IA64::r119,
214 IA64::r120, IA64::r121, IA64::r122, IA64::r123, IA64::r124, IA64::r125,
215 IA64::r126, IA64::r127 };
217 unsigned numStackedGPRsUsed=0;
218 for(int i=0; i<96; i++) {
219 if(MF.isPhysRegUsed(RegsInOrder[i]))
220 numStackedGPRsUsed=i+1; // (i+1 and not ++ - consider fn(fp, fp, int)
223 unsigned numOutRegsUsed=MF.getInfo<IA64FunctionInfo>()->outRegsUsed;
225 // XXX FIXME : this code should be a bit more reliable (in case there _isn't_ a pseudo_alloc in the MBB)
226 unsigned dstRegOfPseudoAlloc;
227 for(MBBI = MBB.begin(); /*MBBI->getOpcode() != IA64::PSEUDO_ALLOC*/; ++MBBI) {
228 assert(MBBI != MBB.end());
229 if(MBBI->getOpcode() == IA64::PSEUDO_ALLOC) {
230 dstRegOfPseudoAlloc=MBBI->getOperand(0).getReg();
235 MI=BuildMI(IA64::ALLOC,5).addReg(dstRegOfPseudoAlloc).addImm(0).\
236 addImm(numStackedGPRsUsed).addImm(numOutRegsUsed).addImm(0);
237 MBB.insert(MBBI, MI);
239 // Get the number of bytes to allocate from the FrameInfo
240 unsigned NumBytes = MFI->getStackSize();
242 if (MFI->hasCalls() && !FP) {
243 // We reserve argument space for call sites in the function immediately on
244 // entry to the current function. This eliminates the need for add/sub
245 // brackets around call sites.
246 NumBytes += MFI->getMaxCallFrameSize();
250 NumBytes += 8; // reserve space for the old FP
252 // Do we need to allocate space on the stack?
256 // Add 16 bytes at the bottom of the stack (scratch area)
257 // and round the size to a multiple of the alignment.
258 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
259 unsigned Size = 16 + (FP ? 8 : 0);
260 NumBytes = (NumBytes+Size+Align-1)/Align*Align;
262 // Update frame info to pretend that this is part of the stack...
263 MFI->setStackSize(NumBytes);
265 // adjust stack pointer: r12 -= numbytes
266 if (NumBytes <= 8191) {
267 MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(-NumBytes);
268 MBB.insert(MBBI, MI);
269 } else { // we use r22 as a scratch register here
270 MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addSImm(-NumBytes);
271 // FIXME: MOVLSI32 expects a _u_32imm
272 MBB.insert(MBBI, MI); // first load the decrement into r22
273 MI=BuildMI(IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
274 MBB.insert(MBBI, MI); // then add (subtract) it to r12 (stack ptr)
277 // now if we need to, save the old FP and set the new
279 MI = BuildMI(IA64::ST8, 2).addReg(IA64::r12).addReg(IA64::r15);
280 MBB.insert(MBBI, MI);
281 // this must be the last instr in the prolog ? (XXX: why??)
282 MI = BuildMI(IA64::MOV, 1, IA64::r15).addReg(IA64::r12);
283 MBB.insert(MBBI, MI);
288 void IA64RegisterInfo::emitEpilogue(MachineFunction &MF,
289 MachineBasicBlock &MBB) const {
290 const MachineFrameInfo *MFI = MF.getFrameInfo();
291 MachineBasicBlock::iterator MBBI = prior(MBB.end());
293 assert(MBBI->getOpcode() == IA64::RET &&
294 "Can only insert epilog into returning blocks");
298 // Get the number of bytes allocated from the FrameInfo...
299 unsigned NumBytes = MFI->getStackSize();
301 //now if we need to, restore the old FP
304 //copy the FP into the SP (discards allocas)
305 MI=BuildMI(IA64::MOV, 1, IA64::r12).addReg(IA64::r15);
306 MBB.insert(MBBI, MI);
308 MI=BuildMI(IA64::LD8, 1, IA64::r15).addReg(IA64::r15);
309 MBB.insert(MBBI, MI);
314 if (NumBytes <= 8191) {
315 MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(NumBytes);
316 MBB.insert(MBBI, MI);
318 MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(NumBytes);
319 MBB.insert(MBBI, MI);
320 MI=BuildMI(IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
321 MBB.insert(MBBI, MI);
327 #include "IA64GenRegisterInfo.inc"